From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::244; helo=mail-it0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x244.google.com (mail-it0-x244.google.com [IPv6:2607:f8b0:4001:c0b::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 988CF223FCF3C for ; Thu, 15 Mar 2018 01:02:35 -0700 (PDT) Received: by mail-it0-x244.google.com with SMTP id e64-v6so8034338ita.5 for ; Thu, 15 Mar 2018 01:08:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=W7Y33fb8nZvSxVF+GnWqxMbMT+IJ8Pw+50yV0dltWzY=; b=A/JMJarNzGnniKMbyvRhc6KnfjgoUlJkmg+Yu6KqE3HVz/qjgrZiFixu+sgU7MXdQ7 RNPXosw2nc9UVL3tqc/rHQ6NC0upF2D7biSgJDXc6eilaY9qA/E1iSo+ENLjmN9+DGr8 LUzRLFvqMep21NmVa222ZnfTrw4JcVZDn+nmk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=W7Y33fb8nZvSxVF+GnWqxMbMT+IJ8Pw+50yV0dltWzY=; b=IWl/jLHpH+szDQ94bWdIUYvRZLgmX3OLrOiTUzQ240nvJ5idLbstL8NiKmz6DGQVzt UM4FkqkRt3tEi/SYDXk+IS38quVW3/7lE8Gtqnrckg5p/ZXXn6+dThi6DIygqnoGeQsq Ob1PofGt79UxTuysqofsnIfeW9fhL2Wp7KKLHbOT4QNlFtCnzGDD2Qnk1O/l8o9/jHiF rpwKzCH43tOogUTkNSUZRwhoCC4CygiompXwNP8SGSt5TH1+8FAb4mG2JZ1GhJwZgNNT YhNRhsO5/CpV+z/U2+4Aal3VtIYCzd29BJuzLLWEIGI+p7WHD+xwk7kp4XSzL4du9RKt 1t5Q== X-Gm-Message-State: AElRT7GQkT3HeUmwAw/fchdTt2Xi1JD0MuQeAfOCwoT0QOdyO7Ra6pJb rLjKEdELQFN2hjfZ81p6aObFa4qp/FUaNurICWeZXA== X-Google-Smtp-Source: AG47ELux3qyDQS0J0t35lZA3grUTVsn16WUtkU3cCEad8inK7PkTlacW8AhXvvwd1VE8bWGSBET3wwgysS6o4S2c6wA= X-Received: by 10.36.60.216 with SMTP id m207mr5204176ita.68.1521101338698; Thu, 15 Mar 2018 01:08:58 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.138.209 with HTTP; Thu, 15 Mar 2018 01:08:58 -0700 (PDT) In-Reply-To: <1521098263-52823-2-git-send-email-heyi.guo@linaro.org> References: <1521098263-52823-1-git-send-email-heyi.guo@linaro.org> <1521098263-52823-2-git-send-email-heyi.guo@linaro.org> From: Ard Biesheuvel Date: Thu, 15 Mar 2018 08:08:58 +0000 Message-ID: To: Heyi Guo Cc: "edk2-devel@lists.01.org" , Yi Li , Leif Lindholm , Marc Zyngier Subject: Re: [PATCH v3 1/1] ArmPkg/TimerDxe: Add ISB for timer compare value reload X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Mar 2018 08:02:36 -0000 Content-Type: text/plain; charset="UTF-8" On 15 March 2018 at 07:17, Heyi Guo wrote: > If timer interrupt is level sensitive, reloading timer compare > register has a side effect of clearing GIC pending status, so a "ISB" > is needed to make sure this instruction is executed before enabling > CPU IRQ, or else we may get spurious timer interrupts. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Heyi Guo > Signed-off-by: Yi Li > Acked-by: Marc Zyngier > Cc: Leif Lindholm > Cc: Ard Biesheuvel > Cc: Marc Zyngier Reviewed-by: Ard Biesheuvel Pushed as ac9b530e6b47 Thanks > --- > > Notes: > v3: > - Move ISB after enabling timer [Marc] > > v2: > - Use ISB instead of DSB [Marc] > - Update commit message accordingly. > > ArmPkg/Drivers/TimerDxe/TimerDxe.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/TimerDxe.c > index 33d7c922221f..a3202fa056f3 100644 > --- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c > +++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c > @@ -338,6 +338,7 @@ TimerInterruptHandler ( > // Set next compare value > ArmGenericTimerSetCompareVal (CompareValue); > ArmGenericTimerEnableTimer (); > + ArmInstructionSynchronizationBarrier (); > } > > gBS->RestoreTPL (OriginalTPL); > -- > 2.7.4 >