From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::244; helo=mail-io0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x244.google.com (mail-io0-x244.google.com [IPv6:2607:f8b0:4001:c06::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 03E8122183C9C for ; Fri, 1 Dec 2017 09:49:29 -0800 (PST) Received: by mail-io0-x244.google.com with SMTP id t196so12126428iof.0 for ; Fri, 01 Dec 2017 09:53:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=5zoxETMN0n59Wkn4lQ0nC8WW/bjKqAdkMwuxYpOQE8c=; b=GTytJ7h6pEBcK87oQx+W8XDMHHO3KsNumx7p9JBpVyx9CiyS83sC0Z7y/PBmzFUFdh XyoRW7dq6I+yoWMiBDNRmfyo2ORMa2+Pc4evQiwMYSmIxTb96gnMklS17ux6QIBZaeS4 wHajEueL0kGfiVN1hzbCXL0m+WBYXV4o08m3A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=5zoxETMN0n59Wkn4lQ0nC8WW/bjKqAdkMwuxYpOQE8c=; b=JwCStp06083KzBzfVS3B7le1OkfddMfpqZBEPZTYgIzWgEMIJ0C49AvbGUhg9VjDvC pNeboRERVk2ez+/hshzZuHyez3eQHa0gAzJ8Jf0t7LxeEDs4jSCfivyF7Y0B0R5kNoMZ QOJcT2fAt3Z+IbJvW49fvvxe/uZfF7+ElrkdQobNjAmG2VahQhoZCWQveqZCAtq26sB8 IeeB+mulCNrLs1I/kelD8tLuoU5vZ8NqOiChkZPtf/chcJDrcqvZkSlFV+Eax4ox/7Cp WFu26MHn7aNfjy7ACzPreK9cd6hA5KQHAPJN/PN2WtYM6ZRn1tWh81cDXDZiL/upW5cR j2Bg== X-Gm-Message-State: AJaThX54u3to50/ypqQ6SOXkiixHzx/4fqkBiTUsHKm48g5jyMOBTSu2 iAKhzwCTwAuAnqTQbV1Fu+FksyHB++SGqz5A57kQFjm6 X-Google-Smtp-Source: AGs4zMbT/l83BqucliyczMKlcD8G6iPOrvkYFtFsp8sSaiIz7AAUKmcYfSq+Z7BQ/Xb/65uod5AaR/EIUcmDtgt6G+M= X-Received: by 10.107.2.137 with SMTP id 131mr14042319ioc.186.1512150835971; Fri, 01 Dec 2017 09:53:55 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.104.16 with HTTP; Fri, 1 Dec 2017 09:53:55 -0800 (PST) In-Reply-To: <20171201125719.ffca5swpw5wajlwz@bivouac.eciton.net> References: <20171130185355.20985-1-ard.biesheuvel@linaro.org> <20171201125719.ffca5swpw5wajlwz@bivouac.eciton.net> From: Ard Biesheuvel Date: Fri, 1 Dec 2017 17:53:55 +0000 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" Subject: Re: [PATCH edk2-platforms v2] Silicon/SynQuacer: enable coherent DMA for NETSEC and eMMC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Dec 2017 17:49:30 -0000 Content-Type: text/plain; charset="UTF-8" On 1 December 2017 at 12:57, Leif Lindholm wrote: > On Thu, Nov 30, 2017 at 06:53:55PM +0000, Ard Biesheuvel wrote: >> As it turns out, it is surprisingly easy to configure both the NETSEC >> and eMMC devices as cache coherent for DMA, given that they are both >> behind the same SMMU which is already configured in passthrough mode >> by the firmware running on the SCP. >> >> So update the static SMMU configuration to make memory accesses performed >> by these devices inner shareable inner/outer writeback cacheable, which >> makes them cache coherent with the CPUs. >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ard Biesheuvel > > Looks fine to me: > Reviewed-by: Leif Lindholm > (If you want to hold back for Tested-by:s, feel free to.) > Thanks. It actually depends on the patch that adds the EMMC driver stack, which depends on the SD/MMC override patches for EDK2, so it needs to wait anyway.