From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::234; helo=mail-io0-x234.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x234.google.com (mail-io0-x234.google.com [IPv6:2607:f8b0:4001:c06::234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6B10E2251212E for ; Fri, 20 Apr 2018 01:34:47 -0700 (PDT) Received: by mail-io0-x234.google.com with SMTP id d6-v6so9710223iog.1 for ; Fri, 20 Apr 2018 01:34:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=bZgZR4Lq7JkkjiOAbKAZrg2U9a73hZzNlEh5wo3VMOs=; b=T3Tf7U23zcsjGk0bmEHD/2jl1x7I+dUrc201a+yYYcfjy6xpXT7xMZHwYizICreMRn KzXYPxvDkdWmAg4ESyrMdqqzsNSvsZjr30pLlumP+UJa+BpxU144oaxseSjfqe3kaeAT 7RBF2VMkYlDXyWBSp0oJW3Gywdo8hpOPegWZw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=bZgZR4Lq7JkkjiOAbKAZrg2U9a73hZzNlEh5wo3VMOs=; b=Ou/iYyZQbAbt2qJMhvRY6l+Gwo9ZYPK94tp8iyFTHuipICxFtke6TXUihIIf4H0UpT IaShff8QRAG+G6IGxXHCp6tUa5PuAW857whiHS/I4fbNhAxdnh6RNqrhhLo/WNcZkiqN hwbj45jy0JVCZfGR9lygWA3NueM8pAgJFO0+qqib8/PckX0CwpV9/ffKYXs3sbLehJer gedQW8mvh+IZNj5D82Ky21uGwRQSbEzk6xUdD/xzluyeKy/QFMlUoEoQytzb6iO2kCFU GGXMPnUCcsPb1kedYY9xc5gd2db6CTefygSq8v3xp6dwVGx4wJih4Sic2s3BsPMrID3X QUxg== X-Gm-Message-State: ALQs6tBCuh0tOvqmowXd18gYRxprkax2OoiL5QN4pq4lTjCdtFu+HcHZ hPtdwaU0i6hjEH9JKoDGyRgtlAkLHq0WfVsnJziqcQ== X-Google-Smtp-Source: AB8JxZpxaWq14T4E3McVB0By8/+HFSVwY7tKB55WgNQEPMKPIn7f/3E2056Ry+gno+4sT60zc0PfiCirJtZENrlBypk= X-Received: by 2002:a6b:970d:: with SMTP id z13-v6mr9004140iod.277.1524213286079; Fri, 20 Apr 2018 01:34:46 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.187.67 with HTTP; Fri, 20 Apr 2018 01:34:45 -0700 (PDT) In-Reply-To: <1518771035-6733-34-git-send-email-meenakshi.aggarwal@nxp.com> References: <1518771035-6733-1-git-send-email-meenakshi.aggarwal@nxp.com> <1518771035-6733-34-git-send-email-meenakshi.aggarwal@nxp.com> From: Ard Biesheuvel Date: Fri, 20 Apr 2018 10:34:45 +0200 Message-ID: To: Meenakshi Cc: Leif Lindholm , "Kinney, Michael D" , "edk2-devel@lists.01.org" , Udit Kumar , Varun Sethi , Vabhav Subject: Re: [PATCH edk2-platforms 33/39] Silicon/NXP: Implement PciHostBridgeLib support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Apr 2018 08:34:47 -0000 Content-Type: text/plain; charset="UTF-8" On 16 February 2018 at 09:50, Meenakshi wrote: > From: Vabhav > > Implement the library that exposes the PCIe root complexes to the > generic PCI host bridge driver,Putting SoC Specific low level init > code for the RCs. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Vabhav > Signed-off-by: Meenakshi Aggarwal > --- > .../Library/PciHostBridgeLib/PciHostBridgeLib.c | 618 +++++++++++++++++++++ > .../Library/PciHostBridgeLib/PciHostBridgeLib.inf | 50 ++ > 2 files changed, 668 insertions(+) > create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c > create mode 100644 Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf > > diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c > new file mode 100644 > index 0000000..e6f9b7c > --- /dev/null > +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.c > @@ -0,0 +1,618 @@ > +/** @file > + PCI Host Bridge Library instance for NXP SoCs > + > + Copyright 2018 NXP > + > + This program and the accompanying materials are licensed and made available > + under the terms and conditions of the BSD License which accompanies this > + distribution. The full text of the license may be found at > + http://opensource.org/licenses/bsd-license.php. > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT > + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#pragma pack(1) > +typedef struct { > + ACPI_HID_DEVICE_PATH AcpiDevicePath; > + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; > +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; > +#pragma pack () > + > +STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = { > + { > + { > + { > + ACPI_DEVICE_PATH, > + ACPI_DP, > + { > + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)), > + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) > + } > + }, > + EISA_PNP_ID (0x0A08), // PCI Express > + PCI_SEG0_NUM > + }, > + > + { > + END_DEVICE_PATH_TYPE, > + END_ENTIRE_DEVICE_PATH_SUBTYPE, > + { > + END_DEVICE_PATH_LENGTH, > + 0 > + } > + } > + }, > + { > + { > + { > + ACPI_DEVICE_PATH, > + ACPI_DP, > + { > + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)), > + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) > + } > + }, > + EISA_PNP_ID (0x0A08), // PCI Express > + PCI_SEG1_NUM > + }, > + > + { > + END_DEVICE_PATH_TYPE, > + END_ENTIRE_DEVICE_PATH_SUBTYPE, > + { > + END_DEVICE_PATH_LENGTH, > + 0 > + } > + } > + }, > + { > + { > + { > + ACPI_DEVICE_PATH, > + ACPI_DP, > + { > + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)), > + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) > + } > + }, > + EISA_PNP_ID (0x0A08), // PCI Express > + PCI_SEG2_NUM > + }, > + > + { > + END_DEVICE_PATH_TYPE, > + END_ENTIRE_DEVICE_PATH_SUBTYPE, > + { > + END_DEVICE_PATH_LENGTH, > + 0 > + } > + } > + }, > + { > + { > + { > + ACPI_DEVICE_PATH, > + ACPI_DP, > + { > + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)), > + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8) > + } > + }, > + EISA_PNP_ID (0x0A08), // PCI Express > + PCI_SEG3_NUM > + }, > + > + { > + END_DEVICE_PATH_TYPE, > + END_ENTIRE_DEVICE_PATH_SUBTYPE, > + { > + END_DEVICE_PATH_LENGTH, > + 0 > + } > + } > + } > +}; > + > +STATIC > +GLOBAL_REMOVE_IF_UNREFERENCED > +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { > + L"Mem", L"I/O", L"Bus" > +}; > + > +#define PCI_ALLOCATION_ATTRIBUTES EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | \ > + EFI_PCI_HOST_BRIDGE_MEM64_DECODE > + > +#define PCI_SUPPORT_ATTRIBUTES EFI_PCI_ATTRIBUTE_ISA_IO_16 | \ > + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \ > + EFI_PCI_ATTRIBUTE_VGA_MEMORY | \ > + EFI_PCI_ATTRIBUTE_VGA_IO_16 | \ > + EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 > + > +PCI_ROOT_BRIDGE mPciRootBridges[] = { > + { > + PCI_SEG0_NUM, // Segment > + PCI_SUPPORT_ATTRIBUTES, // Supports > + PCI_SUPPORT_ATTRIBUTES, // Attributes > + FALSE, // DmaAbove4G Why is this disabled? The root bridge driver will have to do bounce buffering when performing DMA on memory > 4 GB. > + FALSE, // NoExtendedConfigSpace > + FALSE, // ResourceAssigned > + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes > + { PCI_SEG0_BUSNUM_MIN, > + PCI_SEG0_BUSNUM_MAX }, // Bus > + { PCI_SEG0_PORTIO_MIN, > + PCI_SEG0_PORTIO_MAX }, // Io > + { PCI_SEG0_MMIO32_MIN, > + PCI_SEG0_MMIO32_MAX }, // Mem > + { PCI_SEG0_MMIO64_MIN, > + PCI_SEG0_MMIO64_MAX }, // MemAbove4G > + { MAX_UINT64, 0x0 }, // PMem > + { MAX_UINT64, 0x0 }, // PMemAbove4G > + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PCI_SEG0_NUM] > + }, { > + PCI_SEG1_NUM, // Segment > + PCI_SUPPORT_ATTRIBUTES, // Supports > + PCI_SUPPORT_ATTRIBUTES, // Attributes > + FALSE, // DmaAbove4G > + FALSE, // NoExtendedConfigSpace > + FALSE, // ResourceAssigned > + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes > + { PCI_SEG1_BUSNUM_MIN, > + PCI_SEG1_BUSNUM_MAX }, // Bus > + { PCI_SEG1_PORTIO_MIN, > + PCI_SEG1_PORTIO_MAX }, // Io > + { PCI_SEG1_MMIO32_MIN, > + PCI_SEG1_MMIO32_MAX }, // Mem > + { PCI_SEG1_MMIO64_MIN, > + PCI_SEG1_MMIO64_MAX }, // MemAbove4G > + { MAX_UINT64, 0x0 }, // PMem > + { MAX_UINT64, 0x0 }, // PMemAbove4G > + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PCI_SEG1_NUM] > + }, { > + PCI_SEG2_NUM, // Segment > + PCI_SUPPORT_ATTRIBUTES, // Supports > + PCI_SUPPORT_ATTRIBUTES, // Attributes > + FALSE, // DmaAbove4G > + FALSE, // NoExtendedConfigSpace > + FALSE, // ResourceAssigned > + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes > + { PCI_SEG2_BUSNUM_MIN, > + PCI_SEG2_BUSNUM_MAX }, // Bus > + { PCI_SEG2_PORTIO_MIN, > + PCI_SEG2_PORTIO_MAX }, // Io > + { PCI_SEG2_MMIO32_MIN, > + PCI_SEG2_MMIO32_MAX }, // Mem > + { PCI_SEG2_MMIO64_MIN, > + PCI_SEG2_MMIO64_MAX }, // MemAbove4G > + { MAX_UINT64, 0x0 }, // PMem > + { MAX_UINT64, 0x0 }, // PMemAbove4G > + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PCI_SEG2_NUM] > + }, { > + PCI_SEG3_NUM, // Segment > + PCI_SUPPORT_ATTRIBUTES, // Supports > + PCI_SUPPORT_ATTRIBUTES, // Attributes > + FALSE, // DmaAbove4G > + FALSE, // NoExtendedConfigSpace > + FALSE, // ResourceAssigned > + PCI_ALLOCATION_ATTRIBUTES, // AllocationAttributes > + { PCI_SEG3_BUSNUM_MIN, > + PCI_SEG3_BUSNUM_MAX }, // Bus > + { PCI_SEG3_PORTIO_MIN, > + PCI_SEG3_PORTIO_MAX }, // Io > + { PCI_SEG3_MMIO32_MIN, > + PCI_SEG3_MMIO32_MAX }, // Mem > + { PCI_SEG3_MMIO64_MIN, > + PCI_SEG3_MMIO64_MAX }, // MemAbove4G > + { MAX_UINT64, 0x0 }, // PMem > + { MAX_UINT64, 0x0 }, // PMemAbove4G > + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[PCI_SEG3_NUM] > + } > +}; > + > +/** > + Function to set-up iATU outbound window for PCIe controller > + > + @param Dbi Address of PCIe host controller. > + @param Idx Index of iATU outbound window. > + @param Type Type(Cfg0/Cfg1/Mem/IO) of iATU outbound window. > + @param Phys PCIe controller phy address for outbound window. > + @param BusAdr PCIe controller bus address for outbound window. > + @param Pcie Size of PCIe controller space(Cfg0/Cfg1/Mem/IO). > + > +**/ > +STATIC > +VOID > +PcieIatuOutboundSet ( > + IN EFI_PHYSICAL_ADDRESS Dbi, > + IN UINT32 Idx, > + IN UINT32 Type, > + IN UINT64 Phys, > + IN UINT64 BusAddr, > + IN UINT64 Size > + ) > +{ > + MmioWrite32 (Dbi + IATU_VIEWPORT_OFF, > + (UINT32)(IATU_VIEWPORT_OUTBOUND | Idx)); > + MmioWrite32 (Dbi + IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0, > + (UINT32)Phys); > + MmioWrite32 (Dbi + IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0, > + (UINT32)(Phys >> 32)); > + MmioWrite32 (Dbi + IATU_LIMIT_ADDR_OFF_OUTBOUND_0, > + (UINT32)(Phys + Size - BIT0)); > + MmioWrite32 (Dbi + IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0, > + (UINT32)BusAddr); > + MmioWrite32 (Dbi + IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0, > + (UINT32)(BusAddr >> 32)); > + MmioWrite32 (Dbi + IATU_REGION_CTRL_1_OFF_OUTBOUND_0, > + (UINT32)Type); > + MmioWrite32 (Dbi + IATU_REGION_CTRL_2_OFF_OUTBOUND_0, > + IATU_REGION_CTRL_2_OFF_OUTBOUND_0_REGION_EN); > +} > + > +/** > + Function to check PCIe controller LTSSM state > + > + @param Pcie Address of PCIe host controller. > + > +**/ > +STATIC > +INTN > +PcieLinkState ( > + IN EFI_PHYSICAL_ADDRESS Pcie > + ) > +{ > + UINT32 State; > + > + // > + // Reading PCIe controller LTSSM state > + // > + if (FeaturePcdGet (PcdPciLutBigEndian)) { > + State = BeMmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) & > + LTSSM_STATE_MASK; > + } else { > + State = MmioRead32 ((UINTN)Pcie + PCI_LUT_BASE + PCI_LUT_DBG) & > + LTSSM_STATE_MASK; > + } > + > + if (State < LTSSM_PCIE_L0) { > + DEBUG ((DEBUG_INFO," Pcie Link error. LTSSM=0x%2x\n", State)); > + return EFI_SUCCESS; > + } > + > + return EFI_UNSUPPORTED; > +} > + > +/** > + Helper function to check PCIe link state > + > + @param Pcie Address of PCIe host controller. > + > +**/ > +STATIC > +INTN > +PcieLinkUp ( > + IN EFI_PHYSICAL_ADDRESS Pcie > + ) > +{ > + INTN State; > + UINT32 Cap; > + > + State = PcieLinkState (Pcie); > + if (State) { > + return State; > + } > + > + // > + // Try to download speed to gen1 > + // > + Cap = MmioRead32 ((UINTN)Pcie + PCI_LINK_CAP); > + MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, (UINT32)(Cap & (~PCI_LINK_SPEED_MASK)) | BIT0); > + State = PcieLinkState (Pcie); > + if (State) { > + return State; > + } > + > + MmioWrite32 ((UINTN)Pcie + PCI_LINK_CAP, Cap); > + > + return EFI_SUCCESS; > +} > + > +/** > + This function checks whether PCIe is enabled or not > + depending upon SoC serdes protocol map > + > + @param PcieNum PCIe number. > + > + @return The PCIe number enabled in map. > + @return FALSE PCIe number is disabled in map. > + > +**/ > +STATIC > +BOOLEAN > +IsPcieNumEnabled( > + IN UINTN PcieNum > + ) > +{ > + UINT64 SerDes1ProtocolMap; > + > + SerDes1ProtocolMap = 0x0; > + > + // > + // Reading serdes map > + // > + GetSerdesProtocolMaps (&SerDes1ProtocolMap); > + > + // > + // Verify serdes line is configured in the map > + // > + if (PcieNum < NUM_PCIE_CONTROLLER) { > + return IsSerDesLaneProtocolConfigured (SerDes1ProtocolMap, (PcieNum + BIT0)); > + } else { > + DEBUG ((DEBUG_ERROR, "Device not supported\n")); > + } > + > + return FALSE; > +} > + > +/** > + Function to set-up iATU outbound window for PCIe controller > + > + @param Pcie Address of PCIe host controller > + @param Cfg0Base PCIe controller phy address Type0 Configuration Space. > + @param Cfg1Base PCIe controller phy address Type1 Configuration Space. > + @param MemBase PCIe controller phy address Memory Space. > + @param IoBase PCIe controller phy address IO Space. > +**/ > +STATIC > +VOID > +PcieSetupAtu ( > + IN EFI_PHYSICAL_ADDRESS Pcie, > + IN EFI_PHYSICAL_ADDRESS Cfg0Base, > + IN EFI_PHYSICAL_ADDRESS Cfg1Base, > + IN EFI_PHYSICAL_ADDRESS MemBase, > + IN EFI_PHYSICAL_ADDRESS IoBase > + ) > +{ > + > + // > + // iATU : OUTBOUND WINDOW 0 : CFG0 > + // > + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX0, > + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG0, > + Cfg0Base, > + SEG_CFG_BUS, > + SEG_CFG_SIZE); > + > + // > + // iATU : OUTBOUND WINDOW 1 : CFG1 > + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX1, > + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_CFG1, > + Cfg1Base, > + SEG_CFG_BUS, > + SEG_CFG_SIZE); > + // > + // iATU 2 : OUTBOUND WINDOW 2 : MEM > + // > + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX2, > + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM, > + MemBase, > + SEG_MEM_BUS, > + SEG_MEM_SIZE); > + > + // > + // iATU 3 : OUTBOUND WINDOW 3: IO > + // > + PcieIatuOutboundSet (Pcie, IATU_REGION_INDEX3, > + IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_IO, > + IoBase, > + SEG_IO_BUS, > + SEG_IO_SIZE); > + What happened to the 64-bit MMIO window? > +} > + > +/** > + Helper function to set-up PCIe controller > + > + @param Pcie Address of PCIe host controller > + @param Cfg0Base PCIe controller phy address Type0 Configuration Space. > + @param Cfg1Base PCIe controller phy address Type1 Configuration Space. > + @param MemBase PCIe controller phy address Memory Space. > + @param IoBase PCIe controller phy address IO Space. > + > +**/ > +STATIC > +VOID > +PcieSetupCntrl ( > + IN EFI_PHYSICAL_ADDRESS Pcie, > + IN EFI_PHYSICAL_ADDRESS Cfg0Base, > + IN EFI_PHYSICAL_ADDRESS Cfg1Base, > + IN EFI_PHYSICAL_ADDRESS MemBase, > + IN EFI_PHYSICAL_ADDRESS IoBase > + ) > +{ > + // > + // iATU outbound set-up > + // > + PcieSetupAtu (Pcie, Cfg0Base, Cfg1Base, MemBase, IoBase); > + > + // > + // program correct class for RC > + // > + MmioWrite32 ((UINTN)Pcie + PCI_BASE_ADDRESS_0, (BIT0 - BIT0)); > + MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)BIT0); > + MmioWrite32 ((UINTN)Pcie + PCI_CLASS_DEVICE, (UINT32)PCI_CLASS_BRIDGE_PCI); > + MmioWrite32 ((UINTN)Pcie + PCI_DBI_RO_WR_EN, (UINT32)(BIT0 - BIT0)); > +} > + > +/** > + Return all the root bridge instances in an array. > + > + @param Count Return the count of root bridge instances. > + > + @return All the root bridge instances in an array. > + > +**/ > +PCI_ROOT_BRIDGE * > +EFIAPI > +PciHostBridgeGetRootBridges ( > + OUT UINTN *Count > + ) > +{ > + UINTN Idx; > + INTN LinkUp; > + UINT64 PciPhyMemAddr[NUM_PCIE_CONTROLLER]; > + UINT64 PciPhyCfg0Addr[NUM_PCIE_CONTROLLER]; > + UINT64 PciPhyCfg1Addr[NUM_PCIE_CONTROLLER]; > + UINT64 PciPhyIoAddr[NUM_PCIE_CONTROLLER]; > + UINT64 Regs[NUM_PCIE_CONTROLLER]; > + > + *Count = 0; > + > + // > + // Filling local array for > + // PCIe controller Physical address space for Cfg0,Cfg1,Mem,IO > + // Host Contoller address > + // > + for (Idx = 0; Idx < NUM_PCIE_CONTROLLER; Idx++) { > + PciPhyMemAddr[Idx] = PCI_SEG0_PHY_MEM_BASE + (PCI_BASE_DIFF * Idx); > + PciPhyCfg0Addr[Idx] = PCI_SEG0_PHY_CFG0_BASE + (PCI_BASE_DIFF * Idx); > + PciPhyCfg1Addr[Idx] = PCI_SEG0_PHY_CFG1_BASE + (PCI_BASE_DIFF * Idx); > + PciPhyIoAddr [Idx] = PCI_SEG0_PHY_IO_BASE + (PCI_BASE_DIFF * Idx); > + Regs[Idx] = PCI_SEG0_DBI_BASE + (PCI_DBI_SIZE_DIFF * Idx); > + } > + > + for (Idx = 0; Idx < NUM_PCIE_CONTROLLER; Idx++) { > + // > + // Verify PCIe controller is enabled in Soc Serdes Map > + // > + if (!IsPcieNumEnabled (Idx)) { > + DEBUG ((DEBUG_ERROR, "PCIE%d is disabled\n", (Idx + BIT0))); > + // > + // Continue with other PCIe controller > + // > + continue; > + } > + DEBUG ((DEBUG_INFO, "PCIE%d is Enabled\n", Idx + BIT0)); > + > + // > + // Verify PCIe controller LTSSM state > + // > + LinkUp = PcieLinkUp(Regs[Idx]); > + if (!LinkUp) { > + // > + // Let the user know there's no PCIe link > + // > + DEBUG ((DEBUG_INFO,"no link, regs @ 0x%lx\n", Regs[Idx])); > + // > + // Continue with other PCIe controller > + // > + continue; > + } > + DEBUG ((DEBUG_INFO, "PCIE%d Passed Linkup Phase\n", Idx + BIT0)); > + > + // > + // Function to set up address translation unit outbound window for > + // PCIe Controller > + // > + PcieSetupCntrl (Regs[Idx], > + PciPhyCfg0Addr[Idx], > + PciPhyCfg1Addr[Idx], > + PciPhyMemAddr[Idx], > + PciPhyIoAddr[Idx]); > + *Count += BIT0; > + break; > + } > + > + if (*Count == 0) { > + return NULL; > + } else { > + return &mPciRootBridges[Idx]; > + } > +} > + > +/** > + Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). > + > + @param Bridges The root bridge instances array. > + @param Count The count of the array. > +**/ > +VOID > +EFIAPI > +PciHostBridgeFreeRootBridges ( > + PCI_ROOT_BRIDGE *Bridges, > + UINTN Count > + ) > +{ > +} > + > +/** > + Inform the platform that the resource conflict happens. > + > + @param HostBridgeHandle Handle of the Host Bridge. > + @param Configuration Pointer to PCI I/O and PCI memory resource > + descriptors. The Configuration contains the resources > + for all the root bridges. The resource for each root > + bridge is terminated with END descriptor and an > + additional END is appended indicating the end of the > + entire resources. The resource descriptor field > + values follow the description in > + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL > + .SubmitResources(). > + > +**/ > +VOID > +EFIAPI > +PciHostBridgeResourceConflict ( > + EFI_HANDLE HostBridgeHandle, > + VOID *Configuration > + ) > +{ > + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; > + UINTN RootBridgeIndex; > + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n")); > + > + RootBridgeIndex = 0; > + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; > + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { > + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); > + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { > + ASSERT (Descriptor->ResType < > + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr)); > + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n", > + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], > + Descriptor->AddrLen, Descriptor->AddrRangeMax > + )); > + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { > + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n", > + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, > + ((Descriptor->SpecificFlag & > + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE > + ) != 0) ? L" (Prefetchable)" : L"" > + )); > + } > + } > + // > + // Skip the END descriptor for root bridge > + // > + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR); > + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( > + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 > + ); > + } > + > + return; > +} > diff --git a/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf > new file mode 100644 > index 0000000..f08ac60 > --- /dev/null > +++ b/Silicon/NXP/Library/PciHostBridgeLib/PciHostBridgeLib.inf > @@ -0,0 +1,50 @@ > +## @file > +# PCI Host Bridge Library instance for NXP ARM SOC > +# > +# Copyright 2018 NXP > +# > +# This program and the accompanying materials are licensed and made available > +# under the terms and conditions of the BSD License which accompanies this > +# distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR > +# IMPLIED. > +# > +# > +## > + > +[Defines] > + INF_VERSION = 0x0001001A > + BASE_NAME = PciHostBridgeLib > + FILE_GUID = f4c99bcc-5c95-49ad-b0f3-fc5b611dc9c1 > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = PciHostBridgeLib > + > +[Sources] > + PciHostBridgeLib.c > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + Silicon/NXP/NxpQoriqLs.dec > + Silicon/NXP/Chassis/Chassis2/Chassis2.dec > + > +[LibraryClasses] > + DebugLib > + DevicePathLib > + MemoryAllocationLib > + PcdLib > + SocLib > + UefiBootServicesTableLib > + > +[Pcd] > + gNxpQoriqLsTokenSpaceGuid.PcdPciLutBigEndian > + gNxpQoriqLsTokenSpaceGuid.PcdNumPciController > + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutBase > + gNxpQoriqLsTokenSpaceGuid.PcdPcieLutDbg > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp1BaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp2BaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp3BaseAddr > + gNxpQoriqLsTokenSpaceGuid.PcdPciExp4BaseAddr > -- > 1.9.1 >