From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-it0-x22d.google.com (mail-it0-x22d.google.com [IPv6:2607:f8b0:4001:c0b::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D1F3121DFA8F2 for ; Thu, 6 Apr 2017 13:01:58 -0700 (PDT) Received: by mail-it0-x22d.google.com with SMTP id 19so12104541itj.1 for ; Thu, 06 Apr 2017 13:01:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=XJJ4PYER/funZJsIIW1STAyO8A1ZJs6qMXay7NL8J9Q=; b=J/+ic7ChV9gsLbrPu+a3HvRse+IyF7Cisx/Y1SvYpw1F70K3pFIQzLT9UFEW/We6FR Y5Rf3B0qzzuVWCsSHsG+pxX82hHDxviAswaoP733tD5Jlvp5Rt7aflYIup8YLG1lYP6+ 9/pDqJr5x9qMvDRG/4i9JcVu3gEIunxWPRG4k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=XJJ4PYER/funZJsIIW1STAyO8A1ZJs6qMXay7NL8J9Q=; b=jrG0rbtCQG5QXNk3eTcIGXgKv1ZjNx/iOHuci3JBhqYRIocD5B2hmQA8ySO0JgyR39 WzdEr2uIr0RArPaorjOOR3xArk4p1iDF68P9/1eHQ+P+1IZxxZnm25eQhoXCUtepXd1G OkmuuL6bHBfR4yuCnZxZB/fzf2oP1JZ10OvrR3M0arT1LOMeHdjqXb/2KE/sNuR+oWW5 2ViNYOFM+iBWGUWxcw1sr6v0HQKCRJF+82Vx38jPIdjlUTq+YWlECsS0LpTPc83rC8eI sn+BqB0jwSnK1lNucPJ5/VszCbXsJ98WnkGK84PGjAepHgX/Q6rVAfsLw6kFhiYt3BNV Q6rw== X-Gm-Message-State: AFeK/H3iQDVlommNgQ3QFDYyOh3zvjMmshylMsJ6liitTE+AiTLSSH0X uom5EjI7AgdWu21tdtvKpS0hfxTv+ZMS X-Received: by 10.36.65.148 with SMTP id b20mr5732801itd.59.1491508918172; Thu, 06 Apr 2017 13:01:58 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.10.27 with HTTP; Thu, 6 Apr 2017 13:01:57 -0700 (PDT) In-Reply-To: <20170406190610.GP25239@bivouac.eciton.net> References: <20170406131551.3322-1-ard.biesheuvel@linaro.org> <20170406131551.3322-2-ard.biesheuvel@linaro.org> <20170406182648.GK25239@bivouac.eciton.net> <20170406184507.GO25239@bivouac.eciton.net> <20170406190610.GP25239@bivouac.eciton.net> From: Ard Biesheuvel Date: Thu, 6 Apr 2017 21:01:57 +0100 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" , Ryan Harkin , Evan Lloyd , Jeremy Linton Subject: Re: [PATCH v2 1/5] ArmPlatformPkg/FVP: map motherboard VRAM as uncached memory X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Apr 2017 20:01:59 -0000 Content-Type: text/plain; charset=UTF-8 On 6 April 2017 at 20:06, Leif Lindholm wrote: > On Thu, Apr 06, 2017 at 07:46:50PM +0100, Ard Biesheuvel wrote: >> >> >> + // VRAM >> >> >> + VirtualMemoryTable[++Index].PhysicalBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE; >> >> >> + VirtualMemoryTable[Index].VirtualBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE; >> >> >> + VirtualMemoryTable[Index].Length = PL111_CLCD_VRAM_MOTHERBOARD_SIZE; >> >> >> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; >> >> > >> >> > Hmm, looking at this made me a bit confused though. Normal uncached >> >> > memory is certainly bufferable (that's basically what write-combining >> >> > means). >> >> > >> >> >> >> It maps to MAIR attribute encoding 0x44, which translates as >> >> >> >> Normal Memory, Outer Non-Cacheable, Inner Non-Cacheable >> > >> > Exactly - which is definitely "buffered". >> > >> >> > This looks like a naming hangover from ARMv5 translation table format. >> >> > Is it about time we clean this up? >> >> >> >> The whole 'ARM_MEMORY_REGION_xxxx' intermediate namespace should be >> >> removed, I think. >> > >> > That sounds like a good idea to me. >> > There's also _NONSECURE crud in there. >> > >> >> Yes. But I hope you're not saying you want that to be done first >> before this patch can go in? > > No, but it may mean it makes sense to add a comment regarding the > Attributes line, since it looks like it's doing the opposite of what > is actually being done. > Something like --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c @@ -134,6 +134,12 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[++Index].PhysicalBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE; VirtualMemoryTable[Index].VirtualBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE; VirtualMemoryTable[Index].Length = PL111_CLCD_VRAM_MOTHERBOARD_SIZE; + // + // Map the VRAM region as Normal Non-Cacheable memory and not device memory, + // so that we can use the accelerated string routines that may use unaligned + // accesses or DC ZVA instructions. The enum identifier is slightly awkward + // here, but it maps to a memory type that allows buffering and reordering. + // VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; // Map sparse memory region if present perhaps?