From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-oi0-x22a.google.com (mail-oi0-x22a.google.com [IPv6:2607:f8b0:4003:c06::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D8FAD1A1DFF for ; Fri, 9 Sep 2016 03:07:46 -0700 (PDT) Received: by mail-oi0-x22a.google.com with SMTP id q188so16042639oia.3 for ; Fri, 09 Sep 2016 03:07:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=txN1VEYKyUa9z2OG6bWFyGolTsuADqyl1SMAkA8nzTg=; b=a1y1yGreistRXxDtpcld2FULuLoPA2KMCw0RKfsQr6fXFgvtRPtyqvi7jkCplii3QD WX7CRw3CfeAUOTYtsCkfC3TCEpDSEC0lXy+mRh46FLTnpGzEcovMSuTsE9VbxlMi6AyT 1zWau2iz8el45xqA+8JvDF1YVTCQ6jJ4sXRSk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=txN1VEYKyUa9z2OG6bWFyGolTsuADqyl1SMAkA8nzTg=; b=NWuB1VThkIvBaXQv0HUeHjlhLKeTEj8hMNEl/tqtCxDwIe9YJ0wZrWEGLT/wcTk/64 SoRZzAEm+elFNgavbhoaZsrluTOLyir6uaUBTPuKGJYR85q7lSum1Yx1C/xKZL0ILEG3 egim6ACbVXFWlf+3x3WcxV30ldh4pIvylW4mP9OTPfnwE2FJJMgvR7pmDRDjlk+4E4KK gOmZixEVp3ulNJK27HVVUPwG1UjEs+ny02e/xhiY8jbZjjcYY7mLZmUQhqaHDZ78a3s3 SIA05k6m/4iIfBnxjpieHKe1sSS6ByCl1BMKTE/1KCuwm4hw4F7Gu55aD3YDSgNYQDBH +Lgw== X-Gm-Message-State: AE9vXwPPq3/ZSZolucaGFpsPjmIzg9osPtdmERAycfx1d+WsQHddkobBf5OnE+xq+FhRpK8holb+/S+qPIOot3x6 X-Received: by 10.202.183.11 with SMTP id h11mr3878270oif.23.1473415666059; Fri, 09 Sep 2016 03:07:46 -0700 (PDT) MIME-Version: 1.0 Received: by 10.36.204.195 with HTTP; Fri, 9 Sep 2016 03:07:45 -0700 (PDT) In-Reply-To: <1473411633-25763-1-git-send-email-ard.biesheuvel@linaro.org> References: <1473411633-25763-1-git-send-email-ard.biesheuvel@linaro.org> From: Ard Biesheuvel Date: Fri, 9 Sep 2016 11:07:45 +0100 Message-ID: To: edk2-devel-01 , Leif Lindholm , "Cohen, Eugene" Cc: Ard Biesheuvel Subject: Re: [PATCH] ArmPkg/ArmMmuLib: use a pool allocation for the root table X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 09 Sep 2016 10:07:47 -0000 Content-Type: text/plain; charset=UTF-8 Please disregard, I will follow up with a more elaborate series. On 9 September 2016 at 10:00, Ard Biesheuvel wrote: > Currently, we allocate a full page for the root translation table, even > if the configured translation only requires two entries (16 bytes) for > the root level, which happens to be the case for a 40 bit VA. Likewise, > for a 36-bit VA space, the root table only needs 16 entries of 8 bytes > each, adding up to 128 bytes. > > So switch to a pool allocation for the root table, but take into account > that the architecture requires it to be naturally aligned to its size, > i.e., a 64 byte table requires 64 byte alignment, whereas pool allocations > in general are only guaranteed to be aligned to 8 bytes. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel > --- > ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 23 +++++++++++++------- > 1 file changed, 15 insertions(+), 8 deletions(-) > > diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > index b5900a761f80..297771a42761 100644 > --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > @@ -580,11 +580,12 @@ ArmConfigureMmu ( > ) > { > VOID* TranslationTable; > - UINTN TranslationTablePageCount; > + VOID* TranslationTableBuffer; > UINT32 TranslationTableAttribute; > UINT64 MaxAddress; > UINTN T0SZ; > UINTN RootTableEntryCount; > + UINTN RootTableEntrySize; > UINT64 TCR; > RETURN_STATUS Status; > > @@ -656,12 +657,18 @@ ArmConfigureMmu ( > // Set TCR > ArmSetTCR (TCR); > > - // Allocate pages for translation table > - TranslationTablePageCount = EFI_SIZE_TO_PAGES(RootTableEntryCount * sizeof(UINT64)); > - TranslationTable = (UINT64*)AllocateAlignedPages (TranslationTablePageCount, TT_ALIGNMENT_DESCRIPTION_TABLE); > - if (TranslationTable == NULL) { > + // Allocate pages for translation table. Pool allocations are 8 byte aligned, > + // but we may require a higher alignment based on the size of the root table. > + RootTableEntrySize = RootTableEntryCount * sizeof(UINT64); > + TranslationTableBuffer = AllocatePool (2 * RootTableEntrySize - 8); > + if (TranslationTableBuffer == NULL) { > return RETURN_OUT_OF_RESOURCES; > } > + // > + // Naturally align the root table > + // > + TranslationTable = (VOID *)((UINTN)(TranslationTableBuffer - 1) | (RootTableEntrySize - 1)) + 1; > + > // We set TTBR0 just after allocating the table to retrieve its location from the subsequent > // functions without needing to pass this value across the functions. The MMU is only enabled > // after the translation tables are populated. > @@ -672,10 +679,10 @@ ArmConfigureMmu ( > } > > if (TranslationTableSize != NULL) { > - *TranslationTableSize = RootTableEntryCount * sizeof(UINT64); > + *TranslationTableSize = RootTableEntrySize; > } > > - ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64)); > + ZeroMem (TranslationTable, RootTableEntrySize); > > // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs > ArmDisableMmu (); > @@ -735,7 +742,7 @@ ArmConfigureMmu ( > return RETURN_SUCCESS; > > FREE_TRANSLATION_TABLE: > - FreePages (TranslationTable, TranslationTablePageCount); > + FreePool (TranslationTableBuffer); > return Status; > } > > -- > 2.7.4 >