From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::22e; helo=mail-io0-x22e.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x22e.google.com (mail-io0-x22e.google.com [IPv6:2607:f8b0:4001:c06::22e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C3CBD2095B093 for ; Mon, 9 Oct 2017 03:37:20 -0700 (PDT) Received: by mail-io0-x22e.google.com with SMTP id h70so2027990ioi.4 for ; Mon, 09 Oct 2017 03:40:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=MyL9lD0Qal49thW/Gp8qJlp+mcDhdGSgkFyZ4vxZgWA=; b=EBGVuCaZhkn9bFIIiFwfGwdAm9XdQDX/pvWFP02I+zaLjI0gzxBxHR3aC5siQreSQS ABJX3y6Xa/zQIsldOY+Pgd1OUjjZZlDYA8WSf1yUDfudt4cmetabrhbpJvrF5B5WhxOo rbzSplMh63Ur7UdfdiUxudc5gTTUTKyQLhfN0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=MyL9lD0Qal49thW/Gp8qJlp+mcDhdGSgkFyZ4vxZgWA=; b=mou8DlrUsKxUzZLquCx4zZl6WP17HzYAbxtdgc+Cbwv37nXKri6nIBDP8FHIUs/4gl qqEpFL4BifLFB0dPthudtqnOUTXHM7gwHuqh1LFV8RB3EzXVzQjEulZPjqK7NjHR3QoO CcBtHyHOcnjC8Z/Xg1/+BDcctHhZNDKlUF9sWp0fdfDz3sNMidlJWrD5u3uH6SMbVakz gRWEJxReMgKy9TF/R31u27Rspj4DLZZtKo7qlZseVbLqe9QWki7dTrSHkq5hqv7x/4BA FFMYeE86pAwjbLHwyHVzEiujKhKo6zi3RNg7Vr0hWAxGvj2rk2UbVn90Ng8uNsuObMXs Y0UQ== X-Gm-Message-State: AMCzsaVbHdeJ6d4fVess8UVt9azrUHPdZmUAAXSObtLwJzxPsffHJkhZ ALBDDvBhSSy8oqg8CFOgw/0Pnx+GuUeYI2g7T43akQ== X-Google-Smtp-Source: AOwi7QAcn0w8p48JgcnXTO6QL47+fiqpR8Fvp3NKzyyi+qHanT2VBNJtJcEJ3C1PO5PuOU/rCKu9Oe+3xL7dJZEDBD4= X-Received: by 10.107.15.170 with SMTP id 42mr12101448iop.141.1507545646823; Mon, 09 Oct 2017 03:40:46 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.131.167 with HTTP; Mon, 9 Oct 2017 03:40:46 -0700 (PDT) In-Reply-To: <734D49CCEBEEF84792F5B80ED585239D5BA8A854@SHSMSX104.ccr.corp.intel.com> References: <20171009011539.45115-1-daniil.egranov@arm.com> <734D49CCEBEEF84792F5B80ED585239D5BA8A854@SHSMSX104.ccr.corp.intel.com> From: Ard Biesheuvel Date: Mon, 9 Oct 2017 11:40:46 +0100 Message-ID: To: "Ni, Ruiyu" Cc: Daniil Egranov , "edk2-devel@lists.01.org" , "leif.lindholm@linaro.org" , "Zeng, Star" Subject: Re: [PATCH] MdeModulePkg/PciHostBridgeDxe: Fixed PCI DMA Map/Umap bounce buffer X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Oct 2017 10:37:21 -0000 Content-Type: text/plain; charset="UTF-8" On 9 October 2017 at 08:42, Ni, Ruiyu wrote: > The "read"/"write" is from the Bus Master's point of view. > > > Thanks/Ray > >> -----Original Message----- >> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Daniil >> Egranov >> Sent: Monday, October 9, 2017 9:16 AM >> To: edk2-devel@lists.01.org >> Cc: leif.lindholm@linaro.org; Zeng, Star ; >> ard.biesheuvel@linaro.org >> Subject: [edk2] [PATCH] MdeModulePkg/PciHostBridgeDxe: Fixed PCI DMA >> Map/Umap bounce buffer >> >> The patch corrects the logic of transferring data between a bounce buffer and a >> real buffer above 4GB: >> 1. In the case of mapping a bounce buffer for the write operation, data from a >> real buffer should be copied into a bounce buffer. >> 2.In the case of unmapping a bounce buffer for the read operation, data should >> be copied from a bounce buffer into a real buffer. >> >> The patch resolves a Juno board issue with the the grub and SATA drives. >> I am intrigued by this. So as I suggested, this has to do with 64-bit DMA, but not in the way I suspected. UEFI itself never hits this code path, because it runs entirely < 32 GB, but as soon as GRUB starts allocating loader data and use it for DMA, the bounce buffering kicks in because apparently, the SATA controller is not 64-bit DMA capable. Are you using the SataSiI3132Dxe driver on Juno? Does this help at all? diff --git a/EmbeddedPkg/Drivers/SataSiI3132Dxe/SiI3132AtaPassThru.c b/EmbeddedPkg/Drivers/SataSiI3132Dxe/SiI3132AtaPassThru.c index 2fb5fd68db01..a938563ebdd6 100644 --- a/EmbeddedPkg/Drivers/SataSiI3132Dxe/SiI3132AtaPassThru.c +++ b/EmbeddedPkg/Drivers/SataSiI3132Dxe/SiI3132AtaPassThru.c @@ -104,7 +104,7 @@ SiI3132AtaPassThruCommand ( } Status = PciIo->Map ( - PciIo, EfiPciIoOperationBusMasterRead, + PciIo, EfiPciIoOperationBusMasterWrite, Packet->InDataBuffer, &InDataBufferLength, &PhysInDataBuffer, &PciAllocMapping ); if (EFI_ERROR (Status)) { @@ -139,7 +139,7 @@ SiI3132AtaPassThruCommand ( OutDataBufferLength = Packet->OutTransferLength * SataDevice->BlockSize; Status = PciIo->Map ( - PciIo, EfiPciIoOperationBusMasterWrite, + PciIo, EfiPciIoOperationBusMasterRead, Packet->OutDataBuffer, &OutDataBufferLength, &PhysOutDataBuffer, &PciAllocMapping ); if (EFI_ERROR (Status)) {