From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-it0-x232.google.com (mail-it0-x232.google.com [IPv6:2607:f8b0:4001:c0b::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 340D921A16EED for ; Thu, 18 May 2017 09:08:52 -0700 (PDT) Received: by mail-it0-x232.google.com with SMTP id w68so20757385itc.0 for ; Thu, 18 May 2017 09:08:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=0M4XDikGK2QkLqpoEjyOWceMxqAovaFskBMMNtLNLm8=; b=JWDrZYJM9qntc4aAa1sD/Py5aFU4iqwAfs0SHRLoIXOvSLNBprhSJzTQPp+kPKXIbZ UwrKhCfGNAv3tS2sRjoZ6gg7zu1ZrQHe9wbmZsxC2TGrnu2L+Y461kKYe842FdZmQgTU JeOy89ca3A/0q88WJq5lTCSuPcVJSHKAXDP7Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=0M4XDikGK2QkLqpoEjyOWceMxqAovaFskBMMNtLNLm8=; b=ad1K3VfxTgtjN8un867QKs9uSQuqqYcQAf0eFteFhUlwf7VcbopV71pgSYL9/pp1Zn S5f4P4EF9+/XlNNLxCiD7Ikynr0oxp/mnqLE8JTdkPOM3ls70RPWNU/L5vKIwMqDxQiX M2hQoGCqg2jI8TnMAwG84W/iMnZvhk5TPL+QsjhcYQ/8h2MNh3TJtvYyP9C8XLtHUS/y zkZ3PAY1BVOyU/KT3w7dAI6tjeRz5QpAsGIeURHmU9cYq+kQG8C4yN6cRlWf6Ma4YpW5 E+QMmXDvCnTEE/hVRB8XYDwkNI8NO+Yz3yRaRyQcGuZi7NEDfORxxRXdtYy/uUEdUzMe Ko7A== X-Gm-Message-State: AODbwcDxpTyaBFJ4yPRWAuRHgqYItwieTZvML7ru5ldVudMuKPfRfpGe lRydrlOM2L8r6rULzaRZGIiSe0K87+9D X-Received: by 10.36.61.211 with SMTP id n202mr3047523itn.98.1495123731373; Thu, 18 May 2017 09:08:51 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.164.24 with HTTP; Thu, 18 May 2017 09:08:50 -0700 (PDT) In-Reply-To: <1494903391-716-1-git-send-email-s.temerkhanov@gmail.com> References: <1494903391-716-1-git-send-email-s.temerkhanov@gmail.com> From: Ard Biesheuvel Date: Thu, 18 May 2017 17:08:50 +0100 Message-ID: To: Sergey Temerkhanov , Leif Lindholm Cc: "edk2-devel@lists.01.org" Subject: Re: [PATCH] Arm: GICv3: Don't access GIC_ICDIPR for interrupts 0..31 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 18 May 2017 16:08:52 -0000 Content-Type: text/plain; charset="UTF-8" On 16 May 2017 at 03:56, Sergey Temerkhanov wrote: > These registers are reserved for PPIs and unimplemented on > some architectures > What do you mean by 'architectures'? Could you elaborate on which SoC needs this? > Signed-off-by: Sergey Temerkhanov > --- > ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > index 8af97a9..dc6b896 100644 > --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > @@ -257,7 +257,7 @@ GicV3DxeInitialize ( > MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE); > } > > - for (Index = 0; Index < mGicNumInterrupts; Index++) { > + for (Index = 32; Index < mGicNumInterrupts; Index++) { > GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index); > > // Set Priority > -- > 2.7.4 > > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel