From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::242; helo=mail-io0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x242.google.com (mail-io0-x242.google.com [IPv6:2607:f8b0:4001:c06::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BF8502034D8DE for ; Wed, 14 Mar 2018 04:18:10 -0700 (PDT) Received: by mail-io0-x242.google.com with SMTP id f1so3963219iob.0 for ; Wed, 14 Mar 2018 04:24:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=uajvwj2TRf7Sit/aO3j0kCCBKz3yUP1w0oR6b5/J+UE=; b=I5/Vpdf3FwszKKfbS4JZ1x7c3mGNHzRlvLEB4ZZlZlGBKfIz3jrVNUkAqrHA/BL+Im L7OazduPqfAwwmFaCSDdVjFg7f7XMkyyad2gGIsP+ig+WDk77i9bp5iuBuJ+nkPgjnPq u0vPUmfPeuVFMz3TkJIkoj3j5/BdDN/A5cRbg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=uajvwj2TRf7Sit/aO3j0kCCBKz3yUP1w0oR6b5/J+UE=; b=TBpi/afR4Oy3/HEw7MkaGVv9YH+EJIPqQ7JiarEjmV2vSUyZ43IXh8VRdYGSzdt3WS N3HXXWDnlTabr0FKrImxnqDWWbJ9ST6/0crZDdp5hVt9Yah9IsHaky3kbt0khY6VXo/1 GS6pkybbANQvHEeva6w1CXRsP/AHt8+oiycWQQOoE41YkQBpWCTH/gHEgES/DPsvwKM7 5cxkZszDbCvEGPMmL+D38zVFyFyyLIEbX/hCSS3X9moggnb22Cn40/0Is96Z+9qq59HL fDm6HcuOCRDK/WX5gSfgY1ZJLS63c8eHlDTYpbY+u6itZ9nss1SLTZZBC4mgDMoe6amV 9teA== X-Gm-Message-State: AElRT7Fm6cDp6HDKFcUlYZ6NFnIPJBaYzY4ajJ9YcS/mPIynwfHilSFl wF8UV5n3j2AL1NjnfOXrVyiSOCi5EL/BzNU57IcLRA== X-Google-Smtp-Source: AG47ELv5DYVNlOHZTciXfeUXmXwiAbOGCIKuqaGAY+N36x1GQJ9E0bBtx/chftfQwzLXQxUtLGIi63SleZIbB6NMh3g= X-Received: by 10.107.151.74 with SMTP id z71mr4022790iod.277.1521026672189; Wed, 14 Mar 2018 04:24:32 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.138.209 with HTTP; Wed, 14 Mar 2018 04:24:31 -0700 (PDT) In-Reply-To: <1519887444-75510-2-git-send-email-heyi.guo@linaro.org> References: <1519887444-75510-1-git-send-email-heyi.guo@linaro.org> <1519887444-75510-2-git-send-email-heyi.guo@linaro.org> From: Ard Biesheuvel Date: Wed, 14 Mar 2018 11:24:31 +0000 Message-ID: To: Heyi Guo , Maurice Ma , Prince Agyeman , Benjamin You Cc: "edk2-devel@lists.01.org" , Ruiyu Ni , Laszlo Ersek Subject: Re: [PATCH v5 1/6] CorebootPayloadPkg/PciHostBridgeLib: Init PCI aperture to 0 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 14 Mar 2018 11:18:11 -0000 Content-Type: text/plain; charset="UTF-8" On 1 March 2018 at 06:57, Heyi Guo wrote: > Use ZeroMem to initialize all fields in temporary > PCI_ROOT_BRIDGE_APERTURE variables to zero. This is not mandatory but > helpful for future extension: when we add new fields to > PCI_ROOT_BRIDGE_APERTURE and the default value of these fields can > safely be zero, this code will not suffer from an additional change. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Heyi Guo > Cc: Maurice Ma > Cc: Prince Agyeman > Cc: Benjamin You > Cc: Ruiyu Ni > Cc: Laszlo Ersek > Cc: Ard Biesheuvel Reviewed-by: Ard Biesheuvel Maurice, Prince, Benjamin: any comments? > --- > CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c > index 6d94ff72c956..c61609b79cce 100644 > --- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c > +++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c > @@ -319,6 +319,11 @@ ScanForRootBridges ( > > *NumberOfRootBridges = 0; > RootBridges = NULL; > + ZeroMem (&Io, sizeof (Io)); > + ZeroMem (&Mem, sizeof (Mem)); > + ZeroMem (&MemAbove4G, sizeof (MemAbove4G)); > + ZeroMem (&PMem, sizeof (PMem)); > + ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G)); > > // > // After scanning all the PCI devices on the PCI root bridge's primary bus, > -- > 2.7.4 >