From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::234; helo=mail-io0-x234.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x234.google.com (mail-io0-x234.google.com [IPv6:2607:f8b0:4001:c06::234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 93A482034D80E for ; Tue, 7 Nov 2017 03:21:18 -0800 (PST) Received: by mail-io0-x234.google.com with SMTP id i38so1752330iod.2 for ; Tue, 07 Nov 2017 03:25:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=zWkN9sEcYXvFR+kagcImAsumzSWqct49WuVpMIVjUWM=; b=IKgTm6beKBhcfXLO0F8Nw8j5zYJM1a/t89GyEU96Oz/y7EpEbbfhNejK40gD27z1vg cuvqN2foxBfX0xT8CHZcQo2ZVG/qk3NeBelBMi0JWEekBv5hTOYPGuZIqHtoZcMSlj4h +eu9omA11CQl81aq69aHwSiKzq+m9s2IN3S+A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=zWkN9sEcYXvFR+kagcImAsumzSWqct49WuVpMIVjUWM=; b=BBAyyHylhTUaskxlNKWJntEX/Jglt3gCdA6qg3qL1/uuypn1+VVh0iZJ3C38476NQr CISSjvLMChY2O1gkx6eAsLQUpwawWcG5OTuT8iVF4OLCRLzZn+J68E3RjFAzOcZ18Y8s n+xVjHAThP7mXKAjPw4sIwWtNv24yuix7RtWyNIrTETfjPZLNhYcfeLZhtSvWz6Skb+P xg96RwUrmSllt62q4TQBaIdl3VPwNOomh0gx1I50exRs6mWyokqs6DpUPn1gF0t+VhmZ MJT5MxPgFNDXkcHwme3B6lRYbMIJp/+I2I4fYTGK+XbVRJzFU2a5Gg2sJmitef3oB9NI 0P7Q== X-Gm-Message-State: AJaThX7M9mUbtlNoWY1OfmduJNwWlvDIj50p8RwSflpFZNT6vH7zNkLx QymAGNrYlPO4yuqQ4nuBMFjA0frtEitG2AXYafTU0A== X-Google-Smtp-Source: ABhQp+QL9RquQUyoCqut7zafhySgyJaVGiM72OgMhplcGomUazs7oBc2WSG8ZGCl12vO/fR1wuxk22uADxLG7+GBS0s= X-Received: by 10.107.174.206 with SMTP id n75mr11002464ioo.43.1510053917482; Tue, 07 Nov 2017 03:25:17 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.131.167 with HTTP; Tue, 7 Nov 2017 03:25:16 -0800 (PST) In-Reply-To: <20171107112326.atof7lwtgxn5s7nv@bivouac.eciton.net> References: <1510052748-5564-1-git-send-email-heyi.guo@linaro.org> <20171107112326.atof7lwtgxn5s7nv@bivouac.eciton.net> From: Ard Biesheuvel Date: Tue, 7 Nov 2017 11:25:16 +0000 Message-ID: To: Leif Lindholm Cc: Heyi Guo , linaro-uefi , "edk2-devel@lists.01.org" , Peicong Li Subject: Re: [RFC] ArmPkg/ArmMmuLib: Add new attribute WRITE_BACK_NONSHARE X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 07 Nov 2017 11:21:18 -0000 Content-Type: text/plain; charset="UTF-8" On 7 November 2017 at 11:23, Leif Lindholm wrote: > On Tue, Nov 07, 2017 at 11:08:39AM +0000, Ard Biesheuvel wrote: >> On 7 November 2017 at 11:05, Heyi Guo wrote: >> > From: Peicong Li >> > >> > Flash region needs to be set as cacheable (write back) to increase >> > performance, if PEI is still XIP on flash or DXE FV is decompressed >> > from flash FV. However some ARM platforms do not support to set flash >> > as inner shareable since flash is not normal DDR memory and it will >> > not respond to cache snoop request, which will causes system hang >> > after MMU is enabled. >> > >> > So we need a new ARM memory region attribute WRITE_BACK_NONSHARE for >> > flash region on these platforms specifically. This attribute will set >> > the region as write back but not inner shared. >> > >> > Contributed-under: TianoCore Contribution Agreement 1.1 >> > Signed-off-by: Peicong Li >> > Signed-off-by: Heyi Guo >> > Cc: Leif Lindholm >> > Cc: Ard Biesheuvel >> > --- >> > ArmPkg/Include/Library/ArmLib.h | 2 ++ >> > ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 4 ++++ >> > 2 files changed, 6 insertions(+) >> > >> > diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h >> > index 24ffe9f..e43e375 100644 >> > --- a/ArmPkg/Include/Library/ArmLib.h >> > +++ b/ArmPkg/Include/Library/ArmLib.h >> > @@ -39,6 +39,8 @@ >> > typedef enum { >> > ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0, >> > ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED, >> > + ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHARE, >> > + ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHARE, >> > ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK, >> > ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK, >> > ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH, >> > diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c >> > index 8bd1c6f..cc10143 100644 >> > --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c >> > +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c >> > @@ -35,6 +35,10 @@ ArmMemoryAttributeToPageAttribute ( >> > ) >> > { >> > switch (Attributes) { >> > + case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHARE: >> > + case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHARE: >> > + return TT_ATTR_INDX_MEMORY_WRITE_BACK; >> > + >> > case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK: >> > case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK: >> > return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE; >> > -- >> > 2.7.2.windows.1 >> > >> >> I'd prefer the name >> ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE but other than >> that, this looks sensible to me. Leif? > > And the same for NONSECURE, yes. > With that modification, this sounds like something absolutely required > in this situation. > > Does this scenario have any further implications for runtime use? > I don't think so. These attributes are only used to select the attributes UEFI uses for its own mapping, and they should only be used for non-DRAM, so they shouldn't leak into the UEFI memory map in a way the OS would be able to notice.