From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::d41; helo=mail-io1-xd41.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io1-xd41.google.com (mail-io1-xd41.google.com [IPv6:2607:f8b0:4864:20::d41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2F6A821962301 for ; Mon, 28 Jan 2019 04:59:44 -0800 (PST) Received: by mail-io1-xd41.google.com with SMTP id m19so13363882ioh.3 for ; Mon, 28 Jan 2019 04:59:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=+GXT8+aIXRUWh5IX2kEpMop25Sg+H5P303DNAlPBLbk=; b=WIZ9oTKITVPqvsGIt12/LOyeNcwkD+EQGhH+0sSOPZGwCKJ6dfu7tg2b64V5crPgtu S9fN2i5tRycfdQh4UM7W8EZv0pPeM8vaFH4vTOukW0INr1cX2YTccj3a+CAGgi9ZaldL nemWsT9L0RO9C44q6OVa5aoakZB5h3YBp5KuM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=+GXT8+aIXRUWh5IX2kEpMop25Sg+H5P303DNAlPBLbk=; b=Kb3cDb7sCmhHazQ2FSWG8B6I7Il+j18BFF8ztG0EfyCO8+csGxcEtNqxMfkhhRn2LX AKmIsbLK8/XZQKaGF6JBAVAebiT/gmr41utRk9VVjXKfYilEQw+h/vJSoXFCtJQ9mLN8 Ngn2SVjhFA/sRM6DcvSnZEW34dsbK+WLYqhcCmTUlTkMmuFJ75/mNm5ZlcbWqGoqPpoM NivRc2BRzONuSNJqzxR+97PbXfyXA93VHXE5/A1gZKTsCHX4+0VYCl1CsTDFYsVCd8Uc OXs1wW2+5xJGKlO6SIVyN5+MuTtzeaoxg5NYH5qqJOO5daIDTWdX9uCQQ5oJPaxGHBj1 6mXg== X-Gm-Message-State: AHQUAubpoJA3dPlprvR4/Gg7a6hsMJ4CK4cJpSL74yJP+IZ2BOxSGtPZ zHfVjqvHB2Y5/CJDNaHJ25Vzsys71PVOyv6yMmR4Ig== X-Google-Smtp-Source: AHgI3IZqP/DtivBy59GARaeY8v386WncI6WlxfIhPEh0tkan+oV815zvZANm7avZaCsxsKYAFLleArtaYq3eLeSc3RU= X-Received: by 2002:a6b:5d01:: with SMTP id r1mr12021071iob.170.1548680383909; Mon, 28 Jan 2019 04:59:43 -0800 (PST) MIME-Version: 1.0 References: <20190128124445.9868-1-pete@akeo.ie> <20190128124445.9868-2-pete@akeo.ie> In-Reply-To: <20190128124445.9868-2-pete@akeo.ie> From: Ard Biesheuvel Date: Mon, 28 Jan 2019 13:59:31 +0100 Message-ID: To: Pete Batard Cc: "edk2-devel@lists.01.org" , Leif Lindholm Subject: Re: [PATCH v3 edk2-platforms 01/23] Silicon/Broadcom/Bcm282x: Add interrupt driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Jan 2019 12:59:45 -0000 X-List-Received-Date: Mon, 28 Jan 2019 12:59:45 -0000 Content-Type: text/plain; charset="UTF-8" Hi Pete, On Mon, 28 Jan 2019 at 13:44, Pete Batard wrote: > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Pete Batard > --- > Silicon/Broadcom/Bcm283x/Bcm283x.dec | 23 ++ > Silicon/Broadcom/Bcm283x/Drivers/InterruptDxe/InterruptDxe.c | 367 ++++++++++++++++++++ > Silicon/Broadcom/Bcm283x/Drivers/InterruptDxe/InterruptDxe.inf | 48 +++ > Silicon/Broadcom/Include/IndustryStandard/Bcm2836.h | 72 ++++ > 4 files changed, 510 insertions(+) > > diff --git a/Silicon/Broadcom/Bcm283x/Bcm283x.dec b/Silicon/Broadcom/Bcm283x/Bcm283x.dec > new file mode 100644 > index 000000000000..8ead5ca87f5d > --- /dev/null > +++ b/Silicon/Broadcom/Bcm283x/Bcm283x.dec > @@ -0,0 +1,23 @@ > +## @file > +# > +# Copyright (c) 2019, Pete Batard > +# > +# This program and the accompanying materials are licensed and made available > +# under the terms and conditions of the BSD License which accompanies this > +# distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR > +# IMPLIED. > +# > +## > + > +[Defines] > + DEC_SPECIFICATION = 0x0001001A > + PACKAGE_NAME = Bcm283xPkg Please remove the 'Pkg' > + PACKAGE_GUID = 900C0F44-1152-4FF9-B9C5-933E2918C831 > + PACKAGE_VERSION = 1.0 > + > +[Includes] > + Silicon/Broadcom/Include Please change this to 'Include', and move whatever resides in Silicon/Broadcom/Include to Silicon/Broadcom/Bcm283x/Include This ensures that the package itself does not depend on the directory structure of the repository it resides in. With that, Reviewed-by: Ard Biesheuvel > diff --git a/Silicon/Broadcom/Bcm283x/Drivers/InterruptDxe/InterruptDxe.c b/Silicon/Broadcom/Bcm283x/Drivers/InterruptDxe/InterruptDxe.c > new file mode 100644 > index 000000000000..9058aa94ffb9 > --- /dev/null > +++ b/Silicon/Broadcom/Bcm283x/Drivers/InterruptDxe/InterruptDxe.c > @@ -0,0 +1,367 @@ > +/** @file > + * > + * Copyright (c) 2016, Linaro, Ltd. All rights reserved. > + * > + * This program and the accompanying materials > + * are licensed and made available under the terms and conditions of the BSD License > + * which accompanies this distribution. The full text of the license may be found at > + * http://opensource.org/licenses/bsd-license.php > + * > + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + * > + **/ > + > +#include > + > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#include > +#include > + > +// > +// This currently only implements support for the architected timer interrupts > +// on the per-CPU interrupt controllers. > +// > +#define NUM_IRQS (4) > + > +#ifdef MDE_CPU_AARCH64 > +#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ > +#else > +#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ > +#endif > + > +STATIC CONST > +EFI_PHYSICAL_ADDRESS RegBase = FixedPcdGet32 (PcdInterruptBaseAddress); > + > +// > +// Notifications > +// > +STATIC EFI_EVENT mExitBootServicesEvent; > +STATIC HARDWARE_INTERRUPT_HANDLER mRegisteredInterruptHandlers[NUM_IRQS]; > + > +/** > + Shutdown our hardware > + > + DXE Core will disable interrupts and turn off the timer and disable interrupts > + after all the event handlers have run. > + > + @param[in] Event The Event that is being processed > + @param[in] Context Event Context > +**/ > +STATIC > +VOID > +EFIAPI > +ExitBootServicesEvent ( > + IN EFI_EVENT Event, > + IN VOID *Context > + ) > +{ > + // Disable all interrupts > + MmioWrite32 (RegBase + BCM2836_INTC_TIMER_CONTROL_OFFSET, 0); > +} > + > +/** > + Enable interrupt source Source. > + > + @param This Instance pointer for this protocol > + @param Source Hardware source of the interrupt > + > + @retval EFI_SUCCESS Source interrupt enabled. > + @retval EFI_DEVICE_ERROR Hardware could not be programmed. > + > +**/ > +STATIC > +EFI_STATUS > +EFIAPI > +EnableInterruptSource ( > + IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, > + IN HARDWARE_INTERRUPT_SOURCE Source > + ) > +{ > + if (Source >= NUM_IRQS) { > + ASSERT (FALSE); > + return EFI_UNSUPPORTED; > + } > + > + MmioOr32 (RegBase + BCM2836_INTC_TIMER_CONTROL_OFFSET, 1 << Source); > + > + return EFI_SUCCESS; > +} > + > + > +/** > + Disable interrupt source Source. > + > + @param This Instance pointer for this protocol > + @param Source Hardware source of the interrupt > + > + @retval EFI_SUCCESS Source interrupt disabled. > + @retval EFI_DEVICE_ERROR Hardware could not be programmed. > + > +**/ > +STATIC > +EFI_STATUS > +EFIAPI > +DisableInterruptSource ( > + IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, > + IN HARDWARE_INTERRUPT_SOURCE Source > + ) > +{ > + if (Source >= NUM_IRQS) { > + ASSERT (FALSE); > + return EFI_UNSUPPORTED; > + } > + > + MmioAnd32 (RegBase + BCM2836_INTC_TIMER_CONTROL_OFFSET, ~(1 << Source)); > + > + return EFI_SUCCESS; > +} > + > +/** > + Register Handler for the specified interrupt source. > + > + @param This Instance pointer for this protocol > + @param Source Hardware source of the interrupt > + @param Handler Callback for interrupt. NULL to unregister > + > + @retval EFI_SUCCESS Source was updated to support Handler. > + @retval EFI_DEVICE_ERROR Hardware could not be programmed. > + > +**/ > +STATIC > +EFI_STATUS > +EFIAPI > +RegisterInterruptSource ( > + IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, > + IN HARDWARE_INTERRUPT_SOURCE Source, > + IN HARDWARE_INTERRUPT_HANDLER Handler > + ) > +{ > + if (Source >= NUM_IRQS) { > + ASSERT (FALSE); > + return EFI_UNSUPPORTED; > + } > + > + if (Handler == NULL && mRegisteredInterruptHandlers[Source] == NULL) { > + return EFI_INVALID_PARAMETER; > + } > + > + if (Handler != NULL && mRegisteredInterruptHandlers[Source] != NULL) { > + return EFI_ALREADY_STARTED; > + } > + > + mRegisteredInterruptHandlers[Source] = Handler; > + return EnableInterruptSource (This, Source); > +} > + > + > +/** > + Return current state of interrupt source Source. > + > + @param This Instance pointer for this protocol > + @param Source Hardware source of the interrupt > + @param InterruptState TRUE: source enabled, FALSE: source disabled. > + > + @retval EFI_SUCCESS InterruptState is valid > + @retval EFI_DEVICE_ERROR InterruptState is not valid > + > +**/ > +STATIC > +EFI_STATUS > +EFIAPI > +GetInterruptSourceState ( > + IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, > + IN HARDWARE_INTERRUPT_SOURCE Source, > + IN BOOLEAN *InterruptState > + ) > +{ > + if (InterruptState == NULL) { > + return EFI_INVALID_PARAMETER; > + } > + > + if (Source >= NUM_IRQS) { > + ASSERT (FALSE); > + return EFI_UNSUPPORTED; > + } > + > + *InterruptState = (MmioRead32 (RegBase + BCM2836_INTC_TIMER_CONTROL_OFFSET) & > + (1 << Source)) != 0; > + > + return EFI_SUCCESS; > +} > + > +/** > + Signal to the hardware that the End Of Intrrupt state > + has been reached. > + > + @param This Instance pointer for this protocol > + @param Source Hardware source of the interrupt > + > + @retval EFI_SUCCESS Source interrupt EOI'ed. > + @retval EFI_DEVICE_ERROR Hardware could not be programmed. > + > +**/ > +STATIC > +EFI_STATUS > +EFIAPI > +EndOfInterrupt ( > + IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This, > + IN HARDWARE_INTERRUPT_SOURCE Source > + ) > +{ > + return EFI_SUCCESS; > +} > + > + > +/** > + EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs. > + > + @param InterruptType Defines the type of interrupt or exception that > + occurred on the processor.This parameter is processor > + architecture specific. > + @param SystemContext A pointer to the processor context when > + the interrupt occurred on the processor. > + > + @return None > + > +**/ > +STATIC > +VOID > +EFIAPI > +IrqInterruptHandler ( > + IN EFI_EXCEPTION_TYPE InterruptType, > + IN EFI_SYSTEM_CONTEXT SystemContext > + ) > +{ > + HARDWARE_INTERRUPT_HANDLER InterruptHandler; > + HARDWARE_INTERRUPT_SOURCE Source; > + UINT32 RegVal; > + > + RegVal = MmioRead32 (RegBase + BCM2836_INTC_TIMER_PENDING_OFFSET) & > + ((1 << NUM_IRQS) - 1); > + Source = HighBitSet32 (RegVal); > + if (Source < 0) { > + return; > + } > + > + InterruptHandler = mRegisteredInterruptHandlers[Source]; > + if (InterruptHandler != NULL) { > + // Call the registered interrupt handler. > + InterruptHandler (Source, SystemContext); > + } > +} > + > +// > +// The protocol instance produced by this driver > +// > +STATIC EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol = { > + RegisterInterruptSource, > + EnableInterruptSource, > + DisableInterruptSource, > + GetInterruptSourceState, > + EndOfInterrupt > +}; > + > +STATIC VOID *mCpuArchProtocolNotifyEventRegistration; > + > +STATIC > +VOID > +EFIAPI > +CpuArchEventProtocolNotify ( > + IN EFI_EVENT Event, > + IN VOID *Context > + ) > +{ > + EFI_CPU_ARCH_PROTOCOL *Cpu; > + EFI_STATUS Status; > + > + // > + // Get the CPU protocol that this driver requires. > + // > + Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID**)&Cpu); > + if (EFI_ERROR (Status)) { > + return; > + } > + > + // > + // Unregister the default exception handler. > + // > + Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, NULL); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n", > + __FUNCTION__, Status)); > + ASSERT (FALSE); > + return; > + } > + > + // > + // Register to receive interrupts > + // > + Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, IrqInterruptHandler); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n", > + __FUNCTION__, Status)); > + ASSERT (FALSE); > + return; > + } > +} > + > + > +/** > + Initialize the state information for the CPU Architectural Protocol > + > + @param ImageHandle of the loaded driver > + @param SystemTable Pointer to the System Table > + > + @retval EFI_SUCCESS Protocol registered > + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure > + @retval EFI_DEVICE_ERROR Hardware problems > + > +**/ > +EFI_STATUS > +InterruptDxeInitialize ( > + IN EFI_HANDLE ImageHandle, > + IN EFI_SYSTEM_TABLE *SystemTable > + ) > +{ > + EFI_STATUS Status; > + EFI_EVENT CpuArchEvent; > + > + // Make sure the Interrupt Controller Protocol is not already installed in the system. > + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid); > + > + Status = gBS->InstallMultipleProtocolInterfaces ( > + &ImageHandle, > + &gHardwareInterruptProtocolGuid, > + &gHardwareInterruptProtocol, > + NULL > + ); > + ASSERT_EFI_ERROR (Status); > + > + // > + // Install the interrupt handler as soon as the CPU arch protocol appears. > + // > + CpuArchEvent = EfiCreateProtocolNotifyEvent ( > + &gEfiCpuArchProtocolGuid, > + TPL_CALLBACK, > + CpuArchEventProtocolNotify, > + NULL, > + &mCpuArchProtocolNotifyEventRegistration > + ); > + ASSERT (CpuArchEvent != NULL); > + > + // Register for an ExitBootServicesEvent > + Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY, > + ExitBootServicesEvent, NULL, &mExitBootServicesEvent); > + > + ASSERT_EFI_ERROR (Status); > + > + return Status; > +} > diff --git a/Silicon/Broadcom/Bcm283x/Drivers/InterruptDxe/InterruptDxe.inf b/Silicon/Broadcom/Bcm283x/Drivers/InterruptDxe/InterruptDxe.inf > new file mode 100644 > index 000000000000..5812e48dbb7a > --- /dev/null > +++ b/Silicon/Broadcom/Bcm283x/Drivers/InterruptDxe/InterruptDxe.inf > @@ -0,0 +1,48 @@ > +#/** @file > +# > +# Copyright (c) 2017, Andrei Warkentin > +# Copyright (c) 2016 Linaro, Ltd. All rights reserved. > +# > +# This program and the accompanying materials > +# are licensed and made available under the terms and conditions of the BSD License > +# which accompanies this distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +# > +#**/ > + > +[Defines] > + INF_VERSION = 0x0001001A > + BASE_NAME = InterruptDxe > + FILE_GUID = 3944f2d7-2e09-4fc0-9e98-008375641453 > + MODULE_TYPE = DXE_DRIVER > + VERSION_STRING = 1.0 > + ENTRY_POINT = InterruptDxeInitialize > + > +[Sources] > + InterruptDxe.c > + > +[Packages] > + MdePkg/MdePkg.dec > + EmbeddedPkg/EmbeddedPkg.dec > + Silicon/Broadcom/Bcm283x/Bcm283x.dec > + > +[LibraryClasses] > + BaseLib > + DebugLib > + IoLib > + UefiBootServicesTableLib > + UefiLib > + UefiDriverEntryPoint > + > +[Protocols] > + gHardwareInterruptProtocolGuid ## PRODUCES > + gEfiCpuArchProtocolGuid ## CONSUMES ## NOTIFY > + > +[FixedPcd] > + gEmbeddedTokenSpaceGuid.PcdInterruptBaseAddress > + > +[Depex] > + TRUE > diff --git a/Silicon/Broadcom/Include/IndustryStandard/Bcm2836.h b/Silicon/Broadcom/Include/IndustryStandard/Bcm2836.h > new file mode 100644 > index 000000000000..f9fffb764649 > --- /dev/null > +++ b/Silicon/Broadcom/Include/IndustryStandard/Bcm2836.h > @@ -0,0 +1,72 @@ > +/** @file > + * > + * Copyright (c) 2017, Andrei Warkentin > + * Copyright (c) 2016, Linaro Limited. All rights reserved. > + * > + * Redistribution and use in source and binary forms, with or without > + * modification, are permitted provided that the following conditions are met: > + * > + * Redistributions of source code must retain the above copyright notice, this > + * list of conditions and the following disclaimer. > + * > + * Redistributions in binary form must reproduce the above copyright notice, > + * this list of conditions and the following disclaimer in the documentation > + * and/or other materials provided with the distribution. > + * > + * Neither the name of ARM nor the names of its contributors may be used > + * to endorse or promote products derived from this software without specific > + * prior written permission. > + * > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" > + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE > + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE > + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE > + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR > + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF > + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS > + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN > + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) > + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE > + * POSSIBILITY OF SUCH DAMAGE. > + * > + **/ > + > +#ifndef __BCM2836_H__ > +#define __BCM2836_H__ > + > +/* > + * Both "core" and SoC perpherals (1M each). > + */ > +#define BCM2836_SOC_REGISTERS 0x3f000000 > +#define BCM2836_SOC_REGISTER_LENGTH 0x02000000 > + > +/* > + * Offset between the CPU's view and the VC's view of system memory. > + */ > +#define BCM2836_DMA_DEVICE_OFFSET 0xc0000000 > + > +/* watchdog constants */ > +#define BCM2836_WDOG_BASE_ADDRESS 0x3f100000 > +#define BCM2836_WDOG_PASSWORD 0x5a000000 > +#define BCM2836_WDOG_RSTC_OFFSET 0x0000001c > +#define BCM2836_WDOG_WDOG_OFFSET 0x00000024 > +#define BCM2836_WDOG_RSTC_WRCFG_MASK 0x00000030 > +#define BCM2836_WDOG_RSTC_WRCFG_FULL_RESET 0x00000020 > + > +/* mailbox interface constants */ > +#define BCM2836_MBOX_BASE_ADDRESS 0x3f00b880 > +#define BCM2836_MBOX_READ_OFFSET 0x00000000 > +#define BCM2836_MBOX_STATUS_OFFSET 0x00000018 > +#define BCM2836_MBOX_CONFIG_OFFSET 0x0000001c > +#define BCM2836_MBOX_WRITE_OFFSET 0x00000020 > + > +#define BCM2836_MBOX_STATUS_FULL 0x1f > +#define BCM2836_MBOX_STATUS_EMPTY 0x1e > + > +#define BCM2836_MBOX_NUM_CHANNELS 16 > + > +/* interrupt controller constants */ > +#define BCM2836_INTC_TIMER_CONTROL_OFFSET 0x00000040 > +#define BCM2836_INTC_TIMER_PENDING_OFFSET 0x00000060 > + > +#endif /*__BCM2836_H__ */ > -- > 2.17.0.windows.1 >