From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::244; helo=mail-io0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x244.google.com (mail-io0-x244.google.com [IPv6:2607:f8b0:4001:c06::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5389A2034A76E for ; Tue, 28 Nov 2017 05:32:59 -0800 (PST) Received: by mail-io0-x244.google.com with SMTP id i184so886446ioa.0 for ; Tue, 28 Nov 2017 05:37:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=9m+kyvz733bMCndx2sK8yks6oHuE2A0W9HrMKzK3BU4=; b=PYQvIEsta08SSiCH1Vj6MriJCWgm2wSk5iw+LFUzD41b34piCxVgkjMwmmkgaJ3Wkv iAEle4CnWTgkzuWIauIh5Fiuo4BCwj9Z72rzNkjptk/Ixm3cWJcc3m5hY+wR3MbCKEDk YLGNfkJOapQJwjGp8t0hhnJQOSOFg2mZdqo4w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=9m+kyvz733bMCndx2sK8yks6oHuE2A0W9HrMKzK3BU4=; b=EXprz03kbrlyeq6QmyD5Zp0dLmS5yWZN7KvpPc/KrX9B7pMDMNIh6ewdIC6/if/1RO nL23p2MQHFU0mJ2D2fwZOZgBUe11m4QPh1t/KHnmC/TYHLLcA0p+OrfsaRy4RpiDPp8i wY2S442vnH8BlS2J+tuQMwyW+A+dowcjq5ydrI5zouuom9TBB1xi7Ll4pZwqh21EKMHD XWeB7Oa/TWVQx34uJY3VRskz//Y5oDYR+Tm85C2LrMRmmMB7njqYsASQbAe79dx5WCPO izRvvDanYVX47K2y89h9zoPUe7hr7hJdi1ZDC3oa4+t25mJYZiEOz2aqqwV2CbHjEwbp m9Fw== X-Gm-Message-State: AJaThX69gjlnL11zSmvzOPZBoY0jFCjXY5/4eXsBa4SQntqqPJCMWJ0Q 1q4pE/JNzIWLD+lg2hFQttbGbvK0OL85FMF51IuAWOHL X-Google-Smtp-Source: AGs4zMai8K0pZPJ1WU2Z6HIFIFtfEzcHGpVIGiQ/W+qYCPE8I/SpD339T0e8luCYb6tDMk9DqvBwJIr+2+JL+aD0/PU= X-Received: by 10.107.59.85 with SMTP id i82mr90002ioa.253.1511876241149; Tue, 28 Nov 2017 05:37:21 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.104.16 with HTTP; Tue, 28 Nov 2017 05:37:20 -0800 (PST) In-Reply-To: <20171128132807.16701-1-ard.biesheuvel@linaro.org> References: <20171128132807.16701-1-ard.biesheuvel@linaro.org> From: Ard Biesheuvel Date: Tue, 28 Nov 2017 13:37:20 +0000 Message-ID: To: "edk2-devel@lists.01.org" , Leif Lindholm , Daniel Thompson Cc: masahisa.kojima@socionext.com, =?UTF-8?B?UGlwYXQv44Oh44K/44Ov44OL44OD44OI44Od44OzIOODlOODkeODg+ODiA==?= , Ard Biesheuvel Subject: Re: [PATCH edk2-platforms] Silicon/SynQuacer: enable coherent DMA for NETSEC and eMMC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Nov 2017 13:32:59 -0000 Content-Type: text/plain; charset="UTF-8" On 28 November 2017 at 13:28, Ard Biesheuvel wrote: > As it turns out, it is surprisingly easy to configure both the NETSEC > and eMMC devices as cache coherent for DMA, given that they are both > behind the same SMMU which is already configured in passthrough mode. > > So update the static SMMU configuration to make memory accesses performed > by these devices inner shareable, inner/outer writeback cacheable, which > makes them cache coherent with the CPUs. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 2 +- > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 2 ++ > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 2 +- > Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 23 ++++++++++++++++++++ > Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 ++++ > Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 3 +++ > 6 files changed, 34 insertions(+), 2 deletions(-) > > diff --git a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc > index 7245240012bc..dd4a7f9baf69 100644 > --- a/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc > +++ b/Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc > @@ -597,7 +597,7 @@ [Components.common] > NetworkPkg/HttpBootDxe/HttpBootDxe.inf > Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf { > > - DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf > + DmaLib|EmbeddedPkg/Library/CoherentDmaLib/CoherentDmaLib.inf > } > > # Note: this hunk ^^^ needs to be applied to DeveloperBox.dsc as well. > diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > index 7c791de213c7..c9fee5d1f350 100644 > --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > @@ -456,6 +456,7 @@ > max-speed = <1000>; > max-frame-size = <9000>; > phy-handle = <ðphy0>; > + dma-coherent; > > #address-cells = <1>; > #size-cells = <0>; > @@ -557,6 +558,7 @@ > fujitsu,cmd-dat-delay-select; > clocks = <&clk_alw_c_0 &clk_alw_b_0>; > clock-names = "core", "iface"; > + dma-coherent; > status = "disabled"; > }; > }; > diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c > index 9b1957e99907..1c38b3706f9d 100644 > --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c > +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c > @@ -185,7 +185,7 @@ RegisterEmmc ( > > Status = RegisterNonDiscoverableMmioDevice ( > NonDiscoverableDeviceTypeSdhci, > - NonDiscoverableDeviceDmaTypeNonCoherent, > + NonDiscoverableDeviceDmaTypeCoherent, > NULL, > &mSdMmcControllerHandle, > 1, > diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c > index b28d05650bb5..acb3e0272d3f 100644 > --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c > +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c > @@ -181,6 +181,27 @@ I2cEnumerate ( > return EFI_SUCCESS; > } > > +#define SMMU_SCR0 0x0 > +#define SMMU_SCR0_SHCFG_INNER (0x2 << 22) > +#define SMMU_SCR0_MTCFG (0x1 << 20) > +#define SMMU_SCR0_MEMATTR_INNER_OUTER_WB (0xf << 16) > + > +STATIC > +VOID > +SmmuEnableCoherentDma ( > + VOID > + ) > +{ > + // > + // The SCB SMMU (MMU-500) is shared between the NETSEC and eMMC devices, and > + // is configured in passthrough mode by default. Let's set the global memory > + // type override as well, so that all memory accesses by these devices are > + // inner shareable inner/outer writeback cacheable. > + // > + MmioOr32 (SYNQUACER_SCB_SMMU_BASE + SMMU_SCR0, > + SMMU_SCR0_SHCFG_INNER | SMMU_SCR0_MTCFG | SMMU_SCR0_MEMATTR_INNER_OUTER_WB); > +} > + > STATIC > EFI_STATUS > EFIAPI > @@ -272,5 +293,7 @@ PlatformDxeEntryPoint ( > NULL); > ASSERT_EFI_ERROR (Status); > > + SmmuEnableCoherentDma (); > + > return EFI_SUCCESS; > } > diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h > index 3c7bd58866cc..f43adcc8607f 100644 > --- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h > +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h > @@ -65,4 +65,8 @@ > #define SYNQUACER_PCIE_BASE 0x58200000 > #define SYNQUACER_PCIE_SIZE 0x00200000 > > +// SCB SMMU > +#define SYNQUACER_SCB_SMMU_BASE 0x52E00000 > +#define SYNQUACER_SCB_SMMU_SIZE SIZE_64KB > + > #endif > diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c > index a640b3e0c0d1..1402ecafce4a 100644 > --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c > +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c > @@ -115,6 +115,9 @@ STATIC CONST ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = { > FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize)), > ARM_DEVICE_REGION (FixedPcdGet32 (PcdFlashNvStorageFtwSpareBase), > FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize)), > + > + // NETSEC/eMMC SMMU > + ARM_DEVICE_REGION (SYNQUACER_SCB_SMMU_BASE, SYNQUACER_SCB_SMMU_SIZE), > }; > > STATIC > -- > 2.11.0 >