public inbox for devel@edk2.groups.io
 help / color / mirror / Atom feed
From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: Ming <ming.huang@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>,
	linaro-uefi <linaro-uefi@lists.linaro.org>,
	 "edk2-devel@lists.01.org" <edk2-devel@lists.01.org>,
	Graeme Gregory <graeme.gregory@linaro.org>,
	guoheyi@huawei.com,  wanghuiqiang <wanghuiqiang@huawei.com>,
	huangming <huangming23@huawei.com>,
	 Jason Zhang <zhangjinsong2@huawei.com>,
	huangdaode@hisilicon.com,  John Garry <john.garry@huawei.com>,
	Heyi Guo <heyi.guo@linaro.org>
Subject: Re: [PATCH edk2-platforms v1 4/6] Hisilicon/D05: Add PlatformMiscDxe driver
Date: Thu, 28 Jun 2018 12:54:24 +0200	[thread overview]
Message-ID: <CAKv+Gu9wqJ4GNjLk31DrP5Q1pjBHCYjE84rtmn8eAO3yrMFGnw@mail.gmail.com> (raw)
In-Reply-To: <d4c99a0d-c906-807d-13d2-78adbba4a042@linaro.org>

On 28 June 2018 at 04:26, Ming <ming.huang@linaro.org> wrote:
>
>
> 在 2018/6/27 15:33, Ard Biesheuvel 写道:
>> On 27 June 2018 at 09:04, Ming Huang <ming.huang@linaro.org> wrote:
>>> Fix the issue of onboard Nic not work kerenl with AMD GPU and
>>> NVME SSD in board. The GPU don't support 64 MSI, so need to
>>> allocate INTx, but the default interrupt number 255 is invalid,
>>> so Change all the PCI Device interrupt number to 0.
>>>
>>
>> Could you please try to explain in more detail what the problem is you
>> are solving, and why you think it should be solved in the firmware?
>> What does '64 MSI' mean? And where does the default of 255 come from?
>>
>>
>
> With AMD GPU and NVMe in board, the onboard Nic(hns-nic) can not work in ubuntu os.
> The AMD GPU has two devices:
> PCI device amdgpu 000d:33:00.0, snd_hda_intel 000d:33:00.1
> The MSI is 64bit address in D05, and snd_hda_intel don't support 64bit MSI address,

Legacy PCIe endpoints are permitted to only implement support for
32-bit addressing of the MSI doorbell register, which is why it is
generally a good idea to put that below 4 GB in the physical address
space.

So how is this implemented on D05? How are the PCIe host bridge
inbound windows configured? Any chance you could fix this by remapping
inbound transactions so the MSI doorbell appears at a 32-bit
addressable offset?


> so snd_hda_intel use the 255 irq. The onboard Nic register 255 irq failed.
> The 255 is the default value of PCI_INTERRUPT_LINE reg (0x3C).
> There is not a proper solution in kernel.This patch is a workaround in firmware.
>
> error log in kernel:
>  Mar  1 00:27:07 ubuntu kernel: [   25.581265] snd_hda_intel 000d:33:00.1: Device has broken 64-bit MSI but arch tried to assign one above 4Gl
>
> Mar  1 00:36:39 ubuntu kernel: [  600.751276] genirq: Flags mismatch irq 255. 00000001 (enahisic2i0-tx1) vs. 00000081 (snd_hda_intel:card0)
>
> Mar  1 00:36:39 ubuntu kernel: [  600.761137] hns-nic HISI00C2:00 enahisic2i0: request irq(255) fail
>
> Thanks.
>
>>
>>> Contributed-under: TianoCore Contribution Agreement 1.1
>>> Signed-off-by: Ming Huang <ming.huang@linaro.org>
>>> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
>>> ---
>>>  Platform/Hisilicon/D05/D05.dsc                                     |  1 +
>>>  Platform/Hisilicon/D05/D05.fdf                                     |  1 +
>>>  Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c   | 99 ++++++++++++++++++++
>>>  Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf | 47 ++++++++++
>>>  4 files changed, 148 insertions(+)
>>>
>>> diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
>>> index b6e1a9d98a..0e6d5912a0 100644
>>> --- a/Platform/Hisilicon/D05/D05.dsc
>>> +++ b/Platform/Hisilicon/D05/D05.dsc
>>> @@ -629,6 +629,7 @@
>>>
>>>
>>>    Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
>>> +  Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf
>>>
>>>    #
>>>    # Memory test
>>> diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
>>> index 37d9cc0c18..32374e245e 100644
>>> --- a/Platform/Hisilicon/D05/D05.fdf
>>> +++ b/Platform/Hisilicon/D05/D05.fdf
>>> @@ -358,6 +358,7 @@ READ_LOCK_STATUS   = TRUE
>>>    INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
>>>    INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
>>>    INF Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
>>> +  INF Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf
>>>
>>>    INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
>>>
>>> diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c
>>> new file mode 100644
>>> index 0000000000..8519b7139d
>>> --- /dev/null
>>> +++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c
>>> @@ -0,0 +1,99 @@
>>> +/** @file
>>> +*
>>> +*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
>>> +*  Copyright (c) 2016, Linaro Limited. All rights reserved.
>>> +*
>>> +*  This program and the accompanying materials
>>> +*  are licensed and made available under the terms and conditions of the BSD License
>>> +*  which accompanies this distribution.  The full text of the license may be found at
>>> +*  http://opensource.org/licenses/bsd-license.php
>>> +*
>>> +*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>>> +*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>>> +*
>>> +**/
>>> +
>>> +#include <Uefi.h>
>>> +#include <IndustryStandard/Pci.h>
>>> +#include <Library/DebugLib.h>
>>> +#include <Library/UefiBootServicesTableLib.h>
>>> +#include <Protocol/PciIo.h>
>>> +
>>> +VOID
>>> +SetIntLine (
>>> +  )
>>> +{
>>> +  EFI_STATUS                         Status;
>>> +  UINTN                              HandleIndex;
>>> +  EFI_HANDLE                         *HandleBuffer;
>>> +  UINTN                              HandleCount;
>>> +  EFI_PCI_IO_PROTOCOL                *PciIo;
>>> +  UINT8                              INTLine;
>>> +  UINTN                              Segment;
>>> +  UINTN                              Bus;
>>> +  UINTN                              Device;
>>> +  UINTN                              Fun;
>>> +
>>> +  Status = gBS->LocateHandleBuffer (
>>> +                  ByProtocol,
>>> +                  &gEfiPciIoProtocolGuid,
>>> +                  NULL,
>>> +                  &HandleCount,
>>> +                  &HandleBuffer
>>> +                  );
>>> +  if (EFI_ERROR (Status)) {
>>> +      DEBUG  ((DEBUG_ERROR, " Locate gEfiPciIoProtocol Failed.\n"));
>>> +      gBS->FreePool ((VOID *)HandleBuffer);
>>> +      return;
>>> +  }
>>> +
>>> +  for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) {
>>> +      Status = gBS->HandleProtocol (
>>> +                      HandleBuffer[HandleIndex],
>>> +                      &gEfiPciIoProtocolGuid,
>>> +                      (VOID **)&PciIo
>>> +                      );
>>> +      if (EFI_ERROR (Status)) {
>>> +          continue;
>>> +      }
>>> +
>>> +      INTLine = 0;
>>> +      (VOID)PciIo->Pci.Write (
>>> +                         PciIo,
>>> +                         EfiPciIoWidthUint8,
>>> +                         PCI_INT_LINE_OFFSET,
>>> +                         1,
>>> +                         &INTLine);
>>> +      (VOID)PciIo->GetLocation (PciIo, &Segment, &Bus, &Device, &Fun);
>>> +      DEBUG ((DEBUG_INFO, "Set BDF(%x-%x-%x) IntLine to 0\n", Bus, Device, Fun));
>>> +  }
>>> +
>>> +  gBS->FreePool ((VOID *)HandleBuffer);
>>> +  return;
>>> +}
>>> +
>>> +EFI_STATUS
>>> +EFIAPI
>>> +PlatformMiscDxeEntry (
>>> +  IN EFI_HANDLE           ImageHandle,
>>> +  IN EFI_SYSTEM_TABLE     *SystemTable
>>> +  )
>>> +{
>>> +  EFI_STATUS  Status;
>>> +  EFI_EVENT   Event;
>>> +
>>> +  Status = gBS->CreateEventEx (
>>> +                  EVT_NOTIFY_SIGNAL,
>>> +                  TPL_CALLBACK,
>>> +                  SetIntLine,
>>> +                  NULL,
>>> +                  &gEfiEventReadyToBootGuid,
>>> +                  &Event
>>> +                  );
>>> +  if (EFI_ERROR (Status)) {
>>> +    DEBUG ((DEBUG_ERROR, "Create event for SetIntLine, %r!\n", Status));
>>> +  }
>>> +
>>> +  return EFI_SUCCESS;
>>> +}
>>> +
>>> diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf
>>> new file mode 100644
>>> index 0000000000..0b365e7a53
>>> --- /dev/null
>>> +++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf
>>> @@ -0,0 +1,47 @@
>>> +#/** @file
>>> +#
>>> +#    Copyright (c) 2018, Hisilicon Limited. All rights reserved.
>>> +#    Copyright (c) 2016, Linaro Limited. All rights reserved.
>>> +#
>>> +#    This program and the accompanying materials
>>> +#    are licensed and made available under the terms and conditions of the BSD License
>>> +#    which accompanies this distribution. The full text of the license may be found at
>>> +#    http://opensource.org/licenses/bsd-license.php
>>> +#
>>> +#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>>> +#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>>> +#
>>> +#**/
>>> +
>>> +[Defines]
>>> +  INF_VERSION                    = 0x0001001A
>>> +  BASE_NAME                      = PlatformMiscDxe
>>> +  FILE_GUID                      = a48f7a09-253f-468b-87c6-caf78baf47bb
>>> +  MODULE_TYPE                    = DXE_DRIVER
>>> +  VERSION_STRING                 = 1.0
>>> +  ENTRY_POINT                    = PlatformMiscDxeEntry
>>> +
>>> +[Sources.common]
>>> +  PlatformMiscDxe.c
>>> +
>>> +[Packages]
>>> +  MdeModulePkg/MdeModulePkg.dec
>>> +  MdePkg/MdePkg.dec
>>> +  Silicon/Hisilicon/HisiPkg.dec
>>> +
>>> +[Guids]
>>> +  gEfiEventReadyToBootGuid
>>> +
>>> +[Protocols]
>>> +  gEfiPciIoProtocolGuid
>>> +
>>> +[LibraryClasses]
>>> +  BaseLib
>>> +  DebugLib
>>> +  UefiBootServicesTableLib
>>> +  UefiDriverEntryPoint
>>> +
>>> +[FixedPcd]
>>> +
>>> +[Depex]
>>> +  TRUE
>>> --
>>> 2.17.0
>>>


  parent reply	other threads:[~2018-06-28 10:54 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-27  7:04 [PATCH edk2-platforms v1 0/6] Improve D0x platforms and bug fix Ming Huang
2018-06-27  7:04 ` [PATCH edk2-platforms v1 1/6] Hisilicon/D0x: Fix invoke SetMemorySpaceAttributes error bug Ming Huang
2018-06-27  7:20   ` Ard Biesheuvel
2018-07-03  9:53     ` Ming
2018-07-04  6:46     ` Ming
2018-06-27  7:04 ` [PATCH edk2-platforms v1 2/6] Hisilicon/D03/D05: Correct ATU Cfg0/Cfg1 base address Ming Huang
2018-06-27  7:26   ` Ard Biesheuvel
2018-06-27  7:04 ` [PATCH edk2-platforms v1 3/6] Hisilicon/D0x: Fix SetAtuConfig1RW bug Ming Huang
2018-06-27  7:04 ` [PATCH edk2-platforms v1 4/6] Hisilicon/D05: Add PlatformMiscDxe driver Ming Huang
2018-06-27  7:33   ` Ard Biesheuvel
     [not found]     ` <d4c99a0d-c906-807d-13d2-78adbba4a042@linaro.org>
2018-06-28 10:54       ` Ard Biesheuvel [this message]
2018-06-29  7:26         ` Ming
2018-06-27  7:04 ` [PATCH edk2-platforms v1 5/6] Hisilicon/D05/Pcie: optimize two pcie ports space Ming Huang
2018-06-27  7:35   ` Ard Biesheuvel
2018-06-27  7:04 ` [PATCH edk2-platforms v1 6/6] Hisilicon/D0x: Correct smbios product name Ming Huang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-list from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=CAKv+Gu9wqJ4GNjLk31DrP5Q1pjBHCYjE84rtmn8eAO3yrMFGnw@mail.gmail.com \
    --to=devel@edk2.groups.io \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox