From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::241; helo=mail-it0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x241.google.com (mail-it0-x241.google.com [IPv6:2607:f8b0:4001:c0b::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6C9B5224A9ED6 for ; Fri, 30 Mar 2018 08:19:40 -0700 (PDT) Received: by mail-it0-x241.google.com with SMTP id r19-v6so12105906itc.0 for ; Fri, 30 Mar 2018 08:19:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=j0mzOInAIu8uBp39u3V4CU1FQVk/UB7tefph44gaGXY=; b=a5tG4UGk5/xod0DgoP3XlHa2zV4S9IOds8dKrsSNDqUURcRDbD1J0ODQ+QhrQpI+K9 jpXqK0IZ+NqUJlwFF58eS+tcq0BZY0Iq1Wdb6kZytVvBePJyJFlONjafKrvf3OoRBQ4N zShquLGcQXJfpOqQegmlXXwAvHJ0/ABEvY6OI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=j0mzOInAIu8uBp39u3V4CU1FQVk/UB7tefph44gaGXY=; b=p03tikLaxvcYzuhyEg59xHcwGw2mnuDwu2kHuRE0/Bkm2p66VhRp5zamOvkYWpqwh0 ekWMaj/P76mpHui1bnbTIRSFPR6/lRUr+IZX1lbu1poC+Pd8YWYCYwnGw9c+4VDEmqnM uKCtTu+nEBR97oLpzAkCgYsxOkZp3N8zBK+kz/qzKYglNTnNI/ECVodCy2Ml0NIEKt/j h2Jo0BHLeTRJhmDXsTfvRjaODcBMDCBNdLNSKLnxlzkV8PpYcjv9V4mxMRVxVWOMJcFH OWQ+lwXYIWY4W9DxiHtYW1Awqej6KRXAPMh85YI2fuPAM7/jBbWDH/D9dv35ZindXuXK zR5w== X-Gm-Message-State: ALQs6tDcHj6hiWFANOgaIqXft+/wU8F+I5iKL4aUaZNRRIoQH2bHD+us vNU0BfTjRWaz1/qqq5PszLa8oMkLWeVOHLkqXYtSUA== X-Google-Smtp-Source: AIpwx4+JIA11jC32iKQcxF7epKDX0cJBilbydWGlMlCzq8G267Xi4FhNwhLNT1q8xqkDzqHwyAIMh5nSBWSswsO1BsY= X-Received: by 2002:a24:9c82:: with SMTP id b124-v6mr3397205ite.42.1522423179084; Fri, 30 Mar 2018 08:19:39 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.187.67 with HTTP; Fri, 30 Mar 2018 08:19:38 -0700 (PDT) In-Reply-To: <1521594198-52523-4-git-send-email-heyi.guo@linaro.org> References: <1521594198-52523-1-git-send-email-heyi.guo@linaro.org> <1521594198-52523-4-git-send-email-heyi.guo@linaro.org> From: Ard Biesheuvel Date: Fri, 30 Mar 2018 16:19:38 +0100 Message-ID: To: Heyi Guo Cc: "edk2-devel@lists.01.org" , Leif Lindholm , Michael D Kinney Subject: Re: [PATCH edk2-platforms 03/12] Hisilicon/Pci: move ATU configuration to PcieInitDxe X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 30 Mar 2018 15:19:40 -0000 Content-Type: text/plain; charset="UTF-8" On 21 March 2018 at 01:03, Heyi Guo wrote: > This is to prepare for switching to generic PciHostBridge driver, so > we move all platform specific code to platform specific drivers, not > in PciHostBridge driver. > > This patch moves ATU initialization to PcieInitDxe driver. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Heyi Guo > Cc: Ard Biesheuvel > Cc: Leif Lindholm > Cc: Michael D Kinney > --- > Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf | 1 + > Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 2 + > Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 106 --------------- > Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c | 3 + > Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c | 141 ++++++++++++++++++++ > 5 files changed, 147 insertions(+), 106 deletions(-) > > diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf > index 61b091f659b3..cb0a63f9a84e 100644 > --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf > +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf > @@ -25,6 +25,7 @@ [Defines] > [Sources] > PcieInit.c > PcieInitLib.c > + PcieInitAtu.c > > [Packages] > MdePkg/MdePkg.dec > diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h > index e96c53c4fe4e..87700ae8b9aa 100644 > --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h > +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h > @@ -246,4 +246,6 @@ EFI_STATUS PcieWaitLinkUp(UINT32 Port); > > EFI_STATUS PcieSetDBICS2Enable(UINT32 HostBridgeNum, UINT32 Port, UINT32 Enable); > > +VOID InitAtu (PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Private); APPETURE is not a word. This should be APERTURE. I know this occurs in existing code, and so I won't block this series for it, but could you please post a followup patch that replaces all occurrences of 'appeture' with 'aperture'? Thanks. > + > #endif > diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c > index 55b80aa4e49a..273a322ee48f 100644 > --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c > +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c > @@ -633,111 +633,6 @@ UINT64 GetPcieCfgAddress ( > } > > > -void SetAtuConfig0RW ( > - PCI_ROOT_BRIDGE_INSTANCE *Private, > - UINT32 Index > - ) > -{ > - UINTN RbPciBase = Private->RbPciBar; > - UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 1, 1, 0, 0) - 1; > - > - > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam)); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32)); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG0); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE); > - > - { > - UINTN i; > - for (i=0; i<0x20; i+=4) { > - DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i))); > - } > - } > -} > - > -void SetAtuConfig1RW ( > - PCI_ROOT_BRIDGE_INSTANCE *Private, > - UINT32 Index > - ) > -{ > - UINTN RbPciBase = Private->RbPciBar; > - UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1; > - > - > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam)); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32)); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE); > - > - { > - UINTN i; > - for (i=0; i<0x20; i+=4) { > - DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i))); > - } > - } > -} > - > -void SetAtuIoRW(UINT64 RbPciBase,UINT64 IoBase,UINT64 CpuIoRegionLimit, UINT64 CpuIoRegionBase, UINT32 Index) > -{ > - > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_IO); > - > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuIoRegionBase)); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)CpuIoRegionBase >> 32)); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuIoRegionLimit)); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(IoBase)); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(IoBase) >> 32)); > - > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE); > - > - { > - UINTN i; > - for (i=0; i<0x20; i+=4) { > - DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i))); > - } > - } > -} > - > -void SetAtuMemRW(UINT64 RbPciBase,UINT64 MemBase,UINT64 CpuMemRegionLimit, UINT64 CpuMemRegionBase, UINT32 Index) > -{ > - > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_MEM); > - > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuMemRegionBase)); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(CpuMemRegionBase) >> 32)); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuMemRegionLimit)); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(MemBase)); > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(MemBase) >> 32)); > - > - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE); > - > - { > - UINTN i; > - for (i=0; i<0x20; i+=4) { > - DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i))); > - } > - } > -} > - > -VOID InitAtu (PCI_ROOT_BRIDGE_INSTANCE *Private) > -{ > - SetAtuMemRW (Private->RbPciBar, Private->PciRegionBase, Private->PciRegionLimit, Private->CpuMemRegionBase, 0); > - SetAtuConfig0RW (Private, 1); > - SetAtuConfig1RW (Private, 2); > - SetAtuIoRW (Private->RbPciBar, Private->IoBase, Private->IoLimit, Private->CpuIoRegionBase, 3); > -} > - > - > BOOLEAN PcieIsLinkUp (UINT32 SocType, UINTN RbPciBar, UINTN Port) > { > UINT32 Value = 0; > @@ -860,7 +755,6 @@ RootBridgeConstructor ( > > Protocol->SegmentNumber = Seg; > > - InitAtu (PrivateData); > > Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **)&mMetronome); > if (EFI_ERROR(Status)) > diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c > index 5fc0ead5c1d5..de297e67e2e1 100644 > --- a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c > +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInit.c > @@ -17,6 +17,7 @@ > #include > #include > #include > +#include > #include > > > @@ -154,6 +155,8 @@ PcieInitEntry ( > DEBUG((EFI_D_ERROR, "HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port)); > } > > + InitAtu (&mResAppeture[HostBridgeNum][Port]); > + > } > } > > diff --git a/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c > new file mode 100644 > index 000000000000..9eb3451f7402 > --- /dev/null > +++ b/Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitAtu.c > @@ -0,0 +1,141 @@ > +/** @file > +* > +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. > +* Copyright (c) 2018, Linaro Limited. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include "PcieInit.h" > + > +STATIC > +UINT64 > +GetPcieCfgAddress ( > + UINT64 Ecam, > + UINTN Bus, > + UINTN Device, > + UINTN Function, > + UINTN Reg > + ) > +{ > + return Ecam + PCI_EXPRESS_LIB_ADDRESS (Bus, Device, Function, Reg); > +} > + > +STATIC > +VOID > +SetAtuConfig0RW ( > + PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Private, > + UINT32 Index > + ) > +{ > + UINTN RbPciBase = Private->RbPciBar; > + UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 1, 1, 0, 0) - 1; > + > + > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam)); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32)); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG0); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE); > + > + { > + UINTN i; > + for (i=0; i<0x20; i+=4) { > + DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i))); > + } > + } > +} > + > +void SetAtuConfig1RW ( > + PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Private, > + UINT32 Index > + ) > +{ > + UINTN RbPciBase = Private->RbPciBar; > + UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1; > + > + > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam)); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32)); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE); > + > + { > + UINTN i; > + for (i=0; i<0x20; i+=4) { > + DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i))); > + } > + } > +} > + > +void SetAtuIoRW(UINT64 RbPciBase,UINT64 IoBase,UINT64 CpuIoRegionLimit, UINT64 CpuIoRegionBase, UINT32 Index) > +{ > + > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_IO); > + > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuIoRegionBase)); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)CpuIoRegionBase >> 32)); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuIoRegionLimit)); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(IoBase)); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(IoBase) >> 32)); > + > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE); > + > + { > + UINTN i; > + for (i=0; i<0x20; i+=4) { > + DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i))); > + } > + } > +} > + > +void SetAtuMemRW(UINT64 RbPciBase,UINT64 MemBase,UINT64 CpuMemRegionLimit, UINT64 CpuMemRegionBase, UINT32 Index) > +{ > + > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_MEM); > + > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuMemRegionBase)); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(CpuMemRegionBase) >> 32)); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuMemRegionLimit)); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(MemBase)); > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(MemBase) >> 32)); > + > + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE); > + > + { > + UINTN i; > + for (i=0; i<0x20; i+=4) { > + DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i))); > + } > + } > +} > + > +VOID InitAtu (PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Private) > +{ > + SetAtuMemRW (Private->RbPciBar, Private->PciRegionBase, Private->PciRegionLimit, Private->CpuMemRegionBase, 0); > + SetAtuConfig0RW (Private, 1); > + SetAtuConfig1RW (Private, 2); > + SetAtuIoRW (Private->RbPciBar, Private->IoBase, Private->IoLimit, Private->CpuIoRegionBase, 3); > +} > + > -- > 2.7.4 >