From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::241; helo=mail-io0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x241.google.com (mail-io0-x241.google.com [IPv6:2607:f8b0:4001:c06::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D1F47222DE159 for ; Thu, 8 Feb 2018 11:41:06 -0800 (PST) Received: by mail-io0-x241.google.com with SMTP id m11so7040698iob.2 for ; Thu, 08 Feb 2018 11:46:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=PWPdmDgFnNWUEkpXk5tJ2qnuWR6wg2ace30hqn/+2Gc=; b=K6AzeFPjkVrSaphgHqDv1EawH52r7jd+KoDYxCTKAJjXohET1v4VH/O6HlD+V8D9SV QmtYMqmVkpDpmoD/42lAJm7iAW/koYj0j61SEaE7aBsTCdqlL4PHlekStFUZ5Rcj4hg+ g8lcsTGxB/KQrYgLyNpaZVLsGNLLcZquiCtCk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=PWPdmDgFnNWUEkpXk5tJ2qnuWR6wg2ace30hqn/+2Gc=; b=V6E4b4ikj71mKJUMMMpvaVrUD7HwJkVsMdpjDuXUA6cTcM7pI/OiTvJDROLxYcY+rv HeoQjD38o6kGDKLe5Lf2jfgokaSUs7LkgfM7y848u8lGSg/AtuL5FPFvnCHscR7EcRe9 +kdcqyzHoyNVklV2ZZcgT5XSuvXjtQ8RB872BLWRL/wdoEodO05oWRtX8Q7WKQ5j4DpG LuEvYOz1p2GpTn7IfTAMjdM6G7PWIV1bd+tL+LGGfaZfdx5wHriluWXTkAmNb0XlLot+ 8vla0YcA6iKxkUUCfhy6HRdVrvC1Rowym+7xnt3q/k5hh6TqFeYT02LFsV/LoU0NdyKv J4vQ== X-Gm-Message-State: APf1xPCTDM0PArzF6Zq9mrP6hIpFn1i4mcpAltRS4U16FETFfNrf9Fxp Sq2yw2s3BLb46cdv7T/gYsKPGDzWXiSPst4dZmZw9w== X-Google-Smtp-Source: AH8x224HbFi+xmQoU6QpO3LwGP7S/M+q52ikPzdRAmq+AYuCBVHlPmLaovGa7XYqmKdEBkyTjUB1dU+HhbKKN5fmIq0= X-Received: by 10.107.6.161 with SMTP id f33mr246167ioi.196.1518119210805; Thu, 08 Feb 2018 11:46:50 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.112.13 with HTTP; Thu, 8 Feb 2018 11:46:49 -0800 (PST) In-Reply-To: <20180208193021.24524-1-leif.lindholm@linaro.org> References: <20180208193021.24524-1-leif.lindholm@linaro.org> From: Ard Biesheuvel Date: Thu, 8 Feb 2018 19:46:49 +0000 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" Subject: Re: [PATCH edk2-platforms 1/3] Platform/(AMD|LeMaker|SoftIron), Silicon/AMD: drop unused PcdCacheEnabled X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Feb 2018 19:41:07 -0000 Content-Type: text/plain; charset="UTF-8" On 8 February 2018 at 19:30, Leif Lindholm wrote: > PcdCacheEnabled was never useful for these platforms, but they copied it > over from other platforms used as templates. > Delete it here to keep the platforms building once the Pcd is removed > from EmbeddedPkg. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Leif Lindholm For the series: Reviewed-by: Ard Biesheuvel > --- > Platform/AMD/OverdriveBoard/OverdriveBoard.dsc | 3 --- > Platform/LeMaker/CelloBoard/CelloBoard.dsc | 3 --- > Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc | 3 --- > Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf | 3 --- > Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf | 3 --- > Silicon/AMD/Styx/Library/AmdStyxLib/StyxMem.c | 6 +----- > 6 files changed, 1 insertion(+), 20 deletions(-) > > diff --git a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc > index 21edcc8798..48018abc69 100644 > --- a/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc > +++ b/Platform/AMD/OverdriveBoard/OverdriveBoard.dsc > @@ -282,9 +282,6 @@ [BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,Buil > ################################################################################ > > [PcdsFeatureFlag.common] > - # All pages are cached by default > - gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE > - > # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress > gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE > > diff --git a/Platform/LeMaker/CelloBoard/CelloBoard.dsc b/Platform/LeMaker/CelloBoard/CelloBoard.dsc > index cf3df86514..2468583c0d 100644 > --- a/Platform/LeMaker/CelloBoard/CelloBoard.dsc > +++ b/Platform/LeMaker/CelloBoard/CelloBoard.dsc > @@ -270,9 +270,6 @@ [BuildOptions.common.EDKII.DXE_DRIVER,BuildOptions.common.EDKII.UEFI_DRIVER,Buil > ################################################################################ > > [PcdsFeatureFlag.common] > - # All pages are cached by default > - gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE > - > # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress > gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE > > diff --git a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc > index 0abec8120a..f0a7e97941 100644 > --- a/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc > +++ b/Platform/SoftIron/Overdrive1000Board/Overdrive1000Board.dsc > @@ -272,9 +272,6 @@ [BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] > ################################################################################ > > [PcdsFeatureFlag.common] > - # All pages are cached by default > - gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE > - > # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress > gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE > > diff --git a/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf b/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf > index 6b7481ec6d..3a38f294eb 100644 > --- a/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf > +++ b/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLib.inf > @@ -53,9 +53,6 @@ [Guids] > [Ppis] > gArmMpCoreInfoPpiGuid > > -[FeaturePcd] > - gEmbeddedTokenSpaceGuid.PcdCacheEnable > - > [Pcd] > gArmTokenSpaceGuid.PcdSystemMemoryBase > gArmTokenSpaceGuid.PcdSystemMemorySize > diff --git a/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf b/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf > index b313d4baad..b24ffd469a 100644 > --- a/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf > +++ b/Silicon/AMD/Styx/Library/AmdStyxLib/AmdStyxLibSec.inf > @@ -49,9 +49,6 @@ [Sources.AARCH64] > [Guids] > gAmdStyxMpCoreInfoGuid ## CONSUMER > > -[FeaturePcd] > - gEmbeddedTokenSpaceGuid.PcdCacheEnable > - > [Ppis] > gArmMpCoreInfoPpiGuid > > diff --git a/Silicon/AMD/Styx/Library/AmdStyxLib/StyxMem.c b/Silicon/AMD/Styx/Library/AmdStyxLib/StyxMem.c > index 3b82132d08..479a40627d 100644 > --- a/Silicon/AMD/Styx/Library/AmdStyxLib/StyxMem.c > +++ b/Silicon/AMD/Styx/Library/AmdStyxLib/StyxMem.c > @@ -78,11 +78,7 @@ ArmPlatformGetVirtualMemoryMap ( > return; > } > > - if (FeaturePcdGet(PcdCacheEnable) == TRUE) { > - CacheAttributes = DDR_ATTRIBUTES_CACHED; > - } else { > - CacheAttributes = DDR_ATTRIBUTES_UNCACHED; > - } > + CacheAttributes = DDR_ATTRIBUTES_CACHED; > > DEBUG ((EFI_D_ERROR, " Memory Map\n------------------------------------------------------------------------\n")); > DEBUG ((EFI_D_ERROR, "Description : START - END [ SIZE ] { ATTR }\n")); > -- > 2.11.0 >