From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::242; helo=mail-io0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x242.google.com (mail-io0-x242.google.com [IPv6:2607:f8b0:4001:c06::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4C4F021E256B6 for ; Thu, 25 Jan 2018 05:00:04 -0800 (PST) Received: by mail-io0-x242.google.com with SMTP id m11so8572403iob.2 for ; Thu, 25 Jan 2018 05:05:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=Bl4Vkdk16pLVKcBxpeKZsSXZxGqVGCWGzMPal79JfZU=; b=V1Wy9GWU/hL+7vmmApXHPcOv0b4CAQ7D7VXcZzgALaxDuswBwkBEONs6v/6nnkT1hV hBV6eTZUDsgOat98WTNQvmqacv4Dm53Da2mMWS2df2Wz1RarK68PPSOE9XSLhyO+KHtD yoLAInOorNqqg6KwPHNAdFlDl6RNJPFjbenfs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=Bl4Vkdk16pLVKcBxpeKZsSXZxGqVGCWGzMPal79JfZU=; b=NicyfFoS7Nf76ZfykM7AcG23nSqLHC+ei6w1z456Uf+r4iEnG9dFV6604MltO7oOGV 1a3iF27M5Yneauk89dqIRwm0HrQ3wMn8Bm0k9/0qECBPQ+KrhqmCUOmLxzCCyLCKDTmE 7RzNDEcYPFuwJLNNwe22YdM2dDw+I0mBrKhsQW/b1XaZdaRSIBNCw1c1UJAVDxbDVRPA LZCtONr+ZSvzBPlmfCam+ZkVelTmwyXgsXftrQdpHgwKtICQ/AFvJsnHZwZg4cwcxHHW Ni0SDAvGiQ0ZzyB7GJp7LKDWWvHKvz+0BQFfBPALr1qhadYNESosMd1Ij4tGEmu9/Dnz AJ4A== X-Gm-Message-State: AKwxyteKGVZQlL+23X50YkzaxpsRseRt4dEcrfXXZ56VLrxUaa83WUkF DpjTbfC53FKbi91cxZGj6z9eL41BAMC1IIG2Lbad6A== X-Google-Smtp-Source: AH8x225VwIxsZpVN1Q0Ujo4CHcbvy2q839zhnWtFqE1CoY/3mrFhUSLZ2NxYj9tve5LeRYgikI7xZAlulpaZXy5jkj8= X-Received: by 10.107.25.195 with SMTP id 186mr12699469ioz.200.1516885533634; Thu, 25 Jan 2018 05:05:33 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.112.13 with HTTP; Thu, 25 Jan 2018 05:05:33 -0800 (PST) In-Reply-To: <20180125130030.lpfktprqzz3fpy7i@bivouac.eciton.net> References: <20180125122736.5427-1-ard.biesheuvel@linaro.org> <20180125122736.5427-8-ard.biesheuvel@linaro.org> <20180125130030.lpfktprqzz3fpy7i@bivouac.eciton.net> From: Ard Biesheuvel Date: Thu, 25 Jan 2018 13:05:33 +0000 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" Subject: Re: [PATCH edk2-platforms 7/8] Silicon/SynQuacer/DeviceTree: update NETSEC DT node to latest binding X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 25 Jan 2018 13:00:05 -0000 Content-Type: text/plain; charset="UTF-8" On 25 January 2018 at 13:00, Leif Lindholm wrote: > On Thu, Jan 25, 2018 at 12:27:35PM +0000, Ard Biesheuvel wrote: >> The upstream version of the Linux NETSEC driver expects the PHY DT >> node to appear under a MDIO subnode, so fix this in the device tree. >> Fix the node name as well, this should be 'ethernet' not 'netsec', >> and add a clock-names property describing the single clock reference >> as 'phy_ref_clk'. >> >> Also, move the PHY subnode into the per-platform .dts file so we can >> set the unit address in the node name. This is necessary because recent >> versions of the DT compiler are more finicky about this. > > Presumably the only kernels this may break are using non-upstream code? Yes. The upstream version is not quite upstream yet - it is now [finally] queued, for inclusion in v4.16 > If so: > Reviewed-by: Leif Lindholm > Thanks >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ard Biesheuvel >> --- >> Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts | 7 +++++ >> Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 30 +++++++++----------- >> Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts | 7 +++++ >> 3 files changed, 28 insertions(+), 16 deletions(-) >> >> diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts >> index d2cd7ef90e6f..488c51a0f793 100644 >> --- a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts >> +++ b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts >> @@ -44,3 +44,10 @@ >> "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27", >> "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31"; >> }; >> + >> +&mdio_netsec { >> + phy_netsec: ethernet-phy@7 { >> + compatible = "ethernet-phy-ieee802.3-c22"; >> + reg = <7>; >> + }; >> +}; >> diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi >> index 7c3518facb98..6ee7a0b7ccb4 100644 >> --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi >> +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi >> @@ -457,25 +457,23 @@ >> #clock-cells = <0>; >> }; >> >> - eth0: netsec@522D0000 { >> - compatible = "socionext,synquacer-netsec"; >> - reg = <0 0x522d0000 0x0 0x10000>, >> - <0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>; >> - interrupts = ; >> - clocks = <&clk_netsec>; >> - phy-mode = "rgmii"; >> - max-speed = <1000>; >> - max-frame-size = <9000>; >> - phy-handle = <ðphy0>; >> - dma-coherent; >> + ethernet@522d0000 { >> + compatible = "socionext,synquacer-netsec"; >> + reg = <0 0x522d0000 0x0 0x10000>, >> + <0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>; >> + interrupts = ; >> + clocks = <&clk_netsec>; >> + clock-names = "phy_ref_clk"; >> + phy-mode = "rgmii"; >> + max-speed = <1000>; >> + max-frame-size = <9000>; >> + phy-handle = <&phy_netsec>; >> + dma-coherent; >> >> + mdio_netsec: mdio { >> #address-cells = <1>; >> #size-cells = <0>; >> - >> - ethphy0: ethernet-phy { >> - compatible = "ethernet-phy-ieee802.3-c22"; >> - reg = ; >> - }; >> + }; >> }; >> >> smmu: iommu@582c0000 { >> diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts >> index 132fd370a71b..97fddfedcb46 100644 >> --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts >> +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts >> @@ -34,3 +34,10 @@ >> &sdhci { >> status = "okay"; >> }; >> + >> +&mdio_netsec { >> + phy_netsec: ethernet-phy@1 { >> + compatible = "ethernet-phy-ieee802.3-c22"; >> + reg = <1>; >> + }; >> +}; >> -- >> 2.11.0 >>