From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wr1-f66.google.com (mail-wr1-f66.google.com [209.85.221.66]) by mx.groups.io with SMTP id smtpd.web11.10618.1583404012665966959 for ; Thu, 05 Mar 2020 02:26:53 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=tUwjFm6i; spf=pass (domain: linaro.org, ip: 209.85.221.66, mailfrom: ard.biesheuvel@linaro.org) Received: by mail-wr1-f66.google.com with SMTP id h9so6283581wrr.10 for ; Thu, 05 Mar 2020 02:26:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=PumBFz/UOST4/KEhx8lFIrauKRrzjvPL756yX+cgp+8=; b=tUwjFm6ii1NJisKWOX+og9OLBENINLXixbpSaQbmTAxrbQSJ2ny4dRlzrSn6gKy5/z RdXul06h0nAuXh88/pzW892R70YsePZcz+BWBeyT0q1xJEotmdA0TRKhHlNjPdLx3DSw 0pKqboAxvHRiLaEo/RdBE9pQ3jGixwvWZEjnmL4Rr6dXurqOrH3bU7vdTzk5ts+I3/36 7IL8JqFWWgPF/tZ9jXYSPcbEG/JWX12DljPs43Ww1n93lo+3XIsVoU0LA6ENO+lnylav 6ynxCt3sa/OAe/JSxIdoV+gTYxQUOt+e1vZRqCSklPF7P7dZqFOCacblDEd0p6wRlErB j6Ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=PumBFz/UOST4/KEhx8lFIrauKRrzjvPL756yX+cgp+8=; b=l/8VB84bHXeqTYBoFx6r6AvoRvOEh38oT5iQmvpC2MgnruP+C3eon2ON9dT4DeCcWY qwPUFWv1oFLXYfKvK4Zmml+AnfSV0sasT+w8MAQEhI1nRybhNwKYFVGbEqIbUzi0AYzP FTLpzy4bAd/PXJgh84PnMSalWX+P41bjd31TO/kUV01UZz/raDNmrK+E/dPQHP5WmaSA lhq/AwnoWYzNJN0RUs7+P4tjoaRAHq5gTxTEbSPQChwNRn18ZkjtjHqOSbguJKaXsxLE wCC/yeqrMd63ewFMN2aFlhIJ8KGF5CUAZX2b0yDLZKrGQZhiGOzGbCyAWWl/xCpiy5Qg lEYw== X-Gm-Message-State: ANhLgQ2S3QfRDiK2rkG6xgHPmUiSwKSlvAl0r31Dm9/dyNMVcqY2M30o PzpVgDkHNvDkYKhMvcHuBpiNxBtxxYLmyPZntrYrzyRu2Us= X-Google-Smtp-Source: ADFU+vtIMZVPjitItXVOsFs5shb/ZVXTxoSTjSvanMdWebfnxvX34NS+BlL4VLaFGyNvKPt0J5+xU4821uPTaFK1Lb4= X-Received: by 2002:a05:6000:110b:: with SMTP id z11mr9630618wrw.252.1583404010758; Thu, 05 Mar 2020 02:26:50 -0800 (PST) MIME-Version: 1.0 References: <20200305100030.20048-1-ard.biesheuvel@linaro.org> <20200305100030.20048-3-ard.biesheuvel@linaro.org> In-Reply-To: <20200305100030.20048-3-ard.biesheuvel@linaro.org> From: "Ard Biesheuvel" Date: Thu, 5 Mar 2020 11:26:39 +0100 Message-ID: Subject: Re: [PATCH 2/2] ArmPkg/ArmMmuLib ARM: invalidate page tables as they are allocated To: edk2-devel-groups-io Cc: Leif Lindholm Content-Type: text/plain; charset="UTF-8" On Thu, 5 Mar 2020 at 11:00, Ard Biesheuvel wrote: > > Instead of performing two cache invalidations for each section entry > that gets updated, perform the first invalidation, which is intended > to clean the page tables from caches on systems where cache hits are > permitted with the MMU and caches off. > ... as the page tables are allocated. > Signed-off-by: Ard Biesheuvel > --- > ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 33 +++++++++++--------- > 1 file changed, 18 insertions(+), 15 deletions(-) > > diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c > index 0800ef560d89..11a1e704beab 100644 > --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c > +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c > @@ -147,6 +147,13 @@ PopulateLevel2PageTable ( > > BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(*SectionEntry); > > + // > + // Make sure we are not inadvertently hitting in the caches > + // when populating the page tables > + // > + InvalidateDataCacheRange ((VOID *)TranslationTable, > + TRANSLATION_TABLE_PAGE_SIZE); > + > // Populate the new Level2 Page Table for the section > PageEntry = (UINT32*)TranslationTable; > for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) { > @@ -166,6 +173,12 @@ PopulateLevel2PageTable ( > TranslationTable = (UINTN)AllocateAlignedPages ( > EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_PAGE_SIZE), > TRANSLATION_TABLE_PAGE_ALIGNMENT); > + // > + // Make sure we are not inadvertently hitting in the caches > + // when populating the page tables > + // > + InvalidateDataCacheRange ((VOID *)TranslationTable, > + TRANSLATION_TABLE_PAGE_SIZE); > ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_PAGE_SIZE); > > *SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | > @@ -179,13 +192,6 @@ PopulateLevel2PageTable ( > > ASSERT (FirstPageOffset + Pages <= TRANSLATION_TABLE_PAGE_COUNT); > > - // > - // Invalidate once to prevent page table updates to hit in the > - // caches inadvertently. > - // > - InvalidateDataCacheRange ((UINT32 *)TranslationTable + FirstPageOffset, > - RemainLength / TT_DESCRIPTOR_PAGE_SIZE * sizeof (*PageEntry)); > - > for (Index = 0; Index < Pages; Index++) { > *PageEntry++ = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(PhysicalBase) | PageAttributes; > PhysicalBase += TT_DESCRIPTOR_PAGE_SIZE; > @@ -268,14 +274,6 @@ FillTranslationTable ( > SectionEntry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase); > > while (RemainLength != 0) { > - // > - // Ensure that the assignment of the page table entry will not hit > - // in the cache. Whether this could occur is IMPLEMENTATION DEFINED > - // and thus permitted by the ARMv7 architecture. > - // > - ArmInvalidateDataCacheEntryByMVA ((UINTN)SectionEntry); > - ArmDataSynchronizationBarrier (); > - > if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0 && > RemainLength >= TT_DESCRIPTOR_SECTION_SIZE) { > // Case: Physical address aligned on the Section Size (1MB) && the length > @@ -348,6 +346,11 @@ ArmConfigureMmu ( > *TranslationTableSize = TRANSLATION_TABLE_SECTION_SIZE; > } > > + // > + // Make sure we are not inadvertently hitting in the caches > + // when populating the page tables > + // > + InvalidateDataCacheRange (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE); > ZeroMem (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE); > > // By default, mark the translation table as belonging to a uncached region > -- > 2.17.1 >