From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::242; helo=mail-it0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x242.google.com (mail-it0-x242.google.com [IPv6:2607:f8b0:4001:c0b::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 790ED210D7F38 for ; Thu, 2 Aug 2018 11:24:01 -0700 (PDT) Received: by mail-it0-x242.google.com with SMTP id g141-v6so4795051ita.4 for ; Thu, 02 Aug 2018 11:24:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=Rgz7ba/RCu4MMI9rnrDdRAkKaox2NRIL5aRnmvZC2Vs=; b=PAsBY5j6dW7lo3BoZujHdZkt384oSqrAUa02lOVDtGgUYIDz33kea45vXVpLCLirDb 16oc0vyiPrS9J5dsOtT9vx1lQE86Xoa9+BaJuG9Rzdo6ujzC57Oi7XRGWdgA/3Cnd7Gd LSZCuyjXqkgabuDngLgNvyX1oqUAfSDGvrGPo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=Rgz7ba/RCu4MMI9rnrDdRAkKaox2NRIL5aRnmvZC2Vs=; b=VgZ4A3eCJsMPmeyBfKCgadCBJjGVYsjExwT16fB0M49zvYSmrrDwUD95ChLKhg7kuf +UIuO+BMYdNncijUDeZPMsdx4XS9r8pAioUHtvSQPehbm6ahEprUShI8Wl6m6EPYnKvy CuoGK2kfwdAnS3qZ7ihCgPpgRQMbhKPjLXkxEr0N2PsIQ5ljtPu5kvcaVP1wsfVeNlYT uJ0TnpQm/vfK++GXQLoABltMN+f1jqlSSpvOMw9PSOlRY4RR6zAetsKDxJWuSmFFX9zb 35g6l0k/T5SUCWLC9dvKxTN/YSFTWNYH4y63ox4O/v6KR2hfZPe1/SCNV2vU3e+Myq7L JVkg== X-Gm-Message-State: AOUpUlFdNDUmHyBT2YYaF3DUbtDo/HlChUMd5IfQMJCfPZMfkEIGfSdQ pI+0jXRBaYzYQpdjgR8hFWu06OFoQ1RwTXyx/iBfBw== X-Google-Smtp-Source: AAOMgpdQh1StpQYJ6fMUQU14JFmbXSdyahy26iu9brrTC0BLpFp4ZQchueCXBSb+82d7qfhoJ4+yNeeDM2PBW7iI36o= X-Received: by 2002:a24:610d:: with SMTP id s13-v6mr3749370itc.68.1533234240636; Thu, 02 Aug 2018 11:24:00 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a6b:ac05:0:0:0:0:0 with HTTP; Thu, 2 Aug 2018 11:24:00 -0700 (PDT) In-Reply-To: <20180802181324.yyvq3ihu47tvku2a@bivouac.eciton.net> References: <20180724070922.63362-1-ming.huang@linaro.org> <20180724070922.63362-11-ming.huang@linaro.org> <20180802181324.yyvq3ihu47tvku2a@bivouac.eciton.net> From: Ard Biesheuvel Date: Thu, 2 Aug 2018 20:24:00 +0200 Message-ID: To: Leif Lindholm Cc: Ming Huang , linaro-uefi , "edk2-devel@lists.01.org" , Graeme Gregory , guoheyi@huawei.com, wanghuiqiang , huangming , Jason Zhang , huangdaode@hisilicon.com, John Garry , Xinliang Liu , Yan Zhang , Heyi Guo Subject: Re: [PATCH edk2-platforms v1 10/38] Hisilicon/D06: Add ACPI Tables for D06 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Aug 2018 18:24:01 -0000 Content-Type: text/plain; charset="UTF-8" On 2 August 2018 at 20:13, Leif Lindholm wrote: > Graeme, Ard, do either of you have the stamina to go through all this, > or will wi settle for testing it? > Well, without a SoC manual, it is rather difficult to review this in great detail. I did give it a quick skim, and the only thing that looked peculiar to me is that all PCI root complexes use IRQs 640-643 for the legacy INTx interrupts for all slots. Also, there's a cacheline size value of 32 bytes somewhere. In summary, the code does not look wrong per se, but it does not necessarily look like it was put together with great diligence.