From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=tDpOGuJU; spf=pass (domain: linaro.org, ip: 209.85.221.67, mailfrom: ard.biesheuvel@linaro.org) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by groups.io with SMTP; Thu, 19 Sep 2019 03:01:33 -0700 Received: by mail-wr1-f67.google.com with SMTP id l3so2406999wru.7 for ; Thu, 19 Sep 2019 03:01:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Ln6ItgQkytqD6FNdqrgrucl07jn/m44xQv6f9tPj+oA=; b=tDpOGuJUhZ35/Tap0EYQzzjd71upGYpPdf3VStSky1BQ+PzpWYcHt/0xlUbMp+rzjp OaFo79cfqngDEXPKvq7GZt019rOaJmFZi5bWkmnTN4E1ro7fLXHax73Kthn9rBkdPXtb DNucB8n8QhfXOkqMV5HJsfWyfiocgYOFnlMEFgdm/8uVSrpqegcPorr7z7hb/Pbz4DMm rcHfAj94mljjlEAYW5EUIcKG7mu3omX0rri4CwyHjUapEfXnWu3/LXuYw6Wkb4dclbzf mRkwhuGA8uC8GvA0SBJ5KEhTW9KMK8PWMq1DwaQsK7pI1cpBpYC5/Ri6GPKDGKZvJI7u utUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Ln6ItgQkytqD6FNdqrgrucl07jn/m44xQv6f9tPj+oA=; b=Jy6+N99BYG0DWkkHVaBmu3hESsjHA0wLt9QbbCnAG8alutEAH9+P7iwqSywF6O4496 yKO0GjIN1kcK7LZLFvJjQTy/opEZjgVoCGdDPaLM9FSXZWeQqGbqGx4bMQ7PYB61Ez4h eZOUuAKeqyb2Vem/AzFBinNNycBm4KHWaBvE8TFgotfX01YymXgkQb41nybZlLmGvUbN rSAStMoRQAtAUbac4JLgmzdn4fe7UFF5L8LmUYdufOtZuM4EdrtWEV0uicHAqYp1cYnW lOexGVnNvmZcXSsM5mOjfUetdVDXJfUt3vd8XUo3NR/GWFYKeJO7n0Ul7cnB71CNNKlj Carg== X-Gm-Message-State: APjAAAWLMOLJ0wdyKMGtv7Stt6g4xsFqusHhIl5FcHTMh47KECE1SGdF WSj4JqnlvzU4PnbebPeVqOszO12AKc7PmHOFWeugPA== X-Google-Smtp-Source: APXvYqwn5XeT6yTfyoQF7i6Cnfuz+H0lHunuy5Yb63nZU62C1fVA2pPE/vvXqXMKvnh2oa0zk8oIGthCooRiicFSCec= X-Received: by 2002:a5d:638f:: with SMTP id p15mr6479927wru.169.1568887291794; Thu, 19 Sep 2019 03:01:31 -0700 (PDT) MIME-Version: 1.0 References: <0d024d72b50b7f5a6d3d908d309810f350c5b1f5.1568808805.git.baptiste.gerondeau@linaro.org> <20190919094846.GO28454@bivouac.eciton.net> In-Reply-To: <20190919094846.GO28454@bivouac.eciton.net> From: "Ard Biesheuvel" Date: Thu, 19 Sep 2019 13:01:04 +0300 Message-ID: Subject: Re: [PATCH 2/3] ARM/Assembler: Correct syntax from RVCT for MSFT To: Leif Lindholm Cc: Baptiste Gerondeau , edk2-devel-groups-io , "Kinney, Michael D" , "Gao, Liming" , "Zhang, Shenglei" , Baptiste GERONDEAU Content-Type: text/plain; charset="UTF-8" On Thu, 19 Sep 2019 at 12:48, Leif Lindholm wrote: > > On Thu, Sep 19, 2019 at 12:32:56PM +0300, Ard Biesheuvel wrote: > > On Wed, 18 Sep 2019 at 15:27, Baptiste Gerondeau > > wrote: > > > > > > From: Baptiste GERONDEAU > > > > > > RVCT and MSFT's ARM assembler share the same file syntax, but some > > > instructions use pre-UAL syntax that is not picked up > > > by MSFT's ARM assembler, this commit translates those instructions > > > into MSFT-buildable ones (subset of UAL/THUMB). > > > > > > Signed-off-by: Baptiste Gerondeau > > > --- > > > ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm | 30 +++++++++++++++++------------- > > > ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm | 6 ++++-- > > > MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm | 18 +++++++++--------- > > > 3 files changed, 30 insertions(+), 24 deletions(-) > > > > > > diff --git a/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm b/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm > > > index aa0229d2e85f..880246bd6206 100644 > > > --- a/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm > > > +++ b/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm > > > @@ -90,7 +90,7 @@ Fiq > > > ResetEntry > > > srsfd #0x13! ; Store return state on SVC stack > > > ; We are already in SVC mode > > > - stmfd SP!,{LR} ; Store the link register for the current mode > > > + push {LR} ; Store the link register for the current mode > > > sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR > > > stmfd SP!,{R0-R12} ; Store the register state > > > > > > @@ -102,7 +102,7 @@ UndefinedInstructionEntry > > > sub LR, LR, #4 ; Only -2 for Thumb, adjust in CommonExceptionEntry > > > srsfd #0x13! ; Store return state on SVC stack > > > cps #0x13 ; Switch to SVC for common stack > > > - stmfd SP!,{LR} ; Store the link register for the current mode > > > + push {LR} ; Store the link register for the current mode > > > sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR > > > stmfd SP!,{R0-R12} ; Store the register state > > > > > > @@ -113,7 +113,7 @@ UndefinedInstructionEntry > > > SoftwareInterruptEntry > > > srsfd #0x13! ; Store return state on SVC stack > > > ; We are already in SVC mode > > > - stmfd SP!,{LR} ; Store the link register for the current mode > > > + push {LR} ; Store the link register for the current mode > > > sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR > > > stmfd SP!,{R0-R12} ; Store the register state > > > > > > @@ -125,7 +125,7 @@ PrefetchAbortEntry > > > sub LR,LR,#4 > > > srsfd #0x13! ; Store return state on SVC stack > > > cps #0x13 ; Switch to SVC for common stack > > > - stmfd SP!,{LR} ; Store the link register for the current mode > > > + push {LR} ; Store the link register for the current mode > > > sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR > > > stmfd SP!,{R0-R12} ; Store the register state > > > > > > @@ -137,7 +137,7 @@ DataAbortEntry > > > sub LR,LR,#8 > > > srsfd #0x13! ; Store return state on SVC stack > > > cps #0x13 ; Switch to SVC for common stack > > > - stmfd SP!,{LR} ; Store the link register for the current mode > > > + push {LR} ; Store the link register for the current mode > > > sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR > > > stmfd SP!,{R0-R12} ; Store the register state > > > > > > @@ -148,7 +148,7 @@ DataAbortEntry > > > ReservedExceptionEntry > > > srsfd #0x13! ; Store return state on SVC stack > > > cps #0x13 ; Switch to SVC for common stack > > > - stmfd SP!,{LR} ; Store the link register for the current mode > > > + push {LR} ; Store the link register for the current mode > > > sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR > > > stmfd SP!,{R0-R12} ; Store the register state > > > > > > @@ -160,7 +160,7 @@ IrqEntry > > > sub LR,LR,#4 > > > srsfd #0x13! ; Store return state on SVC stack > > > cps #0x13 ; Switch to SVC for common stack > > > - stmfd SP!,{LR} ; Store the link register for the current mode > > > + push {LR} ; Store the link register for the current mode > > > sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR > > > stmfd SP!,{R0-R12} ; Store the register state > > > > > > @@ -172,7 +172,7 @@ FiqEntry > > > sub LR,LR,#4 > > > srsfd #0x13! ; Store return state on SVC stack > > > cps #0x13 ; Switch to SVC for common stack > > > - stmfd SP!,{LR} ; Store the link register for the current mode > > > + push {LR} ; Store the link register for the current mode > > > sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - CPSR > > > stmfd SP!,{R0-R12} ; Store the register state > > > ; Since we have already switch to SVC R8_fiq - R12_fiq > > > @@ -213,9 +213,11 @@ AsmCommonExceptionEntry > > > and R3, R1, #0x1f ; Check CPSR to see if User or System Mode > > > cmp R3, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1f)) > > > cmpne R3, #0x10 ; > > > - stmeqed R2, {lr}^ ; save unbanked lr > > > + mrseq R8, lr_usr ; save unbanked lr to R8 > > > + streq R2, [R8] ; make R2 point to R8 > > > ; else > > > - stmneed R2, {lr} ; save SVC lr > > > + mrsne R8, lr_svc ; save SVC lr to R8 > > > + strne R2, [R8] ; make R2 point to R8 > > > > > > > Can you make this str unconditional, and drop the former? > > Yeah, that would be an improvement. > > > > > > > ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd > > > @@ -280,15 +282,17 @@ CommonCExceptionHandler ( > > > and R1, R1, #0x1f ; Check to see if User or System Mode > > > cmp R1, #0x1f ; if ((CPSR == 0x10) || (CPSR == 0x1f)) > > > cmpne R1, #0x10 ; > > > - ldmeqed R2, {lr}^ ; restore unbanked lr > > > + ldreq R8, [R2] ; load sys/usr lr from R2 pointer > > > + msreq lr_usr, R8 ; restore unbanked lr > > > ; else > > > - ldmneed R3, {lr} ; restore SVC lr, via ldmfd SP!, {LR} > > > + ldrne R8, [R3] ; load SVC lr from R3 pointer > > > + msrne lr_svc, R8 ; restore SVC lr, via ldmfd SP!, {LR} > > > > > > ldmfd SP!,{R0-R12} ; Restore general purpose registers > > > ; Exception handler can not change SP > > > > > > add SP,SP,#0x20 ; Clear out the remaining stack space > > > - ldmfd SP!,{LR} ; restore the link register for this context > > > + pop {LR} ; restore the link register for this context > > > rfefd SP! ; return from exception via srsfd stack slot > > > > > > END > > > diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm b/ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm > > > index 3146c2b52181..724306399e6c 100644 > > > --- a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm > > > +++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm > > > @@ -200,8 +200,10 @@ Loop2 > > > mov R9, R4 ; R9 working copy of the max way size (right aligned) > > > > > > Loop3 > > > - orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11 > > > - orr R0, R0, R7, LSL R2 ; factor in the index number > > > + lsl R8, R9, R5 > > > + orr R0, R10, R8 ; factor in the way number and cache number > > > + lsl R8, R7, R2 > > > + orr R0, R0, R8 ; factor in the index number > > > > > > > What's wrong with this code? > > Inline barrel shifter is only available in A32, not T32 (and VS seems > to love T32). > So is this simply the default of the compiler? I'd prefer it if we could add a 'CODE 32' directive instead, that way, we may not need any of the other changes to begin with.