* [PATCH v2 0/4] SdMmcOverride extension
@ 2018-10-05 13:25 Marcin Wojtas
2018-10-05 13:25 ` [PATCH v2 1/4] MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in NotifyPhase Marcin Wojtas
` (5 more replies)
0 siblings, 6 replies; 47+ messages in thread
From: Marcin Wojtas @ 2018-10-05 13:25 UTC (permalink / raw)
To: edk2-devel
Cc: feng.tian, michael.d.kinney, liming.gao, leif.lindholm, hao.a.wu,
ard.biesheuvel, nadavh, mw, jsd, tm
Hi,
This is the second version of the patchset. Initial one was
interleaved with the fixes, which after split got already merged.
The biggest change is - resigning from the new callbacks
and extending parameter lists of both NotifyPhase and Capability
routines.
Patches are available in the github:
https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/sdmmc-override-upstream-r20181005
Please note that extending SdMmcOverride protocol was impacting
so far the only user of it (Synquacer controller). In paralel
edk2-platforms patchset, a patch can be found:
("Silicon/SynQuacer/PlatformDxe: adjust to updated SdMmcOverride")
which immunizes for above and future extensions of the protocol:
https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/xenon-upstream-r20181005
I'm looking forward to the comments and remarks.
Best regards,
Marcin
Changelog:
v1 -> v2
* Rebase onto newest master
* 1/4 [new patch] - preparation for extending NotifyPhase
* 2/4 - UhsSignaling as a part of NotifyPhase
* 3/4 - SwitchClockFreqPost as a part of NotifyPhase
* 4/4 - Allow updating BaseClkFreq via Capability instead of the
independent callback.
Marcin Wojtas (2):
MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in NotifyPhase
MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequency
Tomasz Michalec (2):
MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to SdMmcOverride
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 6 +
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 62 +++++-
MdeModulePkg/Include/Protocol/SdMmcOverride.h | 12 +-
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 215 ++++++++++++++------
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 57 +++++-
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 18 +-
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 108 ++++++++--
7 files changed, 383 insertions(+), 95 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 47+ messages in thread
* [PATCH v2 1/4] MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in NotifyPhase
2018-10-05 13:25 [PATCH v2 0/4] SdMmcOverride extension Marcin Wojtas
@ 2018-10-05 13:25 ` Marcin Wojtas
2018-10-08 12:21 ` Ard Biesheuvel
2018-10-05 13:25 ` [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol Marcin Wojtas
` (4 subsequent siblings)
5 siblings, 1 reply; 47+ messages in thread
From: Marcin Wojtas @ 2018-10-05 13:25 UTC (permalink / raw)
To: edk2-devel
Cc: feng.tian, michael.d.kinney, liming.gao, leif.lindholm, hao.a.wu,
ard.biesheuvel, nadavh, mw, jsd, tm
In order to ensure bigger flexibility in the NotifyPhase
routine of the SdMmcOverride protocol, enable using an
optional phase-specific data. This will allow to exchange
more information between the protocol producer driver
and SdMmcPciHcDxe in the newly added callbacks.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
MdeModulePkg/Include/Protocol/SdMmcOverride.h | 4 +++-
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 12 ++++++++----
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
index 0766252..178945f 100644
--- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
+++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
@@ -63,6 +63,7 @@ EFI_STATUS
@param[in] PhaseType The type of operation and whether the
hook is invoked right before (pre) or
right after (post)
+ @param[in,out] Data The pointer to a phase-specific data.
@retval EFI_SUCCESS The override function completed successfully.
@retval EFI_NOT_FOUND The specified controller or slot does not exist.
@@ -74,7 +75,8 @@ EFI_STATUS
(EFIAPI * EDKII_SD_MMC_NOTIFY_PHASE) (
IN EFI_HANDLE ControllerHandle,
IN UINT8 Slot,
- IN EDKII_SD_MMC_PHASE_TYPE PhaseType
+ IN EDKII_SD_MMC_PHASE_TYPE PhaseType,
+ IN OUT VOID *OptParam
);
struct _EDKII_SD_MMC_OVERRIDE {
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index 25771dc..02eb4ad 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -444,7 +444,8 @@ SdMmcHcReset (
Status = mOverride->NotifyPhase (
Private->ControllerHandle,
Slot,
- EdkiiSdMmcResetPre);
+ EdkiiSdMmcResetPre,
+ NULL);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN,
"%a: SD/MMC pre reset notifier callback failed - %r\n",
@@ -494,7 +495,8 @@ SdMmcHcReset (
Status = mOverride->NotifyPhase (
Private->ControllerHandle,
Slot,
- EdkiiSdMmcResetPost);
+ EdkiiSdMmcResetPost,
+ NULL);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN,
"%a: SD/MMC post reset notifier callback failed - %r\n",
@@ -1087,7 +1089,8 @@ SdMmcHcInitHost (
Status = mOverride->NotifyPhase (
Private->ControllerHandle,
Slot,
- EdkiiSdMmcInitHostPre);
+ EdkiiSdMmcInitHostPre,
+ NULL);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN,
"%a: SD/MMC pre init notifier callback failed - %r\n",
@@ -1122,7 +1125,8 @@ SdMmcHcInitHost (
Status = mOverride->NotifyPhase (
Private->ControllerHandle,
Slot,
- EdkiiSdMmcInitHostPost);
+ EdkiiSdMmcInitHostPost,
+ NULL);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN,
"%a: SD/MMC post init notifier callback failed - %r\n",
--
2.7.4
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-05 13:25 [PATCH v2 0/4] SdMmcOverride extension Marcin Wojtas
2018-10-05 13:25 ` [PATCH v2 1/4] MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in NotifyPhase Marcin Wojtas
@ 2018-10-05 13:25 ` Marcin Wojtas
2018-10-05 15:12 ` Philippe Mathieu-Daudé
` (2 more replies)
2018-10-05 13:25 ` [PATCH v2 3/4] MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to SdMmcOverride Marcin Wojtas
` (3 subsequent siblings)
5 siblings, 3 replies; 47+ messages in thread
From: Marcin Wojtas @ 2018-10-05 13:25 UTC (permalink / raw)
To: edk2-devel
Cc: feng.tian, michael.d.kinney, liming.gao, leif.lindholm, hao.a.wu,
ard.biesheuvel, nadavh, mw, jsd, tm
From: Tomasz Michalec <tm@semihalf.com>
Some SD Host Controlers use different values in Host Control 2 Register
to select UHS Mode. This patch adds a new UhsSignaling type routine to
the NotifyPhase of the SdMmcOverride protocol.
UHS signaling configuration is moved to a common, default routine
(SdMmcHcUhsSignaling), which is called when SdMmcOverride does not
cover this functionality.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 50 +++++++
MdeModulePkg/Include/Protocol/SdMmcOverride.h | 2 +
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 153 ++++++++++++--------
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 37 +++--
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 69 +++++++++
5 files changed, 243 insertions(+), 68 deletions(-)
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
index e389d52..a03160d 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
@@ -63,6 +63,39 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define SD_MMC_HC_CTRL_VER 0xFE
//
+// SD Host Controler bits to HOST_CTRL2 register
+//
+#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
+#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
+#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
+#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
+#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
+#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
+#define SD_MMC_HC_CTRL_MMC_DDR52 0x0004
+#define SD_MMC_HC_CTRL_MMC_SDR50 0x0002
+#define SD_MMC_HC_CTRL_MMC_SDR25 0x0001
+#define SD_MMC_HC_CTRL_MMC_SDR12 0x0000
+#define SD_MMC_HC_CTRL_HS200 0x0003
+#define SD_MMC_HC_CTRL_HS400 0x0005
+
+//
+// Timing modes for uhs
+//
+typedef enum {
+ SdMmcUhsSdr12,
+ SdMmcUhsSdr25,
+ SdMmcUhsSdr50,
+ SdMmcUhsSdr104,
+ SdMmcUhsDdr50,
+ SdMmcMmcDdr52,
+ SdMmcMmcSdr50,
+ SdMmcMmcSdr25,
+ SdMmcMmcSdr12,
+ SdMmcMmcHs200,
+ SdMmcMmcHs400,
+} SD_MMC_UHS_TIMING;
+
+//
// The transfer modes supported by SD Host Controller
// Simplified Spec 3.0 Table 1-2
//
@@ -508,4 +541,21 @@ SdMmcHcInitTimeoutCtrl (
IN UINT8 Slot
);
+/**
+ Set SD Host Controler control 2 registry according to selected speed.
+
+ @param[in] PciIo The PCI IO protocol instance.
+ @param[in] Slot The slot number of the SD card to send the command to.
+ @param[in] Timing The timing to select.
+
+ @retval EFI_SUCCESS The timing is set successfully.
+ @retval Others The timing isn't set successfully.
+**/
+EFI_STATUS
+SdMmcHcUhsSignaling (
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Slot,
+ IN SD_MMC_UHS_TIMING Timing
+ );
+
#endif
diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
index 178945f..25db98a 100644
--- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
+++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
@@ -17,6 +17,7 @@
#ifndef __SD_MMC_OVERRIDE_H__
#define __SD_MMC_OVERRIDE_H__
+#include <Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h>
#include <Protocol/SdMmcPassThru.h>
#define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \
@@ -31,6 +32,7 @@ typedef enum {
EdkiiSdMmcResetPost,
EdkiiSdMmcInitHostPre,
EdkiiSdMmcInitHostPost,
+ EdkiiSdMmcUhsSignaling,
} EDKII_SD_MMC_PHASE_TYPE;
/**
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
index c5fd214..05bd4a0 100755
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
@@ -740,10 +740,13 @@ EmmcSwitchToHighSpeed (
IN UINT8 BusWidth
)
{
- EFI_STATUS Status;
- UINT8 HsTiming;
- UINT8 HostCtrl1;
- UINT8 HostCtrl2;
+ EFI_STATUS Status;
+ UINT8 HsTiming;
+ UINT8 HostCtrl1;
+ SD_MMC_UHS_TIMING Timing;
+ SD_MMC_HC_PRIVATE_DATA *Private;
+
+ Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusWidth);
if (EFI_ERROR (Status)) {
@@ -758,27 +761,37 @@ EmmcSwitchToHighSpeed (
return Status;
}
- //
- // Clean UHS Mode Select field of Host Control 2 reigster before update
- //
- HostCtrl2 = (UINT8)~0x7;
- Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
- if (EFI_ERROR (Status)) {
- return Status;
- }
- //
- // Set UHS Mode Select field of Host Control 2 reigster to SDR12/25/50
- //
if (IsDdr) {
- HostCtrl2 = BIT2;
+ Timing = SdMmcMmcDdr52;
} else if (ClockFreq == 52) {
- HostCtrl2 = BIT0;
+ Timing = SdMmcMmcSdr50;
+ } else if (ClockFreq == 26) {
+ Timing = SdMmcMmcSdr25;
} else {
- HostCtrl2 = 0;
+ Timing = SdMmcMmcSdr12;
}
- Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
- if (EFI_ERROR (Status)) {
- return Status;
+
+ if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
+ Status = mOverride->NotifyPhase (
+ Private->ControllerHandle,
+ Slot,
+ EdkiiSdMmcUhsSignaling,
+ &Timing
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
+ __FUNCTION__,
+ Status
+ ));
+ return Status;
+ }
+ } else {
+ Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
}
HsTiming = 1;
@@ -814,10 +827,13 @@ EmmcSwitchToHS200 (
IN UINT8 BusWidth
)
{
- EFI_STATUS Status;
- UINT8 HsTiming;
- UINT8 HostCtrl2;
- UINT16 ClockCtrl;
+ EFI_STATUS Status;
+ UINT8 HsTiming;
+ UINT16 ClockCtrl;
+ SD_MMC_UHS_TIMING Timing;
+ SD_MMC_HC_PRIVATE_DATA *Private;
+
+ Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
if ((BusWidth != 4) && (BusWidth != 8)) {
return EFI_INVALID_PARAMETER;
@@ -837,21 +853,30 @@ EmmcSwitchToHS200 (
if (EFI_ERROR (Status)) {
return Status;
}
- //
- // Clean UHS Mode Select field of Host Control 2 reigster before update
- //
- HostCtrl2 = (UINT8)~0x7;
- Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
- if (EFI_ERROR (Status)) {
- return Status;
- }
- //
- // Set UHS Mode Select field of Host Control 2 reigster to SDR104
- //
- HostCtrl2 = BIT0 | BIT1;
- Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
- if (EFI_ERROR (Status)) {
- return Status;
+
+ Timing = SdMmcMmcHs200;
+
+ if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
+ Status = mOverride->NotifyPhase (
+ Private->ControllerHandle,
+ Slot,
+ EdkiiSdMmcUhsSignaling,
+ &Timing
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
+ __FUNCTION__,
+ Status
+ ));
+ return Status;
+ }
+ } else {
+ Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
}
//
// Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit
@@ -910,9 +935,12 @@ EmmcSwitchToHS400 (
IN UINT32 ClockFreq
)
{
- EFI_STATUS Status;
- UINT8 HsTiming;
- UINT8 HostCtrl2;
+ EFI_STATUS Status;
+ UINT8 HsTiming;
+ SD_MMC_UHS_TIMING Timing;
+ SD_MMC_HC_PRIVATE_DATA *Private;
+
+ Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, ClockFreq, 8);
if (EFI_ERROR (Status)) {
@@ -933,21 +961,30 @@ EmmcSwitchToHS400 (
if (EFI_ERROR (Status)) {
return Status;
}
- //
- // Clean UHS Mode Select field of Host Control 2 reigster before update
- //
- HostCtrl2 = (UINT8)~0x7;
- Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
- if (EFI_ERROR (Status)) {
- return Status;
- }
- //
- // Set UHS Mode Select field of Host Control 2 reigster to HS400
- //
- HostCtrl2 = BIT0 | BIT2;
- Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
- if (EFI_ERROR (Status)) {
- return Status;
+
+ Timing = SdMmcMmcHs400;
+
+ if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
+ Status = mOverride->NotifyPhase (
+ Private->ControllerHandle,
+ Slot,
+ EdkiiSdMmcUhsSignaling,
+ &Timing
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
+ __FUNCTION__,
+ Status
+ ));
+ return Status;
+ }
+ } else {
+ Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
}
HsTiming = 3;
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
index 8c93933..5645a71 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
@@ -784,8 +784,8 @@ SdCardSetBusMode (
UINT8 BusWidth;
UINT8 AccessMode;
UINT8 HostCtrl1;
- UINT8 HostCtrl2;
UINT8 SwitchResp[64];
+ SD_MMC_UHS_TIMING Timing;
SD_MMC_HC_PRIVATE_DATA *Private;
Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
@@ -817,18 +817,23 @@ SdCardSetBusMode (
if (S18A && (Capability->Sdr104 != 0) && ((SwitchResp[13] & BIT3) != 0)) {
ClockFreq = 208;
AccessMode = 3;
+ Timing = SdMmcUhsSdr104;
} else if (S18A && (Capability->Sdr50 != 0) && ((SwitchResp[13] & BIT2) != 0)) {
ClockFreq = 100;
AccessMode = 2;
+ Timing = SdMmcUhsSdr50;
} else if (S18A && (Capability->Ddr50 != 0) && ((SwitchResp[13] & BIT4) != 0)) {
ClockFreq = 50;
AccessMode = 4;
+ Timing = SdMmcUhsDdr50;
} else if ((SwitchResp[13] & BIT1) != 0) {
ClockFreq = 50;
AccessMode = 1;
+ Timing = SdMmcUhsSdr25;
} else {
ClockFreq = 25;
AccessMode = 0;
+ Timing = SdMmcUhsSdr12;
}
Status = SdCardSwitch (PassThru, Slot, AccessMode, 0xF, 0xF, 0xF, TRUE, SwitchResp);
@@ -854,15 +859,27 @@ SdCardSetBusMode (
}
}
- HostCtrl2 = (UINT8)~0x7;
- Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
- if (EFI_ERROR (Status)) {
- return Status;
- }
- HostCtrl2 = AccessMode;
- Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
- if (EFI_ERROR (Status)) {
- return Status;
+ if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
+ Status = mOverride->NotifyPhase (
+ Private->ControllerHandle,
+ Slot,
+ EdkiiSdMmcUhsSignaling,
+ &Timing
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
+ __FUNCTION__,
+ Status
+ ));
+ return Status;
+ }
+ } else {
+ Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
}
Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capability);
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index 02eb4ad..38d6202 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -1137,6 +1137,75 @@ SdMmcHcInitHost (
}
/**
+ Set SD Host Controler control 2 registry according to selected speed.
+
+ @param[in] PciIo The PCI IO protocol instance.
+ @param[in] Slot The slot number of the SD card to send the command to.
+ @param[in] Timing The timing to select.
+
+ @retval EFI_SUCCESS The timing is set successfully.
+ @retval Others The timing isn't set successfully.
+**/
+EFI_STATUS
+SdMmcHcUhsSignaling (
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ IN UINT8 Slot,
+ IN SD_MMC_UHS_TIMING Timing
+ )
+{
+ EFI_STATUS Status;
+ UINT8 HostCtrl2;
+
+ HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;
+ Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ switch (Timing) {
+ case SdMmcUhsSdr12:
+ HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;
+ break;
+ case SdMmcUhsSdr25:
+ HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;
+ break;
+ case SdMmcUhsSdr50:
+ HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;
+ break;
+ case SdMmcUhsSdr104:
+ HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;
+ break;
+ case SdMmcUhsDdr50:
+ HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;
+ break;
+ case SdMmcMmcDdr52:
+ HostCtrl2 = SD_MMC_HC_CTRL_MMC_DDR52;
+ break;
+ case SdMmcMmcSdr50:
+ HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR50;
+ break;
+ case SdMmcMmcSdr25:
+ HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR25;
+ break;
+ case SdMmcMmcSdr12:
+ HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR12;
+ break;
+ case SdMmcMmcHs200:
+ HostCtrl2 = SD_MMC_HC_CTRL_HS200;
+ break;
+ case SdMmcMmcHs400:
+ HostCtrl2 = SD_MMC_HC_CTRL_HS400;
+ break;
+ default:
+ HostCtrl2 = 0;
+ break;
+ }
+ Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
+
+ return Status;
+}
+
+/**
Turn on/off LED.
@param[in] PciIo The PCI IO protocol instance.
--
2.7.4
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 3/4] MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to SdMmcOverride
2018-10-05 13:25 [PATCH v2 0/4] SdMmcOverride extension Marcin Wojtas
2018-10-05 13:25 ` [PATCH v2 1/4] MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in NotifyPhase Marcin Wojtas
2018-10-05 13:25 ` [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol Marcin Wojtas
@ 2018-10-05 13:25 ` Marcin Wojtas
2018-10-08 12:44 ` Ard Biesheuvel
2018-11-01 7:06 ` Wu, Hao A
2018-10-05 13:25 ` [PATCH v2 4/4] MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequency Marcin Wojtas
` (2 subsequent siblings)
5 siblings, 2 replies; 47+ messages in thread
From: Marcin Wojtas @ 2018-10-05 13:25 UTC (permalink / raw)
To: edk2-devel
Cc: feng.tian, michael.d.kinney, liming.gao, leif.lindholm, hao.a.wu,
ard.biesheuvel, nadavh, mw, jsd, tm
From: Tomasz Michalec <tm@semihalf.com>
Some SD Host Controlers need to do additional opperations after clock
frequency switch.
This patch add new callback type to NotifyPhase of the SdMmcOverride
protocol. It is called after EmmcSwitchClockFreq and SdMmcHcClockSupply.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
MdeModulePkg/Include/Protocol/SdMmcOverride.h | 1 +
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 60 ++++++++++++++++++++
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 18 ++++++
3 files changed, 79 insertions(+)
diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
index 25db98a..d9daada 100644
--- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
+++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
@@ -33,6 +33,7 @@ typedef enum {
EdkiiSdMmcInitHostPre,
EdkiiSdMmcInitHostPost,
EdkiiSdMmcUhsSignaling,
+ EdkiiSdMmcSwitchClockFreqPost,
} EDKII_SD_MMC_PHASE_TYPE;
/**
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
index 05bd4a0..7e75283 100755
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
@@ -796,6 +796,27 @@ EmmcSwitchToHighSpeed (
HsTiming = 1;
Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, ClockFreq);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
+ Status = mOverride->NotifyPhase (
+ Private->ControllerHandle,
+ Slot,
+ EdkiiSdMmcSwitchClockFreqPost,
+ &Timing
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
+ __FUNCTION__,
+ Status
+ ));
+ return Status;
+ }
+ }
return Status;
}
@@ -905,6 +926,24 @@ EmmcSwitchToHS200 (
return Status;
}
+ if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
+ Status = mOverride->NotifyPhase (
+ Private->ControllerHandle,
+ Slot,
+ EdkiiSdMmcSwitchClockFreqPost,
+ &Timing
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
+ __FUNCTION__,
+ Status
+ ));
+ return Status;
+ }
+ }
+
Status = EmmcTuningClkForHs200 (PciIo, PassThru, Slot, BusWidth);
return Status;
@@ -989,6 +1028,27 @@ EmmcSwitchToHS400 (
HsTiming = 3;
Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, ClockFreq);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
+ Status = mOverride->NotifyPhase (
+ Private->ControllerHandle,
+ Slot,
+ EdkiiSdMmcSwitchClockFreqPost,
+ &Timing
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
+ __FUNCTION__,
+ Status
+ ));
+ return Status;
+ }
+ }
return Status;
}
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
index 5645a71..057a4e2 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
@@ -887,6 +887,24 @@ SdCardSetBusMode (
return Status;
}
+ if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
+ Status = mOverride->NotifyPhase (
+ Private->ControllerHandle,
+ Slot,
+ EdkiiSdMmcSwitchClockFreqPost,
+ &Timing
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
+ __FUNCTION__,
+ Status
+ ));
+ return Status;
+ }
+ }
+
if ((AccessMode == 3) || ((AccessMode == 2) && (Capability->TuningSDR50 != 0))) {
Status = SdCardTuningClock (PciIo, PassThru, Slot);
if (EFI_ERROR (Status)) {
--
2.7.4
^ permalink raw reply related [flat|nested] 47+ messages in thread
* [PATCH v2 4/4] MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequency
2018-10-05 13:25 [PATCH v2 0/4] SdMmcOverride extension Marcin Wojtas
` (2 preceding siblings ...)
2018-10-05 13:25 ` [PATCH v2 3/4] MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to SdMmcOverride Marcin Wojtas
@ 2018-10-05 13:25 ` Marcin Wojtas
2018-10-08 12:49 ` Ard Biesheuvel
2018-11-01 7:11 ` Wu, Hao A
2018-10-12 5:24 ` [PATCH v2 0/4] SdMmcOverride extension Wu, Hao A
2018-11-01 7:11 ` Wu, Hao A
5 siblings, 2 replies; 47+ messages in thread
From: Marcin Wojtas @ 2018-10-05 13:25 UTC (permalink / raw)
To: edk2-devel
Cc: feng.tian, michael.d.kinney, liming.gao, leif.lindholm, hao.a.wu,
ard.biesheuvel, nadavh, mw, jsd, tm
Some SdMmc host controllers are run by clocks with different
frequency than it is reflected in Capabilities Register 1.
It is allowed by SDHCI specification ver. 4.2 - if BaseClkFreq
field value of the Capability Register 1 is zero, the clock
frequency must be obtained via another method.
Because the bitfield is only 8 bits wide, a maximum value
that could be obtained from hardware is 255MHz.
In case the actual frequency exceeds 255MHz, the 8-bit BaseClkFreq
member of SD_MMC_HC_SLOT_CAP structure occurs to be not sufficient
to be used for setting the clock speed in SdMmcHcClockSupply
function.
This patch adds new UINT32 array ('BaseClkFreq[]') to
SD_MMC_HC_PRIVATE_DATA structure for specifying
the input clock speed for each slot of the host controller.
All routines that are used for clock configuration are
updated accordingly.
This patch also adds new IN OUT BaseClockFreq field
in the Capability callback of the SdMmcOverride,
protocol which allows to update BaseClkFreq value.
The patch reuses original commit from edk2-platforms:
20f6f144d3a8 ("Marvell/Drivers: XenonDxe: Allow overriding base clock
frequency")
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 6 +++++
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 12 +++++----
MdeModulePkg/Include/Protocol/SdMmcOverride.h | 5 +++-
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 4 +--
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 4 +--
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 18 +++++++++++--
MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 27 +++++++++++---------
7 files changed, 52 insertions(+), 24 deletions(-)
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
index c683600..8c1a589 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
@@ -118,6 +118,12 @@ typedef struct {
UINT64 MaxCurrent[SD_MMC_HC_MAX_SLOT];
UINT32 ControllerVersion;
+
+ //
+ // Some controllers may require to override base clock frequency
+ // value stored in Capabilities Register 1.
+ //
+ UINT32 BaseClkFreq[SD_MMC_HC_MAX_SLOT];
} SD_MMC_HC_PRIVATE_DATA;
#define SD_MMC_HC_TRB_SIG SIGNATURE_32 ('T', 'R', 'B', 'T')
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
index a03160d..f01ba21 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
@@ -173,12 +173,14 @@ typedef struct {
@param[in] Slot The slot number of the SD card to send the command to.
@param[in] Capability The buffer to store the capability data.
+ @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
**/
VOID
DumpCapabilityReg (
IN UINT8 Slot,
- IN SD_MMC_HC_SLOT_CAP *Capability
+ IN SD_MMC_HC_SLOT_CAP *Capability,
+ IN UINT32 BaseClkFreq
);
/**
@@ -431,7 +433,7 @@ SdMmcHcStopClock (
@param[in] PciIo The PCI IO protocol instance.
@param[in] Slot The slot number of the SD card to send the command to.
@param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
- @param[in] Capability The capability of the slot.
+ @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
@retval EFI_SUCCESS The clock is supplied successfully.
@retval Others The clock isn't supplied successfully.
@@ -442,7 +444,7 @@ SdMmcHcClockSupply (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
IN UINT64 ClockFreq,
- IN SD_MMC_HC_SLOT_CAP Capability
+ IN UINT32 BaseClkFreq
);
/**
@@ -490,7 +492,7 @@ SdMmcHcSetBusWidth (
@param[in] PciIo The PCI IO protocol instance.
@param[in] Slot The slot number of the SD card to send the command to.
- @param[in] Capability The capability of the slot.
+ @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
@retval EFI_SUCCESS The clock is supplied successfully.
@retval Others The clock isn't supplied successfully.
@@ -500,7 +502,7 @@ EFI_STATUS
SdMmcHcInitClockFreq (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
- IN SD_MMC_HC_SLOT_CAP Capability
+ IN UINT32 BaseClkFreq
);
/**
diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
index d9daada..27023d3 100644
--- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
+++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
@@ -43,6 +43,8 @@ typedef enum {
@param[in] ControllerHandle The EFI_HANDLE of the controller.
@param[in] Slot The 0 based slot index.
@param[in,out] SdMmcHcSlotCapability The SDHCI capability structure.
+ @param[in,out] BaseClkFreq The base clock frequency value that
+ optionally can be updated.
@retval EFI_SUCCESS The override function completed successfully.
@retval EFI_NOT_FOUND The specified controller or slot does not exist.
@@ -54,7 +56,8 @@ EFI_STATUS
(EFIAPI * EDKII_SD_MMC_CAPABILITY) (
IN EFI_HANDLE ControllerHandle,
IN UINT8 Slot,
- IN OUT VOID *SdMmcHcSlotCapability
+ IN OUT VOID *SdMmcHcSlotCapability,
+ IN OUT UINT32 *BaseClkFreq
);
/**
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
index 7e75283..27ccd63 100755
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
@@ -705,7 +705,7 @@ EmmcSwitchClockFreq (
//
// Convert the clock freq unit from MHz to KHz.
//
- Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->Capability[Slot]);
+ Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->BaseClkFreq[Slot]);
return Status;
}
@@ -1099,7 +1099,7 @@ EmmcSetBusMode (
return Status;
}
- ASSERT (Private->Capability[Slot].BaseClkFreq != 0);
+ ASSERT (Private->BaseClkFreq[Slot] != 0);
//
// Check if the Host Controller support 8bits bus width.
//
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
index 057a4e2..9ea13be 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
@@ -882,7 +882,7 @@ SdCardSetBusMode (
}
}
- Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capability);
+ Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->BaseClkFreq[Slot]);
if (EFI_ERROR (Status)) {
return Status;
}
@@ -1081,7 +1081,7 @@ SdCardIdentification (
goto Error;
}
- SdMmcHcInitClockFreq (PciIo, Slot, Private->Capability[Slot]);
+ SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot]);
gBS->Stall (1000);
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
index bf9869d..d7cc0ce 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
@@ -625,18 +625,32 @@ SdMmcPciHcDriverBindingStart (
if (EFI_ERROR (Status)) {
continue;
}
+
+ Private->BaseClkFreq[Slot] = Private->Capability[Slot].BaseClkFreq;
+
if (mOverride != NULL && mOverride->Capability != NULL) {
Status = mOverride->Capability (
Controller,
Slot,
- &Private->Capability[Slot]);
+ &Private->Capability[Slot],
+ &Private->BaseClkFreq[Slot]
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_WARN, "%a: Failed to override capability - %r\n",
__FUNCTION__, Status));
continue;
}
}
- DumpCapabilityReg (Slot, &Private->Capability[Slot]);
+
+ //
+ // According to SDHCI specification ver. 4.2, BaseClkFreq field value of
+ // the Capability Register 1 can be zero, which means a need for obtaining
+ // the clock frequency via another method. Fail in case it is not updated
+ // by SW at this point.
+ //
+ ASSERT (Private->BaseClkFreq[Slot] != 0);
+
+ DumpCapabilityReg (Slot, &Private->Capability[Slot], Private->BaseClkFreq[Slot]);
Support64BitDma &= Private->Capability[Slot].SysBus64;
diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
index 38d6202..9f50754 100644
--- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
+++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
@@ -22,12 +22,14 @@
@param[in] Slot The slot number of the SD card to send the command to.
@param[in] Capability The buffer to store the capability data.
+ @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
**/
VOID
DumpCapabilityReg (
IN UINT8 Slot,
- IN SD_MMC_HC_SLOT_CAP *Capability
+ IN SD_MMC_HC_SLOT_CAP *Capability,
+ IN UINT32 BaseClkFreq
)
{
//
@@ -35,7 +37,10 @@ DumpCapabilityReg (
//
DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));
DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));
- DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));
+ if (Capability->BaseClkFreq != BaseClkFreq) {
+ DEBUG ((DEBUG_INFO, " Controller register value overriden:\n"));
+ }
+ DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", BaseClkFreq));
DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));
DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));
DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));
@@ -721,7 +726,7 @@ SdMmcHcStopClock (
@param[in] PciIo The PCI IO protocol instance.
@param[in] Slot The slot number of the SD card to send the command to.
@param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
- @param[in] Capability The capability of the slot.
+ @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
@retval EFI_SUCCESS The clock is supplied successfully.
@retval Others The clock isn't supplied successfully.
@@ -732,11 +737,10 @@ SdMmcHcClockSupply (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
IN UINT64 ClockFreq,
- IN SD_MMC_HC_SLOT_CAP Capability
+ IN UINT32 BaseClkFreq
)
{
EFI_STATUS Status;
- UINT32 BaseClkFreq;
UINT32 SettingFreq;
UINT32 Divisor;
UINT32 Remainder;
@@ -746,9 +750,8 @@ SdMmcHcClockSupply (
//
// Calculate a divisor for SD clock frequency
//
- ASSERT (Capability.BaseClkFreq != 0);
+ ASSERT (BaseClkFreq != 0);
- BaseClkFreq = Capability.BaseClkFreq;
if (ClockFreq == 0) {
return EFI_INVALID_PARAMETER;
}
@@ -939,7 +942,7 @@ SdMmcHcSetBusWidth (
@param[in] PciIo The PCI IO protocol instance.
@param[in] Slot The slot number of the SD card to send the command to.
- @param[in] Capability The capability of the slot.
+ @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
@retval EFI_SUCCESS The clock is supplied successfully.
@retval Others The clock isn't supplied successfully.
@@ -949,7 +952,7 @@ EFI_STATUS
SdMmcHcInitClockFreq (
IN EFI_PCI_IO_PROTOCOL *PciIo,
IN UINT8 Slot,
- IN SD_MMC_HC_SLOT_CAP Capability
+ IN UINT32 BaseClkFreq
)
{
EFI_STATUS Status;
@@ -958,7 +961,7 @@ SdMmcHcInitClockFreq (
//
// Calculate a divisor for SD clock frequency
//
- if (Capability.BaseClkFreq == 0) {
+ if (BaseClkFreq == 0) {
//
// Don't support get Base Clock Frequency information via another method
//
@@ -968,7 +971,7 @@ SdMmcHcInitClockFreq (
// Supply 400KHz clock frequency at initialization phase.
//
InitFreq = 400;
- Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, Capability);
+ Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, BaseClkFreq);
return Status;
}
@@ -1102,7 +1105,7 @@ SdMmcHcInitHost (
PciIo = Private->PciIo;
Capability = Private->Capability[Slot];
- Status = SdMmcHcInitClockFreq (PciIo, Slot, Capability);
+ Status = SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot]);
if (EFI_ERROR (Status)) {
return Status;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-05 13:25 ` [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol Marcin Wojtas
@ 2018-10-05 15:12 ` Philippe Mathieu-Daudé
2018-10-05 15:17 ` Marcin Wojtas
2018-10-08 12:41 ` Ard Biesheuvel
2018-11-01 7:04 ` Wu, Hao A
2 siblings, 1 reply; 47+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-10-05 15:12 UTC (permalink / raw)
To: Marcin Wojtas, edk2-devel
Cc: feng.tian, tm, hao.a.wu, nadavh, liming.gao, michael.d.kinney
Hi Marcin, Tomasz.
On 05/10/2018 15:25, Marcin Wojtas wrote:
> From: Tomasz Michalec <tm@semihalf.com>
>
> Some SD Host Controlers use different values in Host Control 2 Register
My two cents, in various places "Controler" is miswritten, this should
be "Controller".
> to select UHS Mode. This patch adds a new UhsSignaling type routine to
> the NotifyPhase of the SdMmcOverride protocol.
>
> UHS signaling configuration is moved to a common, default routine
> (SdMmcHcUhsSignaling), which is called when SdMmcOverride does not
> cover this functionality.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 50 +++++++
> MdeModulePkg/Include/Protocol/SdMmcOverride.h | 2 +
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 153 ++++++++++++--------
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 37 +++--
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 69 +++++++++
> 5 files changed, 243 insertions(+), 68 deletions(-)
>
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> index e389d52..a03160d 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> @@ -63,6 +63,39 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> #define SD_MMC_HC_CTRL_VER 0xFE
>
> //
> +// SD Host Controler bits to HOST_CTRL2 register
> +//
> +#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
> +#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
> +#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
> +#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
> +#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
> +#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
> +#define SD_MMC_HC_CTRL_MMC_DDR52 0x0004
> +#define SD_MMC_HC_CTRL_MMC_SDR50 0x0002
> +#define SD_MMC_HC_CTRL_MMC_SDR25 0x0001
> +#define SD_MMC_HC_CTRL_MMC_SDR12 0x0000
> +#define SD_MMC_HC_CTRL_HS200 0x0003
> +#define SD_MMC_HC_CTRL_HS400 0x0005
> +
> +//
> +// Timing modes for uhs
> +//
> +typedef enum {
> + SdMmcUhsSdr12,
> + SdMmcUhsSdr25,
> + SdMmcUhsSdr50,
> + SdMmcUhsSdr104,
> + SdMmcUhsDdr50,
> + SdMmcMmcDdr52,
> + SdMmcMmcSdr50,
> + SdMmcMmcSdr25,
> + SdMmcMmcSdr12,
> + SdMmcMmcHs200,
> + SdMmcMmcHs400,
> +} SD_MMC_UHS_TIMING;
> +
> +//
> // The transfer modes supported by SD Host Controller
> // Simplified Spec 3.0 Table 1-2
> //
> @@ -508,4 +541,21 @@ SdMmcHcInitTimeoutCtrl (
> IN UINT8 Slot
> );
>
> +/**
> + Set SD Host Controler control 2 registry according to selected speed.
> +
> + @param[in] PciIo The PCI IO protocol instance.
> + @param[in] Slot The slot number of the SD card to send the command to.
> + @param[in] Timing The timing to select.
> +
> + @retval EFI_SUCCESS The timing is set successfully.
> + @retval Others The timing isn't set successfully.
> +**/
> +EFI_STATUS
> +SdMmcHcUhsSignaling (
> + IN EFI_PCI_IO_PROTOCOL *PciIo,
> + IN UINT8 Slot,
> + IN SD_MMC_UHS_TIMING Timing
> + );
> +
> #endif
> diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> index 178945f..25db98a 100644
> --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> @@ -17,6 +17,7 @@
> #ifndef __SD_MMC_OVERRIDE_H__
> #define __SD_MMC_OVERRIDE_H__
>
> +#include <Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h>
> #include <Protocol/SdMmcPassThru.h>
>
> #define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \
> @@ -31,6 +32,7 @@ typedef enum {
> EdkiiSdMmcResetPost,
> EdkiiSdMmcInitHostPre,
> EdkiiSdMmcInitHostPost,
> + EdkiiSdMmcUhsSignaling,
> } EDKII_SD_MMC_PHASE_TYPE;
>
> /**
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> index c5fd214..05bd4a0 100755
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> @@ -740,10 +740,13 @@ EmmcSwitchToHighSpeed (
> IN UINT8 BusWidth
> )
> {
> - EFI_STATUS Status;
> - UINT8 HsTiming;
> - UINT8 HostCtrl1;
> - UINT8 HostCtrl2;
> + EFI_STATUS Status;
> + UINT8 HsTiming;
> + UINT8 HostCtrl1;
> + SD_MMC_UHS_TIMING Timing;
> + SD_MMC_HC_PRIVATE_DATA *Private;
> +
> + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
>
> Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusWidth);
> if (EFI_ERROR (Status)) {
> @@ -758,27 +761,37 @@ EmmcSwitchToHighSpeed (
> return Status;
> }
>
> - //
> - // Clean UHS Mode Select field of Host Control 2 reigster before update
> - //
> - HostCtrl2 = (UINT8)~0x7;
> - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> - }
> - //
> - // Set UHS Mode Select field of Host Control 2 reigster to SDR12/25/50
> - //
> if (IsDdr) {
> - HostCtrl2 = BIT2;
> + Timing = SdMmcMmcDdr52;
> } else if (ClockFreq == 52) {
> - HostCtrl2 = BIT0;
> + Timing = SdMmcMmcSdr50;
> + } else if (ClockFreq == 26) {
> + Timing = SdMmcMmcSdr25;
> } else {
> - HostCtrl2 = 0;
> + Timing = SdMmcMmcSdr12;
> }
> - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> +
> + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> + Status = mOverride->NotifyPhase (
> + Private->ControllerHandle,
> + Slot,
> + EdkiiSdMmcUhsSignaling,
> + &Timing
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> + __FUNCTION__,
> + Status
> + ));
> + return Status;
> + }
> + } else {
> + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> }
>
> HsTiming = 1;
> @@ -814,10 +827,13 @@ EmmcSwitchToHS200 (
> IN UINT8 BusWidth
> )
> {
> - EFI_STATUS Status;
> - UINT8 HsTiming;
> - UINT8 HostCtrl2;
> - UINT16 ClockCtrl;
> + EFI_STATUS Status;
> + UINT8 HsTiming;
> + UINT16 ClockCtrl;
> + SD_MMC_UHS_TIMING Timing;
> + SD_MMC_HC_PRIVATE_DATA *Private;
> +
> + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
>
> if ((BusWidth != 4) && (BusWidth != 8)) {
> return EFI_INVALID_PARAMETER;
> @@ -837,21 +853,30 @@ EmmcSwitchToHS200 (
> if (EFI_ERROR (Status)) {
> return Status;
> }
> - //
> - // Clean UHS Mode Select field of Host Control 2 reigster before update
> - //
> - HostCtrl2 = (UINT8)~0x7;
> - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> - }
> - //
> - // Set UHS Mode Select field of Host Control 2 reigster to SDR104
> - //
> - HostCtrl2 = BIT0 | BIT1;
> - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> +
> + Timing = SdMmcMmcHs200;
> +
> + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> + Status = mOverride->NotifyPhase (
> + Private->ControllerHandle,
> + Slot,
> + EdkiiSdMmcUhsSignaling,
> + &Timing
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> + __FUNCTION__,
> + Status
> + ));
> + return Status;
> + }
> + } else {
> + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> }
> //
> // Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit
> @@ -910,9 +935,12 @@ EmmcSwitchToHS400 (
> IN UINT32 ClockFreq
> )
> {
> - EFI_STATUS Status;
> - UINT8 HsTiming;
> - UINT8 HostCtrl2;
> + EFI_STATUS Status;
> + UINT8 HsTiming;
> + SD_MMC_UHS_TIMING Timing;
> + SD_MMC_HC_PRIVATE_DATA *Private;
> +
> + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
>
> Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, ClockFreq, 8);
> if (EFI_ERROR (Status)) {
> @@ -933,21 +961,30 @@ EmmcSwitchToHS400 (
> if (EFI_ERROR (Status)) {
> return Status;
> }
> - //
> - // Clean UHS Mode Select field of Host Control 2 reigster before update
> - //
> - HostCtrl2 = (UINT8)~0x7;
> - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> - }
> - //
> - // Set UHS Mode Select field of Host Control 2 reigster to HS400
> - //
> - HostCtrl2 = BIT0 | BIT2;
> - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> +
> + Timing = SdMmcMmcHs400;
> +
> + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> + Status = mOverride->NotifyPhase (
> + Private->ControllerHandle,
> + Slot,
> + EdkiiSdMmcUhsSignaling,
> + &Timing
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> + __FUNCTION__,
> + Status
> + ));
> + return Status;
> + }
> + } else {
> + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> }
>
> HsTiming = 3;
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> index 8c93933..5645a71 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> @@ -784,8 +784,8 @@ SdCardSetBusMode (
> UINT8 BusWidth;
> UINT8 AccessMode;
> UINT8 HostCtrl1;
> - UINT8 HostCtrl2;
> UINT8 SwitchResp[64];
> + SD_MMC_UHS_TIMING Timing;
> SD_MMC_HC_PRIVATE_DATA *Private;
>
> Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> @@ -817,18 +817,23 @@ SdCardSetBusMode (
> if (S18A && (Capability->Sdr104 != 0) && ((SwitchResp[13] & BIT3) != 0)) {
> ClockFreq = 208;
> AccessMode = 3;
> + Timing = SdMmcUhsSdr104;
> } else if (S18A && (Capability->Sdr50 != 0) && ((SwitchResp[13] & BIT2) != 0)) {
> ClockFreq = 100;
> AccessMode = 2;
> + Timing = SdMmcUhsSdr50;
> } else if (S18A && (Capability->Ddr50 != 0) && ((SwitchResp[13] & BIT4) != 0)) {
> ClockFreq = 50;
> AccessMode = 4;
> + Timing = SdMmcUhsDdr50;
> } else if ((SwitchResp[13] & BIT1) != 0) {
> ClockFreq = 50;
> AccessMode = 1;
> + Timing = SdMmcUhsSdr25;
> } else {
> ClockFreq = 25;
> AccessMode = 0;
> + Timing = SdMmcUhsSdr12;
> }
>
> Status = SdCardSwitch (PassThru, Slot, AccessMode, 0xF, 0xF, 0xF, TRUE, SwitchResp);
> @@ -854,15 +859,27 @@ SdCardSetBusMode (
> }
> }
>
> - HostCtrl2 = (UINT8)~0x7;
> - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> - }
> - HostCtrl2 = AccessMode;
> - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> + Status = mOverride->NotifyPhase (
> + Private->ControllerHandle,
> + Slot,
> + EdkiiSdMmcUhsSignaling,
> + &Timing
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> + __FUNCTION__,
> + Status
> + ));
> + return Status;
> + }
> + } else {
> + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> }
>
> Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capability);
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> index 02eb4ad..38d6202 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> @@ -1137,6 +1137,75 @@ SdMmcHcInitHost (
> }
>
> /**
> + Set SD Host Controler control 2 registry according to selected speed.
> +
> + @param[in] PciIo The PCI IO protocol instance.
> + @param[in] Slot The slot number of the SD card to send the command to.
> + @param[in] Timing The timing to select.
> +
> + @retval EFI_SUCCESS The timing is set successfully.
> + @retval Others The timing isn't set successfully.
> +**/
> +EFI_STATUS
> +SdMmcHcUhsSignaling (
> + IN EFI_PCI_IO_PROTOCOL *PciIo,
> + IN UINT8 Slot,
> + IN SD_MMC_UHS_TIMING Timing
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 HostCtrl2;
> +
> + HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;
> + Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + switch (Timing) {
> + case SdMmcUhsSdr12:
> + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;
> + break;
> + case SdMmcUhsSdr25:
> + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;
> + break;
> + case SdMmcUhsSdr50:
> + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;
> + break;
> + case SdMmcUhsSdr104:
> + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;
> + break;
> + case SdMmcUhsDdr50:
> + HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;
> + break;
> + case SdMmcMmcDdr52:
> + HostCtrl2 = SD_MMC_HC_CTRL_MMC_DDR52;
> + break;
> + case SdMmcMmcSdr50:
> + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR50;
> + break;
> + case SdMmcMmcSdr25:
> + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR25;
> + break;
> + case SdMmcMmcSdr12:
> + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR12;
> + break;
> + case SdMmcMmcHs200:
> + HostCtrl2 = SD_MMC_HC_CTRL_HS200;
> + break;
> + case SdMmcMmcHs400:
> + HostCtrl2 = SD_MMC_HC_CTRL_HS400;
> + break;
> + default:
> + HostCtrl2 = 0;
> + break;
> + }
> + Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> +
> + return Status;
> +}
> +
> +/**
> Turn on/off LED.
>
> @param[in] PciIo The PCI IO protocol instance.
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-05 15:12 ` Philippe Mathieu-Daudé
@ 2018-10-05 15:17 ` Marcin Wojtas
0 siblings, 0 replies; 47+ messages in thread
From: Marcin Wojtas @ 2018-10-05 15:17 UTC (permalink / raw)
To: philmd
Cc: edk2-devel-01, Tian, Feng, Tomasz Michalec, hao.a.wu, nadavh,
Gao, Liming, Kinney, Michael D
pt., 5 paź 2018 o 17:12 Philippe Mathieu-Daudé <philmd@redhat.com> napisał(a):
>
> Hi Marcin, Tomasz.
>
> On 05/10/2018 15:25, Marcin Wojtas wrote:
> > From: Tomasz Michalec <tm@semihalf.com>
> >
> > Some SD Host Controlers use different values in Host Control 2 Register
>
> My two cents, in various places "Controler" is miswritten, this should
> be "Controller".
Thanks, missed that. It will be corrected in the next revision.
Best regards,
Marcin
>
> > to select UHS Mode. This patch adds a new UhsSignaling type routine to
> > the NotifyPhase of the SdMmcOverride protocol.
> >
> > UHS signaling configuration is moved to a common, default routine
> > (SdMmcHcUhsSignaling), which is called when SdMmcOverride does not
> > cover this functionality.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> > ---
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 50 +++++++
> > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 2 +
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 153 ++++++++++++--------
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 37 +++--
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 69 +++++++++
> > 5 files changed, 243 insertions(+), 68 deletions(-)
> >
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > index e389d52..a03160d 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > @@ -63,6 +63,39 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> > #define SD_MMC_HC_CTRL_VER 0xFE
> >
> > //
> > +// SD Host Controler bits to HOST_CTRL2 register
> > +//
> > +#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
> > +#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
> > +#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
> > +#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
> > +#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
> > +#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
> > +#define SD_MMC_HC_CTRL_MMC_DDR52 0x0004
> > +#define SD_MMC_HC_CTRL_MMC_SDR50 0x0002
> > +#define SD_MMC_HC_CTRL_MMC_SDR25 0x0001
> > +#define SD_MMC_HC_CTRL_MMC_SDR12 0x0000
> > +#define SD_MMC_HC_CTRL_HS200 0x0003
> > +#define SD_MMC_HC_CTRL_HS400 0x0005
> > +
> > +//
> > +// Timing modes for uhs
> > +//
> > +typedef enum {
> > + SdMmcUhsSdr12,
> > + SdMmcUhsSdr25,
> > + SdMmcUhsSdr50,
> > + SdMmcUhsSdr104,
> > + SdMmcUhsDdr50,
> > + SdMmcMmcDdr52,
> > + SdMmcMmcSdr50,
> > + SdMmcMmcSdr25,
> > + SdMmcMmcSdr12,
> > + SdMmcMmcHs200,
> > + SdMmcMmcHs400,
> > +} SD_MMC_UHS_TIMING;
> > +
> > +//
> > // The transfer modes supported by SD Host Controller
> > // Simplified Spec 3.0 Table 1-2
> > //
> > @@ -508,4 +541,21 @@ SdMmcHcInitTimeoutCtrl (
> > IN UINT8 Slot
> > );
> >
> > +/**
> > + Set SD Host Controler control 2 registry according to selected speed.
> > +
> > + @param[in] PciIo The PCI IO protocol instance.
> > + @param[in] Slot The slot number of the SD card to send the command to.
> > + @param[in] Timing The timing to select.
> > +
> > + @retval EFI_SUCCESS The timing is set successfully.
> > + @retval Others The timing isn't set successfully.
> > +**/
> > +EFI_STATUS
> > +SdMmcHcUhsSignaling (
> > + IN EFI_PCI_IO_PROTOCOL *PciIo,
> > + IN UINT8 Slot,
> > + IN SD_MMC_UHS_TIMING Timing
> > + );
> > +
> > #endif
> > diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > index 178945f..25db98a 100644
> > --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > @@ -17,6 +17,7 @@
> > #ifndef __SD_MMC_OVERRIDE_H__
> > #define __SD_MMC_OVERRIDE_H__
> >
> > +#include <Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h>
> > #include <Protocol/SdMmcPassThru.h>
> >
> > #define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \
> > @@ -31,6 +32,7 @@ typedef enum {
> > EdkiiSdMmcResetPost,
> > EdkiiSdMmcInitHostPre,
> > EdkiiSdMmcInitHostPost,
> > + EdkiiSdMmcUhsSignaling,
> > } EDKII_SD_MMC_PHASE_TYPE;
> >
> > /**
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > index c5fd214..05bd4a0 100755
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > @@ -740,10 +740,13 @@ EmmcSwitchToHighSpeed (
> > IN UINT8 BusWidth
> > )
> > {
> > - EFI_STATUS Status;
> > - UINT8 HsTiming;
> > - UINT8 HostCtrl1;
> > - UINT8 HostCtrl2;
> > + EFI_STATUS Status;
> > + UINT8 HsTiming;
> > + UINT8 HostCtrl1;
> > + SD_MMC_UHS_TIMING Timing;
> > + SD_MMC_HC_PRIVATE_DATA *Private;
> > +
> > + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> >
> > Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusWidth);
> > if (EFI_ERROR (Status)) {
> > @@ -758,27 +761,37 @@ EmmcSwitchToHighSpeed (
> > return Status;
> > }
> >
> > - //
> > - // Clean UHS Mode Select field of Host Control 2 reigster before update
> > - //
> > - HostCtrl2 = (UINT8)~0x7;
> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> > - if (EFI_ERROR (Status)) {
> > - return Status;
> > - }
> > - //
> > - // Set UHS Mode Select field of Host Control 2 reigster to SDR12/25/50
> > - //
> > if (IsDdr) {
> > - HostCtrl2 = BIT2;
> > + Timing = SdMmcMmcDdr52;
> > } else if (ClockFreq == 52) {
> > - HostCtrl2 = BIT0;
> > + Timing = SdMmcMmcSdr50;
> > + } else if (ClockFreq == 26) {
> > + Timing = SdMmcMmcSdr25;
> > } else {
> > - HostCtrl2 = 0;
> > + Timing = SdMmcMmcSdr12;
> > }
> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> > - if (EFI_ERROR (Status)) {
> > - return Status;
> > +
> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> > + Status = mOverride->NotifyPhase (
> > + Private->ControllerHandle,
> > + Slot,
> > + EdkiiSdMmcUhsSignaling,
> > + &Timing
> > + );
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((
> > + DEBUG_ERROR,
> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> > + __FUNCTION__,
> > + Status
> > + ));
> > + return Status;
> > + }
> > + } else {
> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > }
> >
> > HsTiming = 1;
> > @@ -814,10 +827,13 @@ EmmcSwitchToHS200 (
> > IN UINT8 BusWidth
> > )
> > {
> > - EFI_STATUS Status;
> > - UINT8 HsTiming;
> > - UINT8 HostCtrl2;
> > - UINT16 ClockCtrl;
> > + EFI_STATUS Status;
> > + UINT8 HsTiming;
> > + UINT16 ClockCtrl;
> > + SD_MMC_UHS_TIMING Timing;
> > + SD_MMC_HC_PRIVATE_DATA *Private;
> > +
> > + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> >
> > if ((BusWidth != 4) && (BusWidth != 8)) {
> > return EFI_INVALID_PARAMETER;
> > @@ -837,21 +853,30 @@ EmmcSwitchToHS200 (
> > if (EFI_ERROR (Status)) {
> > return Status;
> > }
> > - //
> > - // Clean UHS Mode Select field of Host Control 2 reigster before update
> > - //
> > - HostCtrl2 = (UINT8)~0x7;
> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> > - if (EFI_ERROR (Status)) {
> > - return Status;
> > - }
> > - //
> > - // Set UHS Mode Select field of Host Control 2 reigster to SDR104
> > - //
> > - HostCtrl2 = BIT0 | BIT1;
> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> > - if (EFI_ERROR (Status)) {
> > - return Status;
> > +
> > + Timing = SdMmcMmcHs200;
> > +
> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> > + Status = mOverride->NotifyPhase (
> > + Private->ControllerHandle,
> > + Slot,
> > + EdkiiSdMmcUhsSignaling,
> > + &Timing
> > + );
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((
> > + DEBUG_ERROR,
> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> > + __FUNCTION__,
> > + Status
> > + ));
> > + return Status;
> > + }
> > + } else {
> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > }
> > //
> > // Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit
> > @@ -910,9 +935,12 @@ EmmcSwitchToHS400 (
> > IN UINT32 ClockFreq
> > )
> > {
> > - EFI_STATUS Status;
> > - UINT8 HsTiming;
> > - UINT8 HostCtrl2;
> > + EFI_STATUS Status;
> > + UINT8 HsTiming;
> > + SD_MMC_UHS_TIMING Timing;
> > + SD_MMC_HC_PRIVATE_DATA *Private;
> > +
> > + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> >
> > Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, ClockFreq, 8);
> > if (EFI_ERROR (Status)) {
> > @@ -933,21 +961,30 @@ EmmcSwitchToHS400 (
> > if (EFI_ERROR (Status)) {
> > return Status;
> > }
> > - //
> > - // Clean UHS Mode Select field of Host Control 2 reigster before update
> > - //
> > - HostCtrl2 = (UINT8)~0x7;
> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> > - if (EFI_ERROR (Status)) {
> > - return Status;
> > - }
> > - //
> > - // Set UHS Mode Select field of Host Control 2 reigster to HS400
> > - //
> > - HostCtrl2 = BIT0 | BIT2;
> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> > - if (EFI_ERROR (Status)) {
> > - return Status;
> > +
> > + Timing = SdMmcMmcHs400;
> > +
> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> > + Status = mOverride->NotifyPhase (
> > + Private->ControllerHandle,
> > + Slot,
> > + EdkiiSdMmcUhsSignaling,
> > + &Timing
> > + );
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((
> > + DEBUG_ERROR,
> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> > + __FUNCTION__,
> > + Status
> > + ));
> > + return Status;
> > + }
> > + } else {
> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > }
> >
> > HsTiming = 3;
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > index 8c93933..5645a71 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > @@ -784,8 +784,8 @@ SdCardSetBusMode (
> > UINT8 BusWidth;
> > UINT8 AccessMode;
> > UINT8 HostCtrl1;
> > - UINT8 HostCtrl2;
> > UINT8 SwitchResp[64];
> > + SD_MMC_UHS_TIMING Timing;
> > SD_MMC_HC_PRIVATE_DATA *Private;
> >
> > Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> > @@ -817,18 +817,23 @@ SdCardSetBusMode (
> > if (S18A && (Capability->Sdr104 != 0) && ((SwitchResp[13] & BIT3) != 0)) {
> > ClockFreq = 208;
> > AccessMode = 3;
> > + Timing = SdMmcUhsSdr104;
> > } else if (S18A && (Capability->Sdr50 != 0) && ((SwitchResp[13] & BIT2) != 0)) {
> > ClockFreq = 100;
> > AccessMode = 2;
> > + Timing = SdMmcUhsSdr50;
> > } else if (S18A && (Capability->Ddr50 != 0) && ((SwitchResp[13] & BIT4) != 0)) {
> > ClockFreq = 50;
> > AccessMode = 4;
> > + Timing = SdMmcUhsDdr50;
> > } else if ((SwitchResp[13] & BIT1) != 0) {
> > ClockFreq = 50;
> > AccessMode = 1;
> > + Timing = SdMmcUhsSdr25;
> > } else {
> > ClockFreq = 25;
> > AccessMode = 0;
> > + Timing = SdMmcUhsSdr12;
> > }
> >
> > Status = SdCardSwitch (PassThru, Slot, AccessMode, 0xF, 0xF, 0xF, TRUE, SwitchResp);
> > @@ -854,15 +859,27 @@ SdCardSetBusMode (
> > }
> > }
> >
> > - HostCtrl2 = (UINT8)~0x7;
> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> > - if (EFI_ERROR (Status)) {
> > - return Status;
> > - }
> > - HostCtrl2 = AccessMode;
> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> > - if (EFI_ERROR (Status)) {
> > - return Status;
> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> > + Status = mOverride->NotifyPhase (
> > + Private->ControllerHandle,
> > + Slot,
> > + EdkiiSdMmcUhsSignaling,
> > + &Timing
> > + );
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((
> > + DEBUG_ERROR,
> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> > + __FUNCTION__,
> > + Status
> > + ));
> > + return Status;
> > + }
> > + } else {
> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > }
> >
> > Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capability);
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > index 02eb4ad..38d6202 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > @@ -1137,6 +1137,75 @@ SdMmcHcInitHost (
> > }
> >
> > /**
> > + Set SD Host Controler control 2 registry according to selected speed.
> > +
> > + @param[in] PciIo The PCI IO protocol instance.
> > + @param[in] Slot The slot number of the SD card to send the command to.
> > + @param[in] Timing The timing to select.
> > +
> > + @retval EFI_SUCCESS The timing is set successfully.
> > + @retval Others The timing isn't set successfully.
> > +**/
> > +EFI_STATUS
> > +SdMmcHcUhsSignaling (
> > + IN EFI_PCI_IO_PROTOCOL *PciIo,
> > + IN UINT8 Slot,
> > + IN SD_MMC_UHS_TIMING Timing
> > + )
> > +{
> > + EFI_STATUS Status;
> > + UINT8 HostCtrl2;
> > +
> > + HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;
> > + Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > +
> > + switch (Timing) {
> > + case SdMmcUhsSdr12:
> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;
> > + break;
> > + case SdMmcUhsSdr25:
> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;
> > + break;
> > + case SdMmcUhsSdr50:
> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;
> > + break;
> > + case SdMmcUhsSdr104:
> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;
> > + break;
> > + case SdMmcUhsDdr50:
> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;
> > + break;
> > + case SdMmcMmcDdr52:
> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_DDR52;
> > + break;
> > + case SdMmcMmcSdr50:
> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR50;
> > + break;
> > + case SdMmcMmcSdr25:
> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR25;
> > + break;
> > + case SdMmcMmcSdr12:
> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR12;
> > + break;
> > + case SdMmcMmcHs200:
> > + HostCtrl2 = SD_MMC_HC_CTRL_HS200;
> > + break;
> > + case SdMmcMmcHs400:
> > + HostCtrl2 = SD_MMC_HC_CTRL_HS400;
> > + break;
> > + default:
> > + HostCtrl2 = 0;
> > + break;
> > + }
> > + Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> > +
> > + return Status;
> > +}
> > +
> > +/**
> > Turn on/off LED.
> >
> > @param[in] PciIo The PCI IO protocol instance.
> >
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 1/4] MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in NotifyPhase
2018-10-05 13:25 ` [PATCH v2 1/4] MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in NotifyPhase Marcin Wojtas
@ 2018-10-08 12:21 ` Ard Biesheuvel
0 siblings, 0 replies; 47+ messages in thread
From: Ard Biesheuvel @ 2018-10-08 12:21 UTC (permalink / raw)
To: Marcin Wojtas, Zeng, Star, Eric Dong, Ruiyu Ni
Cc: edk2-devel@lists.01.org, Tian, Feng, Kinney, Michael D,
Gao, Liming, Leif Lindholm, Wu, Hao A, Nadav Haklai,
Jan Dąbroś, Tomasz Michalec
(add MdeModulePkg maintainers)
On 5 October 2018 at 15:25, Marcin Wojtas <mw@semihalf.com> wrote:
> In order to ensure bigger flexibility in the NotifyPhase
> routine of the SdMmcOverride protocol, enable using an
> optional phase-specific data. This will allow to exchange
> more information between the protocol producer driver
> and SdMmcPciHcDxe in the newly added callbacks.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
> MdeModulePkg/Include/Protocol/SdMmcOverride.h | 4 +++-
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 12 ++++++++----
> 2 files changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> index 0766252..178945f 100644
> --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> @@ -63,6 +63,7 @@ EFI_STATUS
> @param[in] PhaseType The type of operation and whether the
> hook is invoked right before (pre) or
> right after (post)
> + @param[in,out] Data The pointer to a phase-specific data.
>
> @retval EFI_SUCCESS The override function completed successfully.
> @retval EFI_NOT_FOUND The specified controller or slot does not exist.
> @@ -74,7 +75,8 @@ EFI_STATUS
> (EFIAPI * EDKII_SD_MMC_NOTIFY_PHASE) (
> IN EFI_HANDLE ControllerHandle,
> IN UINT8 Slot,
> - IN EDKII_SD_MMC_PHASE_TYPE PhaseType
> + IN EDKII_SD_MMC_PHASE_TYPE PhaseType,
> + IN OUT VOID *OptParam
Please use the same name in the comment block and in the actual prototype.
Also, could we use PhaseData as the name perhaps?
With those changes
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> );
>
> struct _EDKII_SD_MMC_OVERRIDE {
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> index 25771dc..02eb4ad 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> @@ -444,7 +444,8 @@ SdMmcHcReset (
> Status = mOverride->NotifyPhase (
> Private->ControllerHandle,
> Slot,
> - EdkiiSdMmcResetPre);
> + EdkiiSdMmcResetPre,
> + NULL);
> if (EFI_ERROR (Status)) {
> DEBUG ((DEBUG_WARN,
> "%a: SD/MMC pre reset notifier callback failed - %r\n",
> @@ -494,7 +495,8 @@ SdMmcHcReset (
> Status = mOverride->NotifyPhase (
> Private->ControllerHandle,
> Slot,
> - EdkiiSdMmcResetPost);
> + EdkiiSdMmcResetPost,
> + NULL);
> if (EFI_ERROR (Status)) {
> DEBUG ((DEBUG_WARN,
> "%a: SD/MMC post reset notifier callback failed - %r\n",
> @@ -1087,7 +1089,8 @@ SdMmcHcInitHost (
> Status = mOverride->NotifyPhase (
> Private->ControllerHandle,
> Slot,
> - EdkiiSdMmcInitHostPre);
> + EdkiiSdMmcInitHostPre,
> + NULL);
> if (EFI_ERROR (Status)) {
> DEBUG ((DEBUG_WARN,
> "%a: SD/MMC pre init notifier callback failed - %r\n",
> @@ -1122,7 +1125,8 @@ SdMmcHcInitHost (
> Status = mOverride->NotifyPhase (
> Private->ControllerHandle,
> Slot,
> - EdkiiSdMmcInitHostPost);
> + EdkiiSdMmcInitHostPost,
> + NULL);
> if (EFI_ERROR (Status)) {
> DEBUG ((DEBUG_WARN,
> "%a: SD/MMC post init notifier callback failed - %r\n",
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-05 13:25 ` [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol Marcin Wojtas
2018-10-05 15:12 ` Philippe Mathieu-Daudé
@ 2018-10-08 12:41 ` Ard Biesheuvel
2018-10-08 12:59 ` Marcin Wojtas
2018-11-01 7:04 ` Wu, Hao A
2 siblings, 1 reply; 47+ messages in thread
From: Ard Biesheuvel @ 2018-10-08 12:41 UTC (permalink / raw)
To: Marcin Wojtas, Zeng, Star, Eric Dong, Ruiyu Ni
Cc: edk2-devel@lists.01.org, Tian, Feng, Kinney, Michael D,
Gao, Liming, Leif Lindholm, Wu, Hao A, Nadav Haklai,
Jan Dąbroś, Tomasz Michalec
(add MdeModulePkg maintainers)
On 5 October 2018 at 15:25, Marcin Wojtas <mw@semihalf.com> wrote:
> From: Tomasz Michalec <tm@semihalf.com>
>
> Some SD Host Controlers use different values in Host Control 2 Register
> to select UHS Mode. This patch adds a new UhsSignaling type routine to
> the NotifyPhase of the SdMmcOverride protocol.
>
> UHS signaling configuration is moved to a common, default routine
> (SdMmcHcUhsSignaling), which is called when SdMmcOverride does not
> cover this functionality.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 50 +++++++
> MdeModulePkg/Include/Protocol/SdMmcOverride.h | 2 +
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 153 ++++++++++++--------
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 37 +++--
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 69 +++++++++
> 5 files changed, 243 insertions(+), 68 deletions(-)
>
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> index e389d52..a03160d 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> @@ -63,6 +63,39 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> #define SD_MMC_HC_CTRL_VER 0xFE
>
> //
> +// SD Host Controler bits to HOST_CTRL2 register
> +//
> +#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
> +#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
> +#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
> +#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
> +#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
> +#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
> +#define SD_MMC_HC_CTRL_MMC_DDR52 0x0004
> +#define SD_MMC_HC_CTRL_MMC_SDR50 0x0002
> +#define SD_MMC_HC_CTRL_MMC_SDR25 0x0001
> +#define SD_MMC_HC_CTRL_MMC_SDR12 0x0000
> +#define SD_MMC_HC_CTRL_HS200 0x0003
> +#define SD_MMC_HC_CTRL_HS400 0x0005
> +
> +//
> +// Timing modes for uhs
> +//
> +typedef enum {
> + SdMmcUhsSdr12,
> + SdMmcUhsSdr25,
> + SdMmcUhsSdr50,
> + SdMmcUhsSdr104,
> + SdMmcUhsDdr50,
> + SdMmcMmcDdr52,
> + SdMmcMmcSdr50,
> + SdMmcMmcSdr25,
> + SdMmcMmcSdr12,
> + SdMmcMmcHs200,
> + SdMmcMmcHs400,
> +} SD_MMC_UHS_TIMING;
> +
Here, we end up with two sets of symbolic constants for the same
thing, and I suppose this enum will be duplicated in your
SdMmcOverride implementation?
> +//
> // The transfer modes supported by SD Host Controller
> // Simplified Spec 3.0 Table 1-2
> //
> @@ -508,4 +541,21 @@ SdMmcHcInitTimeoutCtrl (
> IN UINT8 Slot
> );
>
> +/**
> + Set SD Host Controler control 2 registry according to selected speed.
> +
> + @param[in] PciIo The PCI IO protocol instance.
> + @param[in] Slot The slot number of the SD card to send the command to.
> + @param[in] Timing The timing to select.
> +
> + @retval EFI_SUCCESS The timing is set successfully.
> + @retval Others The timing isn't set successfully.
> +**/
> +EFI_STATUS
> +SdMmcHcUhsSignaling (
> + IN EFI_PCI_IO_PROTOCOL *PciIo,
> + IN UINT8 Slot,
> + IN SD_MMC_UHS_TIMING Timing
> + );
> +
> #endif
> diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> index 178945f..25db98a 100644
> --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> @@ -17,6 +17,7 @@
> #ifndef __SD_MMC_OVERRIDE_H__
> #define __SD_MMC_OVERRIDE_H__
>
> +#include <Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h>
> #include <Protocol/SdMmcPassThru.h>
>
> #define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \
> @@ -31,6 +32,7 @@ typedef enum {
> EdkiiSdMmcResetPost,
> EdkiiSdMmcInitHostPre,
> EdkiiSdMmcInitHostPost,
> + EdkiiSdMmcUhsSignaling,
> } EDKII_SD_MMC_PHASE_TYPE;
>
> /**
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> index c5fd214..05bd4a0 100755
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> @@ -740,10 +740,13 @@ EmmcSwitchToHighSpeed (
> IN UINT8 BusWidth
> )
> {
> - EFI_STATUS Status;
> - UINT8 HsTiming;
> - UINT8 HostCtrl1;
> - UINT8 HostCtrl2;
> + EFI_STATUS Status;
> + UINT8 HsTiming;
> + UINT8 HostCtrl1;
> + SD_MMC_UHS_TIMING Timing;
> + SD_MMC_HC_PRIVATE_DATA *Private;
> +
> + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
>
> Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusWidth);
> if (EFI_ERROR (Status)) {
> @@ -758,27 +761,37 @@ EmmcSwitchToHighSpeed (
> return Status;
> }
>
> - //
> - // Clean UHS Mode Select field of Host Control 2 reigster before update
> - //
> - HostCtrl2 = (UINT8)~0x7;
> - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> - }
> - //
> - // Set UHS Mode Select field of Host Control 2 reigster to SDR12/25/50
> - //
> if (IsDdr) {
> - HostCtrl2 = BIT2;
> + Timing = SdMmcMmcDdr52;
> } else if (ClockFreq == 52) {
> - HostCtrl2 = BIT0;
> + Timing = SdMmcMmcSdr50;
> + } else if (ClockFreq == 26) {
> + Timing = SdMmcMmcSdr25;
> } else {
> - HostCtrl2 = 0;
> + Timing = SdMmcMmcSdr12;
> }
> - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> +
> + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> + Status = mOverride->NotifyPhase (
> + Private->ControllerHandle,
> + Slot,
> + EdkiiSdMmcUhsSignaling,
> + &Timing
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> + __FUNCTION__,
> + Status
> + ));
> + return Status;
> + }
> + } else {
> + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> }
>
> HsTiming = 1;
> @@ -814,10 +827,13 @@ EmmcSwitchToHS200 (
> IN UINT8 BusWidth
> )
> {
> - EFI_STATUS Status;
> - UINT8 HsTiming;
> - UINT8 HostCtrl2;
> - UINT16 ClockCtrl;
> + EFI_STATUS Status;
> + UINT8 HsTiming;
> + UINT16 ClockCtrl;
> + SD_MMC_UHS_TIMING Timing;
> + SD_MMC_HC_PRIVATE_DATA *Private;
> +
> + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
>
> if ((BusWidth != 4) && (BusWidth != 8)) {
> return EFI_INVALID_PARAMETER;
> @@ -837,21 +853,30 @@ EmmcSwitchToHS200 (
> if (EFI_ERROR (Status)) {
> return Status;
> }
> - //
> - // Clean UHS Mode Select field of Host Control 2 reigster before update
> - //
> - HostCtrl2 = (UINT8)~0x7;
> - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> - }
> - //
> - // Set UHS Mode Select field of Host Control 2 reigster to SDR104
> - //
> - HostCtrl2 = BIT0 | BIT1;
> - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> +
> + Timing = SdMmcMmcHs200;
> +
> + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> + Status = mOverride->NotifyPhase (
> + Private->ControllerHandle,
> + Slot,
> + EdkiiSdMmcUhsSignaling,
> + &Timing
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> + __FUNCTION__,
> + Status
> + ));
> + return Status;
> + }
> + } else {
> + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> }
> //
> // Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit
> @@ -910,9 +935,12 @@ EmmcSwitchToHS400 (
> IN UINT32 ClockFreq
> )
> {
> - EFI_STATUS Status;
> - UINT8 HsTiming;
> - UINT8 HostCtrl2;
> + EFI_STATUS Status;
> + UINT8 HsTiming;
> + SD_MMC_UHS_TIMING Timing;
> + SD_MMC_HC_PRIVATE_DATA *Private;
> +
> + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
>
> Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, ClockFreq, 8);
> if (EFI_ERROR (Status)) {
> @@ -933,21 +961,30 @@ EmmcSwitchToHS400 (
> if (EFI_ERROR (Status)) {
> return Status;
> }
> - //
> - // Clean UHS Mode Select field of Host Control 2 reigster before update
> - //
> - HostCtrl2 = (UINT8)~0x7;
> - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> - }
> - //
> - // Set UHS Mode Select field of Host Control 2 reigster to HS400
> - //
> - HostCtrl2 = BIT0 | BIT2;
> - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> +
> + Timing = SdMmcMmcHs400;
> +
> + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> + Status = mOverride->NotifyPhase (
> + Private->ControllerHandle,
> + Slot,
> + EdkiiSdMmcUhsSignaling,
> + &Timing
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> + __FUNCTION__,
> + Status
> + ));
> + return Status;
> + }
> + } else {
> + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> }
>
> HsTiming = 3;
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> index 8c93933..5645a71 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> @@ -784,8 +784,8 @@ SdCardSetBusMode (
> UINT8 BusWidth;
> UINT8 AccessMode;
> UINT8 HostCtrl1;
> - UINT8 HostCtrl2;
> UINT8 SwitchResp[64];
> + SD_MMC_UHS_TIMING Timing;
> SD_MMC_HC_PRIVATE_DATA *Private;
>
> Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> @@ -817,18 +817,23 @@ SdCardSetBusMode (
> if (S18A && (Capability->Sdr104 != 0) && ((SwitchResp[13] & BIT3) != 0)) {
> ClockFreq = 208;
> AccessMode = 3;
> + Timing = SdMmcUhsSdr104;
> } else if (S18A && (Capability->Sdr50 != 0) && ((SwitchResp[13] & BIT2) != 0)) {
> ClockFreq = 100;
> AccessMode = 2;
> + Timing = SdMmcUhsSdr50;
> } else if (S18A && (Capability->Ddr50 != 0) && ((SwitchResp[13] & BIT4) != 0)) {
> ClockFreq = 50;
> AccessMode = 4;
> + Timing = SdMmcUhsDdr50;
> } else if ((SwitchResp[13] & BIT1) != 0) {
> ClockFreq = 50;
> AccessMode = 1;
> + Timing = SdMmcUhsSdr25;
> } else {
> ClockFreq = 25;
> AccessMode = 0;
> + Timing = SdMmcUhsSdr12;
> }
>
> Status = SdCardSwitch (PassThru, Slot, AccessMode, 0xF, 0xF, 0xF, TRUE, SwitchResp);
> @@ -854,15 +859,27 @@ SdCardSetBusMode (
> }
> }
>
> - HostCtrl2 = (UINT8)~0x7;
> - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> - }
> - HostCtrl2 = AccessMode;
> - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> + Status = mOverride->NotifyPhase (
> + Private->ControllerHandle,
> + Slot,
> + EdkiiSdMmcUhsSignaling,
> + &Timing
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> + __FUNCTION__,
> + Status
> + ));
> + return Status;
> + }
> + } else {
> + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> }
>
> Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capability);
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> index 02eb4ad..38d6202 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> @@ -1137,6 +1137,75 @@ SdMmcHcInitHost (
> }
>
> /**
> + Set SD Host Controler control 2 registry according to selected speed.
> +
> + @param[in] PciIo The PCI IO protocol instance.
> + @param[in] Slot The slot number of the SD card to send the command to.
> + @param[in] Timing The timing to select.
> +
> + @retval EFI_SUCCESS The timing is set successfully.
> + @retval Others The timing isn't set successfully.
> +**/
> +EFI_STATUS
> +SdMmcHcUhsSignaling (
> + IN EFI_PCI_IO_PROTOCOL *PciIo,
> + IN UINT8 Slot,
> + IN SD_MMC_UHS_TIMING Timing
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 HostCtrl2;
> +
> + HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;
> + Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + switch (Timing) {
> + case SdMmcUhsSdr12:
> + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;
> + break;
> + case SdMmcUhsSdr25:
> + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;
> + break;
> + case SdMmcUhsSdr50:
> + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;
> + break;
> + case SdMmcUhsSdr104:
> + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;
> + break;
> + case SdMmcUhsDdr50:
> + HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;
> + break;
> + case SdMmcMmcDdr52:
> + HostCtrl2 = SD_MMC_HC_CTRL_MMC_DDR52;
> + break;
> + case SdMmcMmcSdr50:
> + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR50;
> + break;
> + case SdMmcMmcSdr25:
> + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR25;
> + break;
> + case SdMmcMmcSdr12:
> + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR12;
> + break;
> + case SdMmcMmcHs200:
> + HostCtrl2 = SD_MMC_HC_CTRL_HS200;
> + break;
> + case SdMmcMmcHs400:
> + HostCtrl2 = SD_MMC_HC_CTRL_HS400;
> + break;
> + default:
> + HostCtrl2 = 0;
> + break;
> + }
> + Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> +
> + return Status;
> +}
> +
This function looks identical to the override that your are proposing
in your platform code. Why is that? Are the values of those defines
different?
> +/**
> Turn on/off LED.
>
> @param[in] PciIo The PCI IO protocol instance.
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 3/4] MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to SdMmcOverride
2018-10-05 13:25 ` [PATCH v2 3/4] MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to SdMmcOverride Marcin Wojtas
@ 2018-10-08 12:44 ` Ard Biesheuvel
2018-11-01 7:06 ` Wu, Hao A
1 sibling, 0 replies; 47+ messages in thread
From: Ard Biesheuvel @ 2018-10-08 12:44 UTC (permalink / raw)
To: Marcin Wojtas, Zeng, Star, Eric Dong, Ruiyu Ni
Cc: edk2-devel@lists.01.org, Tian, Feng, Kinney, Michael D,
Gao, Liming, Leif Lindholm, Wu, Hao A, Nadav Haklai,
Jan Dąbroś, Tomasz Michalec
(add MdeModulePkg maintainers)
On 5 October 2018 at 15:25, Marcin Wojtas <mw@semihalf.com> wrote:
> From: Tomasz Michalec <tm@semihalf.com>
>
> Some SD Host Controlers need to do additional opperations after clock
> frequency switch.
>
controllers
operations
Otherwise, this looks fine to me
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> This patch add new callback type to NotifyPhase of the SdMmcOverride
> protocol. It is called after EmmcSwitchClockFreq and SdMmcHcClockSupply.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
> MdeModulePkg/Include/Protocol/SdMmcOverride.h | 1 +
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 60 ++++++++++++++++++++
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 18 ++++++
> 3 files changed, 79 insertions(+)
>
> diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> index 25db98a..d9daada 100644
> --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> @@ -33,6 +33,7 @@ typedef enum {
> EdkiiSdMmcInitHostPre,
> EdkiiSdMmcInitHostPost,
> EdkiiSdMmcUhsSignaling,
> + EdkiiSdMmcSwitchClockFreqPost,
> } EDKII_SD_MMC_PHASE_TYPE;
>
> /**
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> index 05bd4a0..7e75283 100755
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> @@ -796,6 +796,27 @@ EmmcSwitchToHighSpeed (
>
> HsTiming = 1;
> Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, ClockFreq);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> + Status = mOverride->NotifyPhase (
> + Private->ControllerHandle,
> + Slot,
> + EdkiiSdMmcSwitchClockFreqPost,
> + &Timing
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
> + __FUNCTION__,
> + Status
> + ));
> + return Status;
> + }
> + }
>
> return Status;
> }
> @@ -905,6 +926,24 @@ EmmcSwitchToHS200 (
> return Status;
> }
>
> + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> + Status = mOverride->NotifyPhase (
> + Private->ControllerHandle,
> + Slot,
> + EdkiiSdMmcSwitchClockFreqPost,
> + &Timing
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
> + __FUNCTION__,
> + Status
> + ));
> + return Status;
> + }
> + }
> +
> Status = EmmcTuningClkForHs200 (PciIo, PassThru, Slot, BusWidth);
>
> return Status;
> @@ -989,6 +1028,27 @@ EmmcSwitchToHS400 (
>
> HsTiming = 3;
> Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming, ClockFreq);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> + Status = mOverride->NotifyPhase (
> + Private->ControllerHandle,
> + Slot,
> + EdkiiSdMmcSwitchClockFreqPost,
> + &Timing
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
> + __FUNCTION__,
> + Status
> + ));
> + return Status;
> + }
> + }
>
> return Status;
> }
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> index 5645a71..057a4e2 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> @@ -887,6 +887,24 @@ SdCardSetBusMode (
> return Status;
> }
>
> + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> + Status = mOverride->NotifyPhase (
> + Private->ControllerHandle,
> + Slot,
> + EdkiiSdMmcSwitchClockFreqPost,
> + &Timing
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
> + __FUNCTION__,
> + Status
> + ));
> + return Status;
> + }
> + }
> +
> if ((AccessMode == 3) || ((AccessMode == 2) && (Capability->TuningSDR50 != 0))) {
> Status = SdCardTuningClock (PciIo, PassThru, Slot);
> if (EFI_ERROR (Status)) {
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 4/4] MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequency
2018-10-05 13:25 ` [PATCH v2 4/4] MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequency Marcin Wojtas
@ 2018-10-08 12:49 ` Ard Biesheuvel
2018-11-01 7:11 ` Wu, Hao A
1 sibling, 0 replies; 47+ messages in thread
From: Ard Biesheuvel @ 2018-10-08 12:49 UTC (permalink / raw)
To: Marcin Wojtas, Zeng, Star, Eric Dong, Ruiyu Ni
Cc: edk2-devel@lists.01.org, Tian, Feng, Kinney, Michael D,
Gao, Liming, Leif Lindholm, Wu, Hao A, Nadav Haklai,
Jan Dąbroś, Tomasz Michalec
(add MdeModulePkg maintainers)
On 5 October 2018 at 15:25, Marcin Wojtas <mw@semihalf.com> wrote:
> Some SdMmc host controllers are run by clocks with different
> frequency than it is reflected in Capabilities Register 1.
> It is allowed by SDHCI specification ver. 4.2 - if BaseClkFreq
> field value of the Capability Register 1 is zero, the clock
> frequency must be obtained via another method.
>
> Because the bitfield is only 8 bits wide, a maximum value
> that could be obtained from hardware is 255MHz.
> In case the actual frequency exceeds 255MHz, the 8-bit BaseClkFreq
> member of SD_MMC_HC_SLOT_CAP structure occurs to be not sufficient
> to be used for setting the clock speed in SdMmcHcClockSupply
> function.
>
> This patch adds new UINT32 array ('BaseClkFreq[]') to
> SD_MMC_HC_PRIVATE_DATA structure for specifying
> the input clock speed for each slot of the host controller.
> All routines that are used for clock configuration are
> updated accordingly.
>
> This patch also adds new IN OUT BaseClockFreq field
> in the Capability callback of the SdMmcOverride,
> protocol which allows to update BaseClkFreq value.
>
> The patch reuses original commit from edk2-platforms:
> 20f6f144d3a8 ("Marvell/Drivers: XenonDxe: Allow overriding base clock
> frequency")
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 6 +++++
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 12 +++++----
> MdeModulePkg/Include/Protocol/SdMmcOverride.h | 5 +++-
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 4 +--
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 4 +--
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 18 +++++++++++--
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 27 +++++++++++---------
> 7 files changed, 52 insertions(+), 24 deletions(-)
>
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> index c683600..8c1a589 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> @@ -118,6 +118,12 @@ typedef struct {
> UINT64 MaxCurrent[SD_MMC_HC_MAX_SLOT];
>
> UINT32 ControllerVersion;
> +
> + //
> + // Some controllers may require to override base clock frequency
> + // value stored in Capabilities Register 1.
> + //
> + UINT32 BaseClkFreq[SD_MMC_HC_MAX_SLOT];
> } SD_MMC_HC_PRIVATE_DATA;
>
> #define SD_MMC_HC_TRB_SIG SIGNATURE_32 ('T', 'R', 'B', 'T')
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> index a03160d..f01ba21 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> @@ -173,12 +173,14 @@ typedef struct {
>
> @param[in] Slot The slot number of the SD card to send the command to.
> @param[in] Capability The buffer to store the capability data.
> + @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
>
> **/
> VOID
> DumpCapabilityReg (
> IN UINT8 Slot,
> - IN SD_MMC_HC_SLOT_CAP *Capability
> + IN SD_MMC_HC_SLOT_CAP *Capability,
> + IN UINT32 BaseClkFreq
> );
>
> /**
> @@ -431,7 +433,7 @@ SdMmcHcStopClock (
> @param[in] PciIo The PCI IO protocol instance.
> @param[in] Slot The slot number of the SD card to send the command to.
> @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
> - @param[in] Capability The capability of the slot.
> + @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
>
> @retval EFI_SUCCESS The clock is supplied successfully.
> @retval Others The clock isn't supplied successfully.
> @@ -442,7 +444,7 @@ SdMmcHcClockSupply (
> IN EFI_PCI_IO_PROTOCOL *PciIo,
> IN UINT8 Slot,
> IN UINT64 ClockFreq,
> - IN SD_MMC_HC_SLOT_CAP Capability
> + IN UINT32 BaseClkFreq
> );
>
> /**
> @@ -490,7 +492,7 @@ SdMmcHcSetBusWidth (
>
> @param[in] PciIo The PCI IO protocol instance.
> @param[in] Slot The slot number of the SD card to send the command to.
> - @param[in] Capability The capability of the slot.
> + @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
>
> @retval EFI_SUCCESS The clock is supplied successfully.
> @retval Others The clock isn't supplied successfully.
> @@ -500,7 +502,7 @@ EFI_STATUS
> SdMmcHcInitClockFreq (
> IN EFI_PCI_IO_PROTOCOL *PciIo,
> IN UINT8 Slot,
> - IN SD_MMC_HC_SLOT_CAP Capability
> + IN UINT32 BaseClkFreq
> );
>
> /**
> diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> index d9daada..27023d3 100644
> --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> @@ -43,6 +43,8 @@ typedef enum {
> @param[in] ControllerHandle The EFI_HANDLE of the controller.
> @param[in] Slot The 0 based slot index.
> @param[in,out] SdMmcHcSlotCapability The SDHCI capability structure.
> + @param[in,out] BaseClkFreq The base clock frequency value that
> + optionally can be updated.
>
> @retval EFI_SUCCESS The override function completed successfully.
> @retval EFI_NOT_FOUND The specified controller or slot does not exist.
> @@ -54,7 +56,8 @@ EFI_STATUS
> (EFIAPI * EDKII_SD_MMC_CAPABILITY) (
> IN EFI_HANDLE ControllerHandle,
> IN UINT8 Slot,
> - IN OUT VOID *SdMmcHcSlotCapability
> + IN OUT VOID *SdMmcHcSlotCapability,
> + IN OUT UINT32 *BaseClkFreq
> );
>
> /**
Please bump the version number for this interface change. (just update
the define, don't add new ones)
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> index 7e75283..27ccd63 100755
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> @@ -705,7 +705,7 @@ EmmcSwitchClockFreq (
> //
> // Convert the clock freq unit from MHz to KHz.
> //
> - Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->Capability[Slot]);
> + Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->BaseClkFreq[Slot]);
>
> return Status;
> }
> @@ -1099,7 +1099,7 @@ EmmcSetBusMode (
> return Status;
> }
>
> - ASSERT (Private->Capability[Slot].BaseClkFreq != 0);
> + ASSERT (Private->BaseClkFreq[Slot] != 0);
> //
> // Check if the Host Controller support 8bits bus width.
> //
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> index 057a4e2..9ea13be 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> @@ -882,7 +882,7 @@ SdCardSetBusMode (
> }
> }
>
> - Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capability);
> + Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->BaseClkFreq[Slot]);
> if (EFI_ERROR (Status)) {
> return Status;
> }
> @@ -1081,7 +1081,7 @@ SdCardIdentification (
> goto Error;
> }
>
> - SdMmcHcInitClockFreq (PciIo, Slot, Private->Capability[Slot]);
> + SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot]);
>
> gBS->Stall (1000);
>
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
> index bf9869d..d7cc0ce 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
> @@ -625,18 +625,32 @@ SdMmcPciHcDriverBindingStart (
> if (EFI_ERROR (Status)) {
> continue;
> }
> +
> + Private->BaseClkFreq[Slot] = Private->Capability[Slot].BaseClkFreq;
> +
> if (mOverride != NULL && mOverride->Capability != NULL) {
> Status = mOverride->Capability (
> Controller,
> Slot,
> - &Private->Capability[Slot]);
> + &Private->Capability[Slot],
> + &Private->BaseClkFreq[Slot]
> + );
> if (EFI_ERROR (Status)) {
> DEBUG ((DEBUG_WARN, "%a: Failed to override capability - %r\n",
> __FUNCTION__, Status));
> continue;
> }
> }
> - DumpCapabilityReg (Slot, &Private->Capability[Slot]);
> +
> + //
> + // According to SDHCI specification ver. 4.2, BaseClkFreq field value of
> + // the Capability Register 1 can be zero, which means a need for obtaining
> + // the clock frequency via another method. Fail in case it is not updated
> + // by SW at this point.
> + //
> + ASSERT (Private->BaseClkFreq[Slot] != 0);
> +
> + DumpCapabilityReg (Slot, &Private->Capability[Slot], Private->BaseClkFreq[Slot]);
>
> Support64BitDma &= Private->Capability[Slot].SysBus64;
>
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> index 38d6202..9f50754 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> @@ -22,12 +22,14 @@
>
> @param[in] Slot The slot number of the SD card to send the command to.
> @param[in] Capability The buffer to store the capability data.
> + @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
>
> **/
> VOID
> DumpCapabilityReg (
> IN UINT8 Slot,
> - IN SD_MMC_HC_SLOT_CAP *Capability
> + IN SD_MMC_HC_SLOT_CAP *Capability,
> + IN UINT32 BaseClkFreq
> )
> {
> //
> @@ -35,7 +37,10 @@ DumpCapabilityReg (
> //
> DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot, Capability));
> DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability->TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));
> - DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability->BaseClkFreq));
> + if (Capability->BaseClkFreq != BaseClkFreq) {
> + DEBUG ((DEBUG_INFO, " Controller register value overriden:\n"));
'overridden'
However, could we just dump both values unconditionally?
> + }
> + DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", BaseClkFreq));
> DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 << Capability->MaxBlkLen)));
> DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ? "TRUE" : "FALSE"));
> DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ? "TRUE" : "FALSE"));
> @@ -721,7 +726,7 @@ SdMmcHcStopClock (
> @param[in] PciIo The PCI IO protocol instance.
> @param[in] Slot The slot number of the SD card to send the command to.
> @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
> - @param[in] Capability The capability of the slot.
> + @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
>
> @retval EFI_SUCCESS The clock is supplied successfully.
> @retval Others The clock isn't supplied successfully.
> @@ -732,11 +737,10 @@ SdMmcHcClockSupply (
> IN EFI_PCI_IO_PROTOCOL *PciIo,
> IN UINT8 Slot,
> IN UINT64 ClockFreq,
> - IN SD_MMC_HC_SLOT_CAP Capability
> + IN UINT32 BaseClkFreq
> )
> {
> EFI_STATUS Status;
> - UINT32 BaseClkFreq;
> UINT32 SettingFreq;
> UINT32 Divisor;
> UINT32 Remainder;
> @@ -746,9 +750,8 @@ SdMmcHcClockSupply (
> //
> // Calculate a divisor for SD clock frequency
> //
> - ASSERT (Capability.BaseClkFreq != 0);
> + ASSERT (BaseClkFreq != 0);
>
> - BaseClkFreq = Capability.BaseClkFreq;
> if (ClockFreq == 0) {
> return EFI_INVALID_PARAMETER;
> }
> @@ -939,7 +942,7 @@ SdMmcHcSetBusWidth (
>
> @param[in] PciIo The PCI IO protocol instance.
> @param[in] Slot The slot number of the SD card to send the command to.
> - @param[in] Capability The capability of the slot.
> + @param[in] BaseClkFreq The base clock frequency of host controller in MHz.
>
> @retval EFI_SUCCESS The clock is supplied successfully.
> @retval Others The clock isn't supplied successfully.
> @@ -949,7 +952,7 @@ EFI_STATUS
> SdMmcHcInitClockFreq (
> IN EFI_PCI_IO_PROTOCOL *PciIo,
> IN UINT8 Slot,
> - IN SD_MMC_HC_SLOT_CAP Capability
> + IN UINT32 BaseClkFreq
> )
> {
> EFI_STATUS Status;
> @@ -958,7 +961,7 @@ SdMmcHcInitClockFreq (
> //
> // Calculate a divisor for SD clock frequency
> //
> - if (Capability.BaseClkFreq == 0) {
> + if (BaseClkFreq == 0) {
> //
> // Don't support get Base Clock Frequency information via another method
> //
> @@ -968,7 +971,7 @@ SdMmcHcInitClockFreq (
> // Supply 400KHz clock frequency at initialization phase.
> //
> InitFreq = 400;
> - Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, Capability);
> + Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, BaseClkFreq);
> return Status;
> }
>
> @@ -1102,7 +1105,7 @@ SdMmcHcInitHost (
> PciIo = Private->PciIo;
> Capability = Private->Capability[Slot];
>
> - Status = SdMmcHcInitClockFreq (PciIo, Slot, Capability);
> + Status = SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot]);
> if (EFI_ERROR (Status)) {
> return Status;
> }
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-08 12:41 ` Ard Biesheuvel
@ 2018-10-08 12:59 ` Marcin Wojtas
2018-10-08 13:07 ` Ard Biesheuvel
0 siblings, 1 reply; 47+ messages in thread
From: Marcin Wojtas @ 2018-10-08 12:59 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: Zeng, Star, eric.dong, Ni, Ruiyu, edk2-devel-01, Tian, Feng,
Kinney, Michael D, Gao, Liming, Leif Lindholm, hao.a.wu, nadavh,
jsd@semihalf.com, Tomasz Michalec
Hi Ard,
pon., 8 paź 2018 o 14:41 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
>
> (add MdeModulePkg maintainers)
>
> On 5 October 2018 at 15:25, Marcin Wojtas <mw@semihalf.com> wrote:
> > From: Tomasz Michalec <tm@semihalf.com>
> >
> > Some SD Host Controlers use different values in Host Control 2 Register
> > to select UHS Mode. This patch adds a new UhsSignaling type routine to
> > the NotifyPhase of the SdMmcOverride protocol.
> >
> > UHS signaling configuration is moved to a common, default routine
> > (SdMmcHcUhsSignaling), which is called when SdMmcOverride does not
> > cover this functionality.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> > ---
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 50 +++++++
> > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 2 +
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 153 ++++++++++++--------
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 37 +++--
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 69 +++++++++
> > 5 files changed, 243 insertions(+), 68 deletions(-)
> >
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > index e389d52..a03160d 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > @@ -63,6 +63,39 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> > #define SD_MMC_HC_CTRL_VER 0xFE
> >
> > //
> > +// SD Host Controler bits to HOST_CTRL2 register
> > +//
> > +#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
> > +#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
> > +#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
> > +#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
> > +#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
> > +#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
> > +#define SD_MMC_HC_CTRL_MMC_DDR52 0x0004
> > +#define SD_MMC_HC_CTRL_MMC_SDR50 0x0002
> > +#define SD_MMC_HC_CTRL_MMC_SDR25 0x0001
> > +#define SD_MMC_HC_CTRL_MMC_SDR12 0x0000
> > +#define SD_MMC_HC_CTRL_HS200 0x0003
> > +#define SD_MMC_HC_CTRL_HS400 0x0005
> > +
> > +//
> > +// Timing modes for uhs
> > +//
> > +typedef enum {
> > + SdMmcUhsSdr12,
> > + SdMmcUhsSdr25,
> > + SdMmcUhsSdr50,
> > + SdMmcUhsSdr104,
> > + SdMmcUhsDdr50,
> > + SdMmcMmcDdr52,
> > + SdMmcMmcSdr50,
> > + SdMmcMmcSdr25,
> > + SdMmcMmcSdr12,
> > + SdMmcMmcHs200,
> > + SdMmcMmcHs400,
> > +} SD_MMC_UHS_TIMING;
> > +
>
> Here, we end up with two sets of symbolic constants for the same
> thing, and I suppose this enum will be duplicated in your
> SdMmcOverride implementation?
>
Why duplicated? Macros are for generic UHS_MODE_SEL field values for
SD and MMC in HostControl2Register.
SD_MMC_UHS_TIMING is just a timing mode indicator, it can be used not
only in UhsSignaling routine (actually the next patch, with
SwitchClockFreqPost, use it...).
In my SdMmcOverride implementation this enum is not duplicated,
because this file (SdMmcPciHci.h) is included via
Protocol/SdMmcOverride.h.
>
>
> > +//
> > // The transfer modes supported by SD Host Controller
> > // Simplified Spec 3.0 Table 1-2
> > //
> > @@ -508,4 +541,21 @@ SdMmcHcInitTimeoutCtrl (
> > IN UINT8 Slot
> > );
> >
> > +/**
> > + Set SD Host Controler control 2 registry according to selected speed.
> > +
> > + @param[in] PciIo The PCI IO protocol instance.
> > + @param[in] Slot The slot number of the SD card to send the command to.
> > + @param[in] Timing The timing to select.
> > +
> > + @retval EFI_SUCCESS The timing is set successfully.
> > + @retval Others The timing isn't set successfully.
> > +**/
> > +EFI_STATUS
> > +SdMmcHcUhsSignaling (
> > + IN EFI_PCI_IO_PROTOCOL *PciIo,
> > + IN UINT8 Slot,
> > + IN SD_MMC_UHS_TIMING Timing
> > + );
> > +
> > #endif
> > diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > index 178945f..25db98a 100644
> > --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > @@ -17,6 +17,7 @@
> > #ifndef __SD_MMC_OVERRIDE_H__
> > #define __SD_MMC_OVERRIDE_H__
> >
> > +#include <Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h>
> > #include <Protocol/SdMmcPassThru.h>
> >
> > #define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \
> > @@ -31,6 +32,7 @@ typedef enum {
> > EdkiiSdMmcResetPost,
> > EdkiiSdMmcInitHostPre,
> > EdkiiSdMmcInitHostPost,
> > + EdkiiSdMmcUhsSignaling,
> > } EDKII_SD_MMC_PHASE_TYPE;
> >
> > /**
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > index c5fd214..05bd4a0 100755
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > @@ -740,10 +740,13 @@ EmmcSwitchToHighSpeed (
> > IN UINT8 BusWidth
> > )
> > {
> > - EFI_STATUS Status;
> > - UINT8 HsTiming;
> > - UINT8 HostCtrl1;
> > - UINT8 HostCtrl2;
> > + EFI_STATUS Status;
> > + UINT8 HsTiming;
> > + UINT8 HostCtrl1;
> > + SD_MMC_UHS_TIMING Timing;
> > + SD_MMC_HC_PRIVATE_DATA *Private;
> > +
> > + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> >
> > Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusWidth);
> > if (EFI_ERROR (Status)) {
> > @@ -758,27 +761,37 @@ EmmcSwitchToHighSpeed (
> > return Status;
> > }
> >
> > - //
> > - // Clean UHS Mode Select field of Host Control 2 reigster before update
> > - //
> > - HostCtrl2 = (UINT8)~0x7;
> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> > - if (EFI_ERROR (Status)) {
> > - return Status;
> > - }
> > - //
> > - // Set UHS Mode Select field of Host Control 2 reigster to SDR12/25/50
> > - //
> > if (IsDdr) {
> > - HostCtrl2 = BIT2;
> > + Timing = SdMmcMmcDdr52;
> > } else if (ClockFreq == 52) {
> > - HostCtrl2 = BIT0;
> > + Timing = SdMmcMmcSdr50;
> > + } else if (ClockFreq == 26) {
> > + Timing = SdMmcMmcSdr25;
> > } else {
> > - HostCtrl2 = 0;
> > + Timing = SdMmcMmcSdr12;
> > }
> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> > - if (EFI_ERROR (Status)) {
> > - return Status;
> > +
> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> > + Status = mOverride->NotifyPhase (
> > + Private->ControllerHandle,
> > + Slot,
> > + EdkiiSdMmcUhsSignaling,
> > + &Timing
> > + );
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((
> > + DEBUG_ERROR,
> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> > + __FUNCTION__,
> > + Status
> > + ));
> > + return Status;
> > + }
> > + } else {
> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > }
> >
> > HsTiming = 1;
> > @@ -814,10 +827,13 @@ EmmcSwitchToHS200 (
> > IN UINT8 BusWidth
> > )
> > {
> > - EFI_STATUS Status;
> > - UINT8 HsTiming;
> > - UINT8 HostCtrl2;
> > - UINT16 ClockCtrl;
> > + EFI_STATUS Status;
> > + UINT8 HsTiming;
> > + UINT16 ClockCtrl;
> > + SD_MMC_UHS_TIMING Timing;
> > + SD_MMC_HC_PRIVATE_DATA *Private;
> > +
> > + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> >
> > if ((BusWidth != 4) && (BusWidth != 8)) {
> > return EFI_INVALID_PARAMETER;
> > @@ -837,21 +853,30 @@ EmmcSwitchToHS200 (
> > if (EFI_ERROR (Status)) {
> > return Status;
> > }
> > - //
> > - // Clean UHS Mode Select field of Host Control 2 reigster before update
> > - //
> > - HostCtrl2 = (UINT8)~0x7;
> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> > - if (EFI_ERROR (Status)) {
> > - return Status;
> > - }
> > - //
> > - // Set UHS Mode Select field of Host Control 2 reigster to SDR104
> > - //
> > - HostCtrl2 = BIT0 | BIT1;
> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> > - if (EFI_ERROR (Status)) {
> > - return Status;
> > +
> > + Timing = SdMmcMmcHs200;
> > +
> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> > + Status = mOverride->NotifyPhase (
> > + Private->ControllerHandle,
> > + Slot,
> > + EdkiiSdMmcUhsSignaling,
> > + &Timing
> > + );
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((
> > + DEBUG_ERROR,
> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> > + __FUNCTION__,
> > + Status
> > + ));
> > + return Status;
> > + }
> > + } else {
> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > }
> > //
> > // Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit
> > @@ -910,9 +935,12 @@ EmmcSwitchToHS400 (
> > IN UINT32 ClockFreq
> > )
> > {
> > - EFI_STATUS Status;
> > - UINT8 HsTiming;
> > - UINT8 HostCtrl2;
> > + EFI_STATUS Status;
> > + UINT8 HsTiming;
> > + SD_MMC_UHS_TIMING Timing;
> > + SD_MMC_HC_PRIVATE_DATA *Private;
> > +
> > + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> >
> > Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, ClockFreq, 8);
> > if (EFI_ERROR (Status)) {
> > @@ -933,21 +961,30 @@ EmmcSwitchToHS400 (
> > if (EFI_ERROR (Status)) {
> > return Status;
> > }
> > - //
> > - // Clean UHS Mode Select field of Host Control 2 reigster before update
> > - //
> > - HostCtrl2 = (UINT8)~0x7;
> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> > - if (EFI_ERROR (Status)) {
> > - return Status;
> > - }
> > - //
> > - // Set UHS Mode Select field of Host Control 2 reigster to HS400
> > - //
> > - HostCtrl2 = BIT0 | BIT2;
> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> > - if (EFI_ERROR (Status)) {
> > - return Status;
> > +
> > + Timing = SdMmcMmcHs400;
> > +
> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> > + Status = mOverride->NotifyPhase (
> > + Private->ControllerHandle,
> > + Slot,
> > + EdkiiSdMmcUhsSignaling,
> > + &Timing
> > + );
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((
> > + DEBUG_ERROR,
> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> > + __FUNCTION__,
> > + Status
> > + ));
> > + return Status;
> > + }
> > + } else {
> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > }
> >
> > HsTiming = 3;
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > index 8c93933..5645a71 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > @@ -784,8 +784,8 @@ SdCardSetBusMode (
> > UINT8 BusWidth;
> > UINT8 AccessMode;
> > UINT8 HostCtrl1;
> > - UINT8 HostCtrl2;
> > UINT8 SwitchResp[64];
> > + SD_MMC_UHS_TIMING Timing;
> > SD_MMC_HC_PRIVATE_DATA *Private;
> >
> > Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> > @@ -817,18 +817,23 @@ SdCardSetBusMode (
> > if (S18A && (Capability->Sdr104 != 0) && ((SwitchResp[13] & BIT3) != 0)) {
> > ClockFreq = 208;
> > AccessMode = 3;
> > + Timing = SdMmcUhsSdr104;
> > } else if (S18A && (Capability->Sdr50 != 0) && ((SwitchResp[13] & BIT2) != 0)) {
> > ClockFreq = 100;
> > AccessMode = 2;
> > + Timing = SdMmcUhsSdr50;
> > } else if (S18A && (Capability->Ddr50 != 0) && ((SwitchResp[13] & BIT4) != 0)) {
> > ClockFreq = 50;
> > AccessMode = 4;
> > + Timing = SdMmcUhsDdr50;
> > } else if ((SwitchResp[13] & BIT1) != 0) {
> > ClockFreq = 50;
> > AccessMode = 1;
> > + Timing = SdMmcUhsSdr25;
> > } else {
> > ClockFreq = 25;
> > AccessMode = 0;
> > + Timing = SdMmcUhsSdr12;
> > }
> >
> > Status = SdCardSwitch (PassThru, Slot, AccessMode, 0xF, 0xF, 0xF, TRUE, SwitchResp);
> > @@ -854,15 +859,27 @@ SdCardSetBusMode (
> > }
> > }
> >
> > - HostCtrl2 = (UINT8)~0x7;
> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> > - if (EFI_ERROR (Status)) {
> > - return Status;
> > - }
> > - HostCtrl2 = AccessMode;
> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> > - if (EFI_ERROR (Status)) {
> > - return Status;
> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> > + Status = mOverride->NotifyPhase (
> > + Private->ControllerHandle,
> > + Slot,
> > + EdkiiSdMmcUhsSignaling,
> > + &Timing
> > + );
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((
> > + DEBUG_ERROR,
> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> > + __FUNCTION__,
> > + Status
> > + ));
> > + return Status;
> > + }
> > + } else {
> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > }
> >
> > Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capability);
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > index 02eb4ad..38d6202 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > @@ -1137,6 +1137,75 @@ SdMmcHcInitHost (
> > }
> >
> > /**
> > + Set SD Host Controler control 2 registry according to selected speed.
> > +
> > + @param[in] PciIo The PCI IO protocol instance.
> > + @param[in] Slot The slot number of the SD card to send the command to.
> > + @param[in] Timing The timing to select.
> > +
> > + @retval EFI_SUCCESS The timing is set successfully.
> > + @retval Others The timing isn't set successfully.
> > +**/
> > +EFI_STATUS
> > +SdMmcHcUhsSignaling (
> > + IN EFI_PCI_IO_PROTOCOL *PciIo,
> > + IN UINT8 Slot,
> > + IN SD_MMC_UHS_TIMING Timing
> > + )
> > +{
> > + EFI_STATUS Status;
> > + UINT8 HostCtrl2;
> > +
> > + HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;
> > + Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > +
> > + switch (Timing) {
> > + case SdMmcUhsSdr12:
> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;
> > + break;
> > + case SdMmcUhsSdr25:
> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;
> > + break;
> > + case SdMmcUhsSdr50:
> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;
> > + break;
> > + case SdMmcUhsSdr104:
> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;
> > + break;
> > + case SdMmcUhsDdr50:
> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;
> > + break;
> > + case SdMmcMmcDdr52:
> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_DDR52;
> > + break;
> > + case SdMmcMmcSdr50:
> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR50;
> > + break;
> > + case SdMmcMmcSdr25:
> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR25;
> > + break;
> > + case SdMmcMmcSdr12:
> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR12;
> > + break;
> > + case SdMmcMmcHs200:
> > + HostCtrl2 = SD_MMC_HC_CTRL_HS200;
> > + break;
> > + case SdMmcMmcHs400:
> > + HostCtrl2 = SD_MMC_HC_CTRL_HS400;
> > + break;
> > + default:
> > + HostCtrl2 = 0;
> > + break;
> > + }
> > + Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> > +
> > + return Status;
> > +}
> > +
>
> This function looks identical to the override that your are proposing
> in your platform code. Why is that? Are the values of those defines
> different?
>
This is exactly the reason. For Xenon, MMC_HS400 and MMC_HS200 values
of UHS_MODE_SEL field in HostControl2Register are custom. Actually,
non-generic UHS_MODE_SEL values are pretty common, from what I can see
in the Linux code. The new callback allows overriding it. Looking
forward to your feedback.
Best regards,
Marcin
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-08 12:59 ` Marcin Wojtas
@ 2018-10-08 13:07 ` Ard Biesheuvel
2018-10-08 13:17 ` Marcin Wojtas
0 siblings, 1 reply; 47+ messages in thread
From: Ard Biesheuvel @ 2018-10-08 13:07 UTC (permalink / raw)
To: Marcin Wojtas
Cc: Zeng, Star, Eric Dong, Ni, Ruiyu, edk2-devel-01, Tian, Feng,
Kinney, Michael D, Gao, Liming, Leif Lindholm, Wu, Hao A,
Nadav Haklai, jsd@semihalf.com, Tomasz Michalec
On 8 October 2018 at 14:59, Marcin Wojtas <mw@semihalf.com> wrote:
> Hi Ard,
>
> pon., 8 paź 2018 o 14:41 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
>>
>> (add MdeModulePkg maintainers)
>>
>> On 5 October 2018 at 15:25, Marcin Wojtas <mw@semihalf.com> wrote:
>> > From: Tomasz Michalec <tm@semihalf.com>
>> >
>> > Some SD Host Controlers use different values in Host Control 2 Register
>> > to select UHS Mode. This patch adds a new UhsSignaling type routine to
>> > the NotifyPhase of the SdMmcOverride protocol.
>> >
>> > UHS signaling configuration is moved to a common, default routine
>> > (SdMmcHcUhsSignaling), which is called when SdMmcOverride does not
>> > cover this functionality.
>> >
>> > Contributed-under: TianoCore Contribution Agreement 1.1
>> > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>> > ---
>> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 50 +++++++
>> > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 2 +
>> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 153 ++++++++++++--------
>> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 37 +++--
>> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 69 +++++++++
>> > 5 files changed, 243 insertions(+), 68 deletions(-)
>> >
>> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
>> > index e389d52..a03160d 100644
>> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
>> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
>> > @@ -63,6 +63,39 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> > #define SD_MMC_HC_CTRL_VER 0xFE
>> >
>> > //
>> > +// SD Host Controler bits to HOST_CTRL2 register
>> > +//
>> > +#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
>> > +#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
>> > +#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
>> > +#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
>> > +#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
>> > +#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
>> > +#define SD_MMC_HC_CTRL_MMC_DDR52 0x0004
>> > +#define SD_MMC_HC_CTRL_MMC_SDR50 0x0002
>> > +#define SD_MMC_HC_CTRL_MMC_SDR25 0x0001
>> > +#define SD_MMC_HC_CTRL_MMC_SDR12 0x0000
>> > +#define SD_MMC_HC_CTRL_HS200 0x0003
>> > +#define SD_MMC_HC_CTRL_HS400 0x0005
>> > +
>> > +//
>> > +// Timing modes for uhs
>> > +//
>> > +typedef enum {
>> > + SdMmcUhsSdr12,
>> > + SdMmcUhsSdr25,
>> > + SdMmcUhsSdr50,
>> > + SdMmcUhsSdr104,
>> > + SdMmcUhsDdr50,
>> > + SdMmcMmcDdr52,
>> > + SdMmcMmcSdr50,
>> > + SdMmcMmcSdr25,
>> > + SdMmcMmcSdr12,
>> > + SdMmcMmcHs200,
>> > + SdMmcMmcHs400,
>> > +} SD_MMC_UHS_TIMING;
>> > +
>>
>> Here, we end up with two sets of symbolic constants for the same
>> thing, and I suppose this enum will be duplicated in your
>> SdMmcOverride implementation?
>>
>
> Why duplicated? Macros are for generic UHS_MODE_SEL field values for
> SD and MMC in HostControl2Register.
>
> SD_MMC_UHS_TIMING is just a timing mode indicator, it can be used not
> only in UhsSignaling routine (actually the next patch, with
> SwitchClockFreqPost, use it...).
>
> In my SdMmcOverride implementation this enum is not duplicated,
> because this file (SdMmcPciHci.h) is included via
> Protocol/SdMmcOverride.h.
>
Ah ok. Please don't expose internal headers of the SD/MMC driver via
Protocol/SdMmcOverride.h
I think it should be fine to add the enum definition to
Protocol/SdMmcOverride.h instead.
But wouldn't it be much easier to have a hook for setting
HostControl2Register that decodes the value and modifies it according
to what the platform requires?
>>
>>
>> > +//
>> > // The transfer modes supported by SD Host Controller
>> > // Simplified Spec 3.0 Table 1-2
>> > //
>> > @@ -508,4 +541,21 @@ SdMmcHcInitTimeoutCtrl (
>> > IN UINT8 Slot
>> > );
>> >
>> > +/**
>> > + Set SD Host Controler control 2 registry according to selected speed.
>> > +
>> > + @param[in] PciIo The PCI IO protocol instance.
>> > + @param[in] Slot The slot number of the SD card to send the command to.
>> > + @param[in] Timing The timing to select.
>> > +
>> > + @retval EFI_SUCCESS The timing is set successfully.
>> > + @retval Others The timing isn't set successfully.
>> > +**/
>> > +EFI_STATUS
>> > +SdMmcHcUhsSignaling (
>> > + IN EFI_PCI_IO_PROTOCOL *PciIo,
>> > + IN UINT8 Slot,
>> > + IN SD_MMC_UHS_TIMING Timing
>> > + );
>> > +
>> > #endif
>> > diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
>> > index 178945f..25db98a 100644
>> > --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
>> > +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
>> > @@ -17,6 +17,7 @@
>> > #ifndef __SD_MMC_OVERRIDE_H__
>> > #define __SD_MMC_OVERRIDE_H__
>> >
>> > +#include <Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h>
>> > #include <Protocol/SdMmcPassThru.h>
>> >
>> > #define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \
>> > @@ -31,6 +32,7 @@ typedef enum {
>> > EdkiiSdMmcResetPost,
>> > EdkiiSdMmcInitHostPre,
>> > EdkiiSdMmcInitHostPost,
>> > + EdkiiSdMmcUhsSignaling,
>> > } EDKII_SD_MMC_PHASE_TYPE;
>> >
>> > /**
>> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
>> > index c5fd214..05bd4a0 100755
>> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
>> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
>> > @@ -740,10 +740,13 @@ EmmcSwitchToHighSpeed (
>> > IN UINT8 BusWidth
>> > )
>> > {
>> > - EFI_STATUS Status;
>> > - UINT8 HsTiming;
>> > - UINT8 HostCtrl1;
>> > - UINT8 HostCtrl2;
>> > + EFI_STATUS Status;
>> > + UINT8 HsTiming;
>> > + UINT8 HostCtrl1;
>> > + SD_MMC_UHS_TIMING Timing;
>> > + SD_MMC_HC_PRIVATE_DATA *Private;
>> > +
>> > + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
>> >
>> > Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusWidth);
>> > if (EFI_ERROR (Status)) {
>> > @@ -758,27 +761,37 @@ EmmcSwitchToHighSpeed (
>> > return Status;
>> > }
>> >
>> > - //
>> > - // Clean UHS Mode Select field of Host Control 2 reigster before update
>> > - //
>> > - HostCtrl2 = (UINT8)~0x7;
>> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
>> > - if (EFI_ERROR (Status)) {
>> > - return Status;
>> > - }
>> > - //
>> > - // Set UHS Mode Select field of Host Control 2 reigster to SDR12/25/50
>> > - //
>> > if (IsDdr) {
>> > - HostCtrl2 = BIT2;
>> > + Timing = SdMmcMmcDdr52;
>> > } else if (ClockFreq == 52) {
>> > - HostCtrl2 = BIT0;
>> > + Timing = SdMmcMmcSdr50;
>> > + } else if (ClockFreq == 26) {
>> > + Timing = SdMmcMmcSdr25;
>> > } else {
>> > - HostCtrl2 = 0;
>> > + Timing = SdMmcMmcSdr12;
>> > }
>> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
>> > - if (EFI_ERROR (Status)) {
>> > - return Status;
>> > +
>> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
>> > + Status = mOverride->NotifyPhase (
>> > + Private->ControllerHandle,
>> > + Slot,
>> > + EdkiiSdMmcUhsSignaling,
>> > + &Timing
>> > + );
>> > + if (EFI_ERROR (Status)) {
>> > + DEBUG ((
>> > + DEBUG_ERROR,
>> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
>> > + __FUNCTION__,
>> > + Status
>> > + ));
>> > + return Status;
>> > + }
>> > + } else {
>> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
>> > + if (EFI_ERROR (Status)) {
>> > + return Status;
>> > + }
>> > }
>> >
>> > HsTiming = 1;
>> > @@ -814,10 +827,13 @@ EmmcSwitchToHS200 (
>> > IN UINT8 BusWidth
>> > )
>> > {
>> > - EFI_STATUS Status;
>> > - UINT8 HsTiming;
>> > - UINT8 HostCtrl2;
>> > - UINT16 ClockCtrl;
>> > + EFI_STATUS Status;
>> > + UINT8 HsTiming;
>> > + UINT16 ClockCtrl;
>> > + SD_MMC_UHS_TIMING Timing;
>> > + SD_MMC_HC_PRIVATE_DATA *Private;
>> > +
>> > + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
>> >
>> > if ((BusWidth != 4) && (BusWidth != 8)) {
>> > return EFI_INVALID_PARAMETER;
>> > @@ -837,21 +853,30 @@ EmmcSwitchToHS200 (
>> > if (EFI_ERROR (Status)) {
>> > return Status;
>> > }
>> > - //
>> > - // Clean UHS Mode Select field of Host Control 2 reigster before update
>> > - //
>> > - HostCtrl2 = (UINT8)~0x7;
>> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
>> > - if (EFI_ERROR (Status)) {
>> > - return Status;
>> > - }
>> > - //
>> > - // Set UHS Mode Select field of Host Control 2 reigster to SDR104
>> > - //
>> > - HostCtrl2 = BIT0 | BIT1;
>> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
>> > - if (EFI_ERROR (Status)) {
>> > - return Status;
>> > +
>> > + Timing = SdMmcMmcHs200;
>> > +
>> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
>> > + Status = mOverride->NotifyPhase (
>> > + Private->ControllerHandle,
>> > + Slot,
>> > + EdkiiSdMmcUhsSignaling,
>> > + &Timing
>> > + );
>> > + if (EFI_ERROR (Status)) {
>> > + DEBUG ((
>> > + DEBUG_ERROR,
>> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
>> > + __FUNCTION__,
>> > + Status
>> > + ));
>> > + return Status;
>> > + }
>> > + } else {
>> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
>> > + if (EFI_ERROR (Status)) {
>> > + return Status;
>> > + }
>> > }
>> > //
>> > // Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit
>> > @@ -910,9 +935,12 @@ EmmcSwitchToHS400 (
>> > IN UINT32 ClockFreq
>> > )
>> > {
>> > - EFI_STATUS Status;
>> > - UINT8 HsTiming;
>> > - UINT8 HostCtrl2;
>> > + EFI_STATUS Status;
>> > + UINT8 HsTiming;
>> > + SD_MMC_UHS_TIMING Timing;
>> > + SD_MMC_HC_PRIVATE_DATA *Private;
>> > +
>> > + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
>> >
>> > Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, ClockFreq, 8);
>> > if (EFI_ERROR (Status)) {
>> > @@ -933,21 +961,30 @@ EmmcSwitchToHS400 (
>> > if (EFI_ERROR (Status)) {
>> > return Status;
>> > }
>> > - //
>> > - // Clean UHS Mode Select field of Host Control 2 reigster before update
>> > - //
>> > - HostCtrl2 = (UINT8)~0x7;
>> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
>> > - if (EFI_ERROR (Status)) {
>> > - return Status;
>> > - }
>> > - //
>> > - // Set UHS Mode Select field of Host Control 2 reigster to HS400
>> > - //
>> > - HostCtrl2 = BIT0 | BIT2;
>> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
>> > - if (EFI_ERROR (Status)) {
>> > - return Status;
>> > +
>> > + Timing = SdMmcMmcHs400;
>> > +
>> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
>> > + Status = mOverride->NotifyPhase (
>> > + Private->ControllerHandle,
>> > + Slot,
>> > + EdkiiSdMmcUhsSignaling,
>> > + &Timing
>> > + );
>> > + if (EFI_ERROR (Status)) {
>> > + DEBUG ((
>> > + DEBUG_ERROR,
>> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
>> > + __FUNCTION__,
>> > + Status
>> > + ));
>> > + return Status;
>> > + }
>> > + } else {
>> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
>> > + if (EFI_ERROR (Status)) {
>> > + return Status;
>> > + }
>> > }
>> >
>> > HsTiming = 3;
>> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
>> > index 8c93933..5645a71 100644
>> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
>> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
>> > @@ -784,8 +784,8 @@ SdCardSetBusMode (
>> > UINT8 BusWidth;
>> > UINT8 AccessMode;
>> > UINT8 HostCtrl1;
>> > - UINT8 HostCtrl2;
>> > UINT8 SwitchResp[64];
>> > + SD_MMC_UHS_TIMING Timing;
>> > SD_MMC_HC_PRIVATE_DATA *Private;
>> >
>> > Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
>> > @@ -817,18 +817,23 @@ SdCardSetBusMode (
>> > if (S18A && (Capability->Sdr104 != 0) && ((SwitchResp[13] & BIT3) != 0)) {
>> > ClockFreq = 208;
>> > AccessMode = 3;
>> > + Timing = SdMmcUhsSdr104;
>> > } else if (S18A && (Capability->Sdr50 != 0) && ((SwitchResp[13] & BIT2) != 0)) {
>> > ClockFreq = 100;
>> > AccessMode = 2;
>> > + Timing = SdMmcUhsSdr50;
>> > } else if (S18A && (Capability->Ddr50 != 0) && ((SwitchResp[13] & BIT4) != 0)) {
>> > ClockFreq = 50;
>> > AccessMode = 4;
>> > + Timing = SdMmcUhsDdr50;
>> > } else if ((SwitchResp[13] & BIT1) != 0) {
>> > ClockFreq = 50;
>> > AccessMode = 1;
>> > + Timing = SdMmcUhsSdr25;
>> > } else {
>> > ClockFreq = 25;
>> > AccessMode = 0;
>> > + Timing = SdMmcUhsSdr12;
>> > }
>> >
>> > Status = SdCardSwitch (PassThru, Slot, AccessMode, 0xF, 0xF, 0xF, TRUE, SwitchResp);
>> > @@ -854,15 +859,27 @@ SdCardSetBusMode (
>> > }
>> > }
>> >
>> > - HostCtrl2 = (UINT8)~0x7;
>> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
>> > - if (EFI_ERROR (Status)) {
>> > - return Status;
>> > - }
>> > - HostCtrl2 = AccessMode;
>> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
>> > - if (EFI_ERROR (Status)) {
>> > - return Status;
>> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
>> > + Status = mOverride->NotifyPhase (
>> > + Private->ControllerHandle,
>> > + Slot,
>> > + EdkiiSdMmcUhsSignaling,
>> > + &Timing
>> > + );
>> > + if (EFI_ERROR (Status)) {
>> > + DEBUG ((
>> > + DEBUG_ERROR,
>> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
>> > + __FUNCTION__,
>> > + Status
>> > + ));
>> > + return Status;
>> > + }
>> > + } else {
>> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
>> > + if (EFI_ERROR (Status)) {
>> > + return Status;
>> > + }
>> > }
>> >
>> > Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capability);
>> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
>> > index 02eb4ad..38d6202 100644
>> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
>> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
>> > @@ -1137,6 +1137,75 @@ SdMmcHcInitHost (
>> > }
>> >
>> > /**
>> > + Set SD Host Controler control 2 registry according to selected speed.
>> > +
>> > + @param[in] PciIo The PCI IO protocol instance.
>> > + @param[in] Slot The slot number of the SD card to send the command to.
>> > + @param[in] Timing The timing to select.
>> > +
>> > + @retval EFI_SUCCESS The timing is set successfully.
>> > + @retval Others The timing isn't set successfully.
>> > +**/
>> > +EFI_STATUS
>> > +SdMmcHcUhsSignaling (
>> > + IN EFI_PCI_IO_PROTOCOL *PciIo,
>> > + IN UINT8 Slot,
>> > + IN SD_MMC_UHS_TIMING Timing
>> > + )
>> > +{
>> > + EFI_STATUS Status;
>> > + UINT8 HostCtrl2;
>> > +
>> > + HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;
>> > + Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
>> > + if (EFI_ERROR (Status)) {
>> > + return Status;
>> > + }
>> > +
>> > + switch (Timing) {
>> > + case SdMmcUhsSdr12:
>> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;
>> > + break;
>> > + case SdMmcUhsSdr25:
>> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;
>> > + break;
>> > + case SdMmcUhsSdr50:
>> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;
>> > + break;
>> > + case SdMmcUhsSdr104:
>> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;
>> > + break;
>> > + case SdMmcUhsDdr50:
>> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;
>> > + break;
>> > + case SdMmcMmcDdr52:
>> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_DDR52;
>> > + break;
>> > + case SdMmcMmcSdr50:
>> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR50;
>> > + break;
>> > + case SdMmcMmcSdr25:
>> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR25;
>> > + break;
>> > + case SdMmcMmcSdr12:
>> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR12;
>> > + break;
>> > + case SdMmcMmcHs200:
>> > + HostCtrl2 = SD_MMC_HC_CTRL_HS200;
>> > + break;
>> > + case SdMmcMmcHs400:
>> > + HostCtrl2 = SD_MMC_HC_CTRL_HS400;
>> > + break;
>> > + default:
>> > + HostCtrl2 = 0;
>> > + break;
>> > + }
>> > + Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
>> > +
>> > + return Status;
>> > +}
>> > +
>>
>> This function looks identical to the override that your are proposing
>> in your platform code. Why is that? Are the values of those defines
>> different?
>>
>
> This is exactly the reason. For Xenon, MMC_HS400 and MMC_HS200 values
> of UHS_MODE_SEL field in HostControl2Register are custom. Actually,
> non-generic UHS_MODE_SEL values are pretty common, from what I can see
> in the Linux code. The new callback allows overriding it. Looking
> forward to your feedback.
>
> Best regards,
> Marcin
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-08 13:07 ` Ard Biesheuvel
@ 2018-10-08 13:17 ` Marcin Wojtas
2018-10-08 13:27 ` Ard Biesheuvel
0 siblings, 1 reply; 47+ messages in thread
From: Marcin Wojtas @ 2018-10-08 13:17 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: Zeng, Star, eric.dong, Ni, Ruiyu, edk2-devel-01, Tian, Feng,
Kinney, Michael D, Gao, Liming, Leif Lindholm, hao.a.wu, nadavh,
jsd@semihalf.com, Tomasz Michalec
pon., 8 paź 2018 o 15:07 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
>
> On 8 October 2018 at 14:59, Marcin Wojtas <mw@semihalf.com> wrote:
> > Hi Ard,
> >
> > pon., 8 paź 2018 o 14:41 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
> >>
> >> (add MdeModulePkg maintainers)
> >>
> >> On 5 October 2018 at 15:25, Marcin Wojtas <mw@semihalf.com> wrote:
> >> > From: Tomasz Michalec <tm@semihalf.com>
> >> >
> >> > Some SD Host Controlers use different values in Host Control 2 Register
> >> > to select UHS Mode. This patch adds a new UhsSignaling type routine to
> >> > the NotifyPhase of the SdMmcOverride protocol.
> >> >
> >> > UHS signaling configuration is moved to a common, default routine
> >> > (SdMmcHcUhsSignaling), which is called when SdMmcOverride does not
> >> > cover this functionality.
> >> >
> >> > Contributed-under: TianoCore Contribution Agreement 1.1
> >> > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> >> > ---
> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 50 +++++++
> >> > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 2 +
> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 153 ++++++++++++--------
> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 37 +++--
> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 69 +++++++++
> >> > 5 files changed, 243 insertions(+), 68 deletions(-)
> >> >
> >> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> >> > index e389d52..a03160d 100644
> >> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> >> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> >> > @@ -63,6 +63,39 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> >> > #define SD_MMC_HC_CTRL_VER 0xFE
> >> >
> >> > //
> >> > +// SD Host Controler bits to HOST_CTRL2 register
> >> > +//
> >> > +#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
> >> > +#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
> >> > +#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
> >> > +#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
> >> > +#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
> >> > +#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
> >> > +#define SD_MMC_HC_CTRL_MMC_DDR52 0x0004
> >> > +#define SD_MMC_HC_CTRL_MMC_SDR50 0x0002
> >> > +#define SD_MMC_HC_CTRL_MMC_SDR25 0x0001
> >> > +#define SD_MMC_HC_CTRL_MMC_SDR12 0x0000
> >> > +#define SD_MMC_HC_CTRL_HS200 0x0003
> >> > +#define SD_MMC_HC_CTRL_HS400 0x0005
> >> > +
> >> > +//
> >> > +// Timing modes for uhs
> >> > +//
> >> > +typedef enum {
> >> > + SdMmcUhsSdr12,
> >> > + SdMmcUhsSdr25,
> >> > + SdMmcUhsSdr50,
> >> > + SdMmcUhsSdr104,
> >> > + SdMmcUhsDdr50,
> >> > + SdMmcMmcDdr52,
> >> > + SdMmcMmcSdr50,
> >> > + SdMmcMmcSdr25,
> >> > + SdMmcMmcSdr12,
> >> > + SdMmcMmcHs200,
> >> > + SdMmcMmcHs400,
> >> > +} SD_MMC_UHS_TIMING;
> >> > +
> >>
> >> Here, we end up with two sets of symbolic constants for the same
> >> thing, and I suppose this enum will be duplicated in your
> >> SdMmcOverride implementation?
> >>
> >
> > Why duplicated? Macros are for generic UHS_MODE_SEL field values for
> > SD and MMC in HostControl2Register.
> >
> > SD_MMC_UHS_TIMING is just a timing mode indicator, it can be used not
> > only in UhsSignaling routine (actually the next patch, with
> > SwitchClockFreqPost, use it...).
> >
> > In my SdMmcOverride implementation this enum is not duplicated,
> > because this file (SdMmcPciHci.h) is included via
> > Protocol/SdMmcOverride.h.
> >
>
> Ah ok. Please don't expose internal headers of the SD/MMC driver via
> Protocol/SdMmcOverride.h
>
OK.
> I think it should be fine to add the enum definition to
> Protocol/SdMmcOverride.h instead.
>
OK.
> But wouldn't it be much easier to have a hook for setting
> HostControl2Register that decodes the value and modifies it according
> to what the platform requires?
>
Can you please explain, how it will be different from UhsSignaling in
current shape (read required timing value and update UHS_MODE_SEL
field)?
Thanks,
Marcin
>
>
> >>
> >>
> >> > +//
> >> > // The transfer modes supported by SD Host Controller
> >> > // Simplified Spec 3.0 Table 1-2
> >> > //
> >> > @@ -508,4 +541,21 @@ SdMmcHcInitTimeoutCtrl (
> >> > IN UINT8 Slot
> >> > );
> >> >
> >> > +/**
> >> > + Set SD Host Controler control 2 registry according to selected speed.
> >> > +
> >> > + @param[in] PciIo The PCI IO protocol instance.
> >> > + @param[in] Slot The slot number of the SD card to send the command to.
> >> > + @param[in] Timing The timing to select.
> >> > +
> >> > + @retval EFI_SUCCESS The timing is set successfully.
> >> > + @retval Others The timing isn't set successfully.
> >> > +**/
> >> > +EFI_STATUS
> >> > +SdMmcHcUhsSignaling (
> >> > + IN EFI_PCI_IO_PROTOCOL *PciIo,
> >> > + IN UINT8 Slot,
> >> > + IN SD_MMC_UHS_TIMING Timing
> >> > + );
> >> > +
> >> > #endif
> >> > diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> >> > index 178945f..25db98a 100644
> >> > --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> >> > +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> >> > @@ -17,6 +17,7 @@
> >> > #ifndef __SD_MMC_OVERRIDE_H__
> >> > #define __SD_MMC_OVERRIDE_H__
> >> >
> >> > +#include <Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h>
> >> > #include <Protocol/SdMmcPassThru.h>
> >> >
> >> > #define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \
> >> > @@ -31,6 +32,7 @@ typedef enum {
> >> > EdkiiSdMmcResetPost,
> >> > EdkiiSdMmcInitHostPre,
> >> > EdkiiSdMmcInitHostPost,
> >> > + EdkiiSdMmcUhsSignaling,
> >> > } EDKII_SD_MMC_PHASE_TYPE;
> >> >
> >> > /**
> >> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> >> > index c5fd214..05bd4a0 100755
> >> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> >> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> >> > @@ -740,10 +740,13 @@ EmmcSwitchToHighSpeed (
> >> > IN UINT8 BusWidth
> >> > )
> >> > {
> >> > - EFI_STATUS Status;
> >> > - UINT8 HsTiming;
> >> > - UINT8 HostCtrl1;
> >> > - UINT8 HostCtrl2;
> >> > + EFI_STATUS Status;
> >> > + UINT8 HsTiming;
> >> > + UINT8 HostCtrl1;
> >> > + SD_MMC_UHS_TIMING Timing;
> >> > + SD_MMC_HC_PRIVATE_DATA *Private;
> >> > +
> >> > + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> >> >
> >> > Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusWidth);
> >> > if (EFI_ERROR (Status)) {
> >> > @@ -758,27 +761,37 @@ EmmcSwitchToHighSpeed (
> >> > return Status;
> >> > }
> >> >
> >> > - //
> >> > - // Clean UHS Mode Select field of Host Control 2 reigster before update
> >> > - //
> >> > - HostCtrl2 = (UINT8)~0x7;
> >> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> >> > - if (EFI_ERROR (Status)) {
> >> > - return Status;
> >> > - }
> >> > - //
> >> > - // Set UHS Mode Select field of Host Control 2 reigster to SDR12/25/50
> >> > - //
> >> > if (IsDdr) {
> >> > - HostCtrl2 = BIT2;
> >> > + Timing = SdMmcMmcDdr52;
> >> > } else if (ClockFreq == 52) {
> >> > - HostCtrl2 = BIT0;
> >> > + Timing = SdMmcMmcSdr50;
> >> > + } else if (ClockFreq == 26) {
> >> > + Timing = SdMmcMmcSdr25;
> >> > } else {
> >> > - HostCtrl2 = 0;
> >> > + Timing = SdMmcMmcSdr12;
> >> > }
> >> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> >> > - if (EFI_ERROR (Status)) {
> >> > - return Status;
> >> > +
> >> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> >> > + Status = mOverride->NotifyPhase (
> >> > + Private->ControllerHandle,
> >> > + Slot,
> >> > + EdkiiSdMmcUhsSignaling,
> >> > + &Timing
> >> > + );
> >> > + if (EFI_ERROR (Status)) {
> >> > + DEBUG ((
> >> > + DEBUG_ERROR,
> >> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> >> > + __FUNCTION__,
> >> > + Status
> >> > + ));
> >> > + return Status;
> >> > + }
> >> > + } else {
> >> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> >> > + if (EFI_ERROR (Status)) {
> >> > + return Status;
> >> > + }
> >> > }
> >> >
> >> > HsTiming = 1;
> >> > @@ -814,10 +827,13 @@ EmmcSwitchToHS200 (
> >> > IN UINT8 BusWidth
> >> > )
> >> > {
> >> > - EFI_STATUS Status;
> >> > - UINT8 HsTiming;
> >> > - UINT8 HostCtrl2;
> >> > - UINT16 ClockCtrl;
> >> > + EFI_STATUS Status;
> >> > + UINT8 HsTiming;
> >> > + UINT16 ClockCtrl;
> >> > + SD_MMC_UHS_TIMING Timing;
> >> > + SD_MMC_HC_PRIVATE_DATA *Private;
> >> > +
> >> > + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> >> >
> >> > if ((BusWidth != 4) && (BusWidth != 8)) {
> >> > return EFI_INVALID_PARAMETER;
> >> > @@ -837,21 +853,30 @@ EmmcSwitchToHS200 (
> >> > if (EFI_ERROR (Status)) {
> >> > return Status;
> >> > }
> >> > - //
> >> > - // Clean UHS Mode Select field of Host Control 2 reigster before update
> >> > - //
> >> > - HostCtrl2 = (UINT8)~0x7;
> >> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> >> > - if (EFI_ERROR (Status)) {
> >> > - return Status;
> >> > - }
> >> > - //
> >> > - // Set UHS Mode Select field of Host Control 2 reigster to SDR104
> >> > - //
> >> > - HostCtrl2 = BIT0 | BIT1;
> >> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> >> > - if (EFI_ERROR (Status)) {
> >> > - return Status;
> >> > +
> >> > + Timing = SdMmcMmcHs200;
> >> > +
> >> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> >> > + Status = mOverride->NotifyPhase (
> >> > + Private->ControllerHandle,
> >> > + Slot,
> >> > + EdkiiSdMmcUhsSignaling,
> >> > + &Timing
> >> > + );
> >> > + if (EFI_ERROR (Status)) {
> >> > + DEBUG ((
> >> > + DEBUG_ERROR,
> >> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> >> > + __FUNCTION__,
> >> > + Status
> >> > + ));
> >> > + return Status;
> >> > + }
> >> > + } else {
> >> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> >> > + if (EFI_ERROR (Status)) {
> >> > + return Status;
> >> > + }
> >> > }
> >> > //
> >> > // Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit
> >> > @@ -910,9 +935,12 @@ EmmcSwitchToHS400 (
> >> > IN UINT32 ClockFreq
> >> > )
> >> > {
> >> > - EFI_STATUS Status;
> >> > - UINT8 HsTiming;
> >> > - UINT8 HostCtrl2;
> >> > + EFI_STATUS Status;
> >> > + UINT8 HsTiming;
> >> > + SD_MMC_UHS_TIMING Timing;
> >> > + SD_MMC_HC_PRIVATE_DATA *Private;
> >> > +
> >> > + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> >> >
> >> > Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, ClockFreq, 8);
> >> > if (EFI_ERROR (Status)) {
> >> > @@ -933,21 +961,30 @@ EmmcSwitchToHS400 (
> >> > if (EFI_ERROR (Status)) {
> >> > return Status;
> >> > }
> >> > - //
> >> > - // Clean UHS Mode Select field of Host Control 2 reigster before update
> >> > - //
> >> > - HostCtrl2 = (UINT8)~0x7;
> >> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> >> > - if (EFI_ERROR (Status)) {
> >> > - return Status;
> >> > - }
> >> > - //
> >> > - // Set UHS Mode Select field of Host Control 2 reigster to HS400
> >> > - //
> >> > - HostCtrl2 = BIT0 | BIT2;
> >> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> >> > - if (EFI_ERROR (Status)) {
> >> > - return Status;
> >> > +
> >> > + Timing = SdMmcMmcHs400;
> >> > +
> >> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> >> > + Status = mOverride->NotifyPhase (
> >> > + Private->ControllerHandle,
> >> > + Slot,
> >> > + EdkiiSdMmcUhsSignaling,
> >> > + &Timing
> >> > + );
> >> > + if (EFI_ERROR (Status)) {
> >> > + DEBUG ((
> >> > + DEBUG_ERROR,
> >> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> >> > + __FUNCTION__,
> >> > + Status
> >> > + ));
> >> > + return Status;
> >> > + }
> >> > + } else {
> >> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> >> > + if (EFI_ERROR (Status)) {
> >> > + return Status;
> >> > + }
> >> > }
> >> >
> >> > HsTiming = 3;
> >> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> >> > index 8c93933..5645a71 100644
> >> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> >> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> >> > @@ -784,8 +784,8 @@ SdCardSetBusMode (
> >> > UINT8 BusWidth;
> >> > UINT8 AccessMode;
> >> > UINT8 HostCtrl1;
> >> > - UINT8 HostCtrl2;
> >> > UINT8 SwitchResp[64];
> >> > + SD_MMC_UHS_TIMING Timing;
> >> > SD_MMC_HC_PRIVATE_DATA *Private;
> >> >
> >> > Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> >> > @@ -817,18 +817,23 @@ SdCardSetBusMode (
> >> > if (S18A && (Capability->Sdr104 != 0) && ((SwitchResp[13] & BIT3) != 0)) {
> >> > ClockFreq = 208;
> >> > AccessMode = 3;
> >> > + Timing = SdMmcUhsSdr104;
> >> > } else if (S18A && (Capability->Sdr50 != 0) && ((SwitchResp[13] & BIT2) != 0)) {
> >> > ClockFreq = 100;
> >> > AccessMode = 2;
> >> > + Timing = SdMmcUhsSdr50;
> >> > } else if (S18A && (Capability->Ddr50 != 0) && ((SwitchResp[13] & BIT4) != 0)) {
> >> > ClockFreq = 50;
> >> > AccessMode = 4;
> >> > + Timing = SdMmcUhsDdr50;
> >> > } else if ((SwitchResp[13] & BIT1) != 0) {
> >> > ClockFreq = 50;
> >> > AccessMode = 1;
> >> > + Timing = SdMmcUhsSdr25;
> >> > } else {
> >> > ClockFreq = 25;
> >> > AccessMode = 0;
> >> > + Timing = SdMmcUhsSdr12;
> >> > }
> >> >
> >> > Status = SdCardSwitch (PassThru, Slot, AccessMode, 0xF, 0xF, 0xF, TRUE, SwitchResp);
> >> > @@ -854,15 +859,27 @@ SdCardSetBusMode (
> >> > }
> >> > }
> >> >
> >> > - HostCtrl2 = (UINT8)~0x7;
> >> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> >> > - if (EFI_ERROR (Status)) {
> >> > - return Status;
> >> > - }
> >> > - HostCtrl2 = AccessMode;
> >> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> >> > - if (EFI_ERROR (Status)) {
> >> > - return Status;
> >> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> >> > + Status = mOverride->NotifyPhase (
> >> > + Private->ControllerHandle,
> >> > + Slot,
> >> > + EdkiiSdMmcUhsSignaling,
> >> > + &Timing
> >> > + );
> >> > + if (EFI_ERROR (Status)) {
> >> > + DEBUG ((
> >> > + DEBUG_ERROR,
> >> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> >> > + __FUNCTION__,
> >> > + Status
> >> > + ));
> >> > + return Status;
> >> > + }
> >> > + } else {
> >> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> >> > + if (EFI_ERROR (Status)) {
> >> > + return Status;
> >> > + }
> >> > }
> >> >
> >> > Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capability);
> >> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> >> > index 02eb4ad..38d6202 100644
> >> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> >> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> >> > @@ -1137,6 +1137,75 @@ SdMmcHcInitHost (
> >> > }
> >> >
> >> > /**
> >> > + Set SD Host Controler control 2 registry according to selected speed.
> >> > +
> >> > + @param[in] PciIo The PCI IO protocol instance.
> >> > + @param[in] Slot The slot number of the SD card to send the command to.
> >> > + @param[in] Timing The timing to select.
> >> > +
> >> > + @retval EFI_SUCCESS The timing is set successfully.
> >> > + @retval Others The timing isn't set successfully.
> >> > +**/
> >> > +EFI_STATUS
> >> > +SdMmcHcUhsSignaling (
> >> > + IN EFI_PCI_IO_PROTOCOL *PciIo,
> >> > + IN UINT8 Slot,
> >> > + IN SD_MMC_UHS_TIMING Timing
> >> > + )
> >> > +{
> >> > + EFI_STATUS Status;
> >> > + UINT8 HostCtrl2;
> >> > +
> >> > + HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;
> >> > + Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> >> > + if (EFI_ERROR (Status)) {
> >> > + return Status;
> >> > + }
> >> > +
> >> > + switch (Timing) {
> >> > + case SdMmcUhsSdr12:
> >> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;
> >> > + break;
> >> > + case SdMmcUhsSdr25:
> >> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;
> >> > + break;
> >> > + case SdMmcUhsSdr50:
> >> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;
> >> > + break;
> >> > + case SdMmcUhsSdr104:
> >> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;
> >> > + break;
> >> > + case SdMmcUhsDdr50:
> >> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;
> >> > + break;
> >> > + case SdMmcMmcDdr52:
> >> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_DDR52;
> >> > + break;
> >> > + case SdMmcMmcSdr50:
> >> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR50;
> >> > + break;
> >> > + case SdMmcMmcSdr25:
> >> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR25;
> >> > + break;
> >> > + case SdMmcMmcSdr12:
> >> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR12;
> >> > + break;
> >> > + case SdMmcMmcHs200:
> >> > + HostCtrl2 = SD_MMC_HC_CTRL_HS200;
> >> > + break;
> >> > + case SdMmcMmcHs400:
> >> > + HostCtrl2 = SD_MMC_HC_CTRL_HS400;
> >> > + break;
> >> > + default:
> >> > + HostCtrl2 = 0;
> >> > + break;
> >> > + }
> >> > + Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> >> > +
> >> > + return Status;
> >> > +}
> >> > +
> >>
> >> This function looks identical to the override that your are proposing
> >> in your platform code. Why is that? Are the values of those defines
> >> different?
> >>
> >
> > This is exactly the reason. For Xenon, MMC_HS400 and MMC_HS200 values
> > of UHS_MODE_SEL field in HostControl2Register are custom. Actually,
> > non-generic UHS_MODE_SEL values are pretty common, from what I can see
> > in the Linux code. The new callback allows overriding it. Looking
> > forward to your feedback.
> >
> > Best regards,
> > Marcin
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-08 13:17 ` Marcin Wojtas
@ 2018-10-08 13:27 ` Ard Biesheuvel
2018-10-08 13:37 ` Marcin Wojtas
0 siblings, 1 reply; 47+ messages in thread
From: Ard Biesheuvel @ 2018-10-08 13:27 UTC (permalink / raw)
To: Marcin Wojtas
Cc: Zeng, Star, Eric Dong, Ni, Ruiyu, edk2-devel-01, Tian, Feng,
Kinney, Michael D, Gao, Liming, Leif Lindholm, Wu, Hao A,
Nadav Haklai, jsd@semihalf.com, Tomasz Michalec
On 8 October 2018 at 15:17, Marcin Wojtas <mw@semihalf.com> wrote:
> pon., 8 paź 2018 o 15:07 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
>>
>> On 8 October 2018 at 14:59, Marcin Wojtas <mw@semihalf.com> wrote:
>> > Hi Ard,
>> >
>> > pon., 8 paź 2018 o 14:41 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
>> >>
>> >> (add MdeModulePkg maintainers)
>> >>
>> >> On 5 October 2018 at 15:25, Marcin Wojtas <mw@semihalf.com> wrote:
>> >> > From: Tomasz Michalec <tm@semihalf.com>
>> >> >
>> >> > Some SD Host Controlers use different values in Host Control 2 Register
>> >> > to select UHS Mode. This patch adds a new UhsSignaling type routine to
>> >> > the NotifyPhase of the SdMmcOverride protocol.
>> >> >
>> >> > UHS signaling configuration is moved to a common, default routine
>> >> > (SdMmcHcUhsSignaling), which is called when SdMmcOverride does not
>> >> > cover this functionality.
>> >> >
>> >> > Contributed-under: TianoCore Contribution Agreement 1.1
>> >> > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>> >> > ---
>> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 50 +++++++
>> >> > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 2 +
>> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 153 ++++++++++++--------
>> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 37 +++--
>> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 69 +++++++++
>> >> > 5 files changed, 243 insertions(+), 68 deletions(-)
>> >> >
>> >> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
>> >> > index e389d52..a03160d 100644
>> >> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
>> >> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
>> >> > @@ -63,6 +63,39 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> >> > #define SD_MMC_HC_CTRL_VER 0xFE
>> >> >
>> >> > //
>> >> > +// SD Host Controler bits to HOST_CTRL2 register
>> >> > +//
>> >> > +#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
>> >> > +#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
>> >> > +#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
>> >> > +#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
>> >> > +#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
>> >> > +#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
>> >> > +#define SD_MMC_HC_CTRL_MMC_DDR52 0x0004
>> >> > +#define SD_MMC_HC_CTRL_MMC_SDR50 0x0002
>> >> > +#define SD_MMC_HC_CTRL_MMC_SDR25 0x0001
>> >> > +#define SD_MMC_HC_CTRL_MMC_SDR12 0x0000
>> >> > +#define SD_MMC_HC_CTRL_HS200 0x0003
>> >> > +#define SD_MMC_HC_CTRL_HS400 0x0005
>> >> > +
>> >> > +//
>> >> > +// Timing modes for uhs
>> >> > +//
>> >> > +typedef enum {
>> >> > + SdMmcUhsSdr12,
>> >> > + SdMmcUhsSdr25,
>> >> > + SdMmcUhsSdr50,
>> >> > + SdMmcUhsSdr104,
>> >> > + SdMmcUhsDdr50,
>> >> > + SdMmcMmcDdr52,
>> >> > + SdMmcMmcSdr50,
>> >> > + SdMmcMmcSdr25,
>> >> > + SdMmcMmcSdr12,
>> >> > + SdMmcMmcHs200,
>> >> > + SdMmcMmcHs400,
>> >> > +} SD_MMC_UHS_TIMING;
>> >> > +
>> >>
>> >> Here, we end up with two sets of symbolic constants for the same
>> >> thing, and I suppose this enum will be duplicated in your
>> >> SdMmcOverride implementation?
>> >>
>> >
>> > Why duplicated? Macros are for generic UHS_MODE_SEL field values for
>> > SD and MMC in HostControl2Register.
>> >
>> > SD_MMC_UHS_TIMING is just a timing mode indicator, it can be used not
>> > only in UhsSignaling routine (actually the next patch, with
>> > SwitchClockFreqPost, use it...).
>> >
>> > In my SdMmcOverride implementation this enum is not duplicated,
>> > because this file (SdMmcPciHci.h) is included via
>> > Protocol/SdMmcOverride.h.
>> >
>>
>> Ah ok. Please don't expose internal headers of the SD/MMC driver via
>> Protocol/SdMmcOverride.h
>>
>
> OK.
>
>> I think it should be fine to add the enum definition to
>> Protocol/SdMmcOverride.h instead.
>>
>
> OK.
>
>> But wouldn't it be much easier to have a hook for setting
>> HostControl2Register that decodes the value and modifies it according
>> to what the platform requires?
>>
>
> Can you please explain, how it will be different from UhsSignaling in
> current shape (read required timing value and update UHS_MODE_SEL
> field)?
>
Well, you decode the value, and if, e.g., the SD_MMC_HC_CTRL_HS200
bits are set, you substitute them with the appropriate xenon values.
Also, how important is it to drive the SD/MMC at its max rated speed
at boot time? On Synquacer, I just disable HS200 in the capability
struct so I can forget about all this stuff
>>
>>
>> >>
>> >>
>> >> > +//
>> >> > // The transfer modes supported by SD Host Controller
>> >> > // Simplified Spec 3.0 Table 1-2
>> >> > //
>> >> > @@ -508,4 +541,21 @@ SdMmcHcInitTimeoutCtrl (
>> >> > IN UINT8 Slot
>> >> > );
>> >> >
>> >> > +/**
>> >> > + Set SD Host Controler control 2 registry according to selected speed.
>> >> > +
>> >> > + @param[in] PciIo The PCI IO protocol instance.
>> >> > + @param[in] Slot The slot number of the SD card to send the command to.
>> >> > + @param[in] Timing The timing to select.
>> >> > +
>> >> > + @retval EFI_SUCCESS The timing is set successfully.
>> >> > + @retval Others The timing isn't set successfully.
>> >> > +**/
>> >> > +EFI_STATUS
>> >> > +SdMmcHcUhsSignaling (
>> >> > + IN EFI_PCI_IO_PROTOCOL *PciIo,
>> >> > + IN UINT8 Slot,
>> >> > + IN SD_MMC_UHS_TIMING Timing
>> >> > + );
>> >> > +
>> >> > #endif
>> >> > diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
>> >> > index 178945f..25db98a 100644
>> >> > --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
>> >> > +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
>> >> > @@ -17,6 +17,7 @@
>> >> > #ifndef __SD_MMC_OVERRIDE_H__
>> >> > #define __SD_MMC_OVERRIDE_H__
>> >> >
>> >> > +#include <Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h>
>> >> > #include <Protocol/SdMmcPassThru.h>
>> >> >
>> >> > #define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \
>> >> > @@ -31,6 +32,7 @@ typedef enum {
>> >> > EdkiiSdMmcResetPost,
>> >> > EdkiiSdMmcInitHostPre,
>> >> > EdkiiSdMmcInitHostPost,
>> >> > + EdkiiSdMmcUhsSignaling,
>> >> > } EDKII_SD_MMC_PHASE_TYPE;
>> >> >
>> >> > /**
>> >> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
>> >> > index c5fd214..05bd4a0 100755
>> >> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
>> >> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
>> >> > @@ -740,10 +740,13 @@ EmmcSwitchToHighSpeed (
>> >> > IN UINT8 BusWidth
>> >> > )
>> >> > {
>> >> > - EFI_STATUS Status;
>> >> > - UINT8 HsTiming;
>> >> > - UINT8 HostCtrl1;
>> >> > - UINT8 HostCtrl2;
>> >> > + EFI_STATUS Status;
>> >> > + UINT8 HsTiming;
>> >> > + UINT8 HostCtrl1;
>> >> > + SD_MMC_UHS_TIMING Timing;
>> >> > + SD_MMC_HC_PRIVATE_DATA *Private;
>> >> > +
>> >> > + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
>> >> >
>> >> > Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusWidth);
>> >> > if (EFI_ERROR (Status)) {
>> >> > @@ -758,27 +761,37 @@ EmmcSwitchToHighSpeed (
>> >> > return Status;
>> >> > }
>> >> >
>> >> > - //
>> >> > - // Clean UHS Mode Select field of Host Control 2 reigster before update
>> >> > - //
>> >> > - HostCtrl2 = (UINT8)~0x7;
>> >> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
>> >> > - if (EFI_ERROR (Status)) {
>> >> > - return Status;
>> >> > - }
>> >> > - //
>> >> > - // Set UHS Mode Select field of Host Control 2 reigster to SDR12/25/50
>> >> > - //
>> >> > if (IsDdr) {
>> >> > - HostCtrl2 = BIT2;
>> >> > + Timing = SdMmcMmcDdr52;
>> >> > } else if (ClockFreq == 52) {
>> >> > - HostCtrl2 = BIT0;
>> >> > + Timing = SdMmcMmcSdr50;
>> >> > + } else if (ClockFreq == 26) {
>> >> > + Timing = SdMmcMmcSdr25;
>> >> > } else {
>> >> > - HostCtrl2 = 0;
>> >> > + Timing = SdMmcMmcSdr12;
>> >> > }
>> >> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
>> >> > - if (EFI_ERROR (Status)) {
>> >> > - return Status;
>> >> > +
>> >> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
>> >> > + Status = mOverride->NotifyPhase (
>> >> > + Private->ControllerHandle,
>> >> > + Slot,
>> >> > + EdkiiSdMmcUhsSignaling,
>> >> > + &Timing
>> >> > + );
>> >> > + if (EFI_ERROR (Status)) {
>> >> > + DEBUG ((
>> >> > + DEBUG_ERROR,
>> >> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
>> >> > + __FUNCTION__,
>> >> > + Status
>> >> > + ));
>> >> > + return Status;
>> >> > + }
>> >> > + } else {
>> >> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
>> >> > + if (EFI_ERROR (Status)) {
>> >> > + return Status;
>> >> > + }
>> >> > }
>> >> >
>> >> > HsTiming = 1;
>> >> > @@ -814,10 +827,13 @@ EmmcSwitchToHS200 (
>> >> > IN UINT8 BusWidth
>> >> > )
>> >> > {
>> >> > - EFI_STATUS Status;
>> >> > - UINT8 HsTiming;
>> >> > - UINT8 HostCtrl2;
>> >> > - UINT16 ClockCtrl;
>> >> > + EFI_STATUS Status;
>> >> > + UINT8 HsTiming;
>> >> > + UINT16 ClockCtrl;
>> >> > + SD_MMC_UHS_TIMING Timing;
>> >> > + SD_MMC_HC_PRIVATE_DATA *Private;
>> >> > +
>> >> > + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
>> >> >
>> >> > if ((BusWidth != 4) && (BusWidth != 8)) {
>> >> > return EFI_INVALID_PARAMETER;
>> >> > @@ -837,21 +853,30 @@ EmmcSwitchToHS200 (
>> >> > if (EFI_ERROR (Status)) {
>> >> > return Status;
>> >> > }
>> >> > - //
>> >> > - // Clean UHS Mode Select field of Host Control 2 reigster before update
>> >> > - //
>> >> > - HostCtrl2 = (UINT8)~0x7;
>> >> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
>> >> > - if (EFI_ERROR (Status)) {
>> >> > - return Status;
>> >> > - }
>> >> > - //
>> >> > - // Set UHS Mode Select field of Host Control 2 reigster to SDR104
>> >> > - //
>> >> > - HostCtrl2 = BIT0 | BIT1;
>> >> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
>> >> > - if (EFI_ERROR (Status)) {
>> >> > - return Status;
>> >> > +
>> >> > + Timing = SdMmcMmcHs200;
>> >> > +
>> >> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
>> >> > + Status = mOverride->NotifyPhase (
>> >> > + Private->ControllerHandle,
>> >> > + Slot,
>> >> > + EdkiiSdMmcUhsSignaling,
>> >> > + &Timing
>> >> > + );
>> >> > + if (EFI_ERROR (Status)) {
>> >> > + DEBUG ((
>> >> > + DEBUG_ERROR,
>> >> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
>> >> > + __FUNCTION__,
>> >> > + Status
>> >> > + ));
>> >> > + return Status;
>> >> > + }
>> >> > + } else {
>> >> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
>> >> > + if (EFI_ERROR (Status)) {
>> >> > + return Status;
>> >> > + }
>> >> > }
>> >> > //
>> >> > // Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit
>> >> > @@ -910,9 +935,12 @@ EmmcSwitchToHS400 (
>> >> > IN UINT32 ClockFreq
>> >> > )
>> >> > {
>> >> > - EFI_STATUS Status;
>> >> > - UINT8 HsTiming;
>> >> > - UINT8 HostCtrl2;
>> >> > + EFI_STATUS Status;
>> >> > + UINT8 HsTiming;
>> >> > + SD_MMC_UHS_TIMING Timing;
>> >> > + SD_MMC_HC_PRIVATE_DATA *Private;
>> >> > +
>> >> > + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
>> >> >
>> >> > Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, ClockFreq, 8);
>> >> > if (EFI_ERROR (Status)) {
>> >> > @@ -933,21 +961,30 @@ EmmcSwitchToHS400 (
>> >> > if (EFI_ERROR (Status)) {
>> >> > return Status;
>> >> > }
>> >> > - //
>> >> > - // Clean UHS Mode Select field of Host Control 2 reigster before update
>> >> > - //
>> >> > - HostCtrl2 = (UINT8)~0x7;
>> >> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
>> >> > - if (EFI_ERROR (Status)) {
>> >> > - return Status;
>> >> > - }
>> >> > - //
>> >> > - // Set UHS Mode Select field of Host Control 2 reigster to HS400
>> >> > - //
>> >> > - HostCtrl2 = BIT0 | BIT2;
>> >> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
>> >> > - if (EFI_ERROR (Status)) {
>> >> > - return Status;
>> >> > +
>> >> > + Timing = SdMmcMmcHs400;
>> >> > +
>> >> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
>> >> > + Status = mOverride->NotifyPhase (
>> >> > + Private->ControllerHandle,
>> >> > + Slot,
>> >> > + EdkiiSdMmcUhsSignaling,
>> >> > + &Timing
>> >> > + );
>> >> > + if (EFI_ERROR (Status)) {
>> >> > + DEBUG ((
>> >> > + DEBUG_ERROR,
>> >> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
>> >> > + __FUNCTION__,
>> >> > + Status
>> >> > + ));
>> >> > + return Status;
>> >> > + }
>> >> > + } else {
>> >> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
>> >> > + if (EFI_ERROR (Status)) {
>> >> > + return Status;
>> >> > + }
>> >> > }
>> >> >
>> >> > HsTiming = 3;
>> >> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
>> >> > index 8c93933..5645a71 100644
>> >> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
>> >> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
>> >> > @@ -784,8 +784,8 @@ SdCardSetBusMode (
>> >> > UINT8 BusWidth;
>> >> > UINT8 AccessMode;
>> >> > UINT8 HostCtrl1;
>> >> > - UINT8 HostCtrl2;
>> >> > UINT8 SwitchResp[64];
>> >> > + SD_MMC_UHS_TIMING Timing;
>> >> > SD_MMC_HC_PRIVATE_DATA *Private;
>> >> >
>> >> > Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
>> >> > @@ -817,18 +817,23 @@ SdCardSetBusMode (
>> >> > if (S18A && (Capability->Sdr104 != 0) && ((SwitchResp[13] & BIT3) != 0)) {
>> >> > ClockFreq = 208;
>> >> > AccessMode = 3;
>> >> > + Timing = SdMmcUhsSdr104;
>> >> > } else if (S18A && (Capability->Sdr50 != 0) && ((SwitchResp[13] & BIT2) != 0)) {
>> >> > ClockFreq = 100;
>> >> > AccessMode = 2;
>> >> > + Timing = SdMmcUhsSdr50;
>> >> > } else if (S18A && (Capability->Ddr50 != 0) && ((SwitchResp[13] & BIT4) != 0)) {
>> >> > ClockFreq = 50;
>> >> > AccessMode = 4;
>> >> > + Timing = SdMmcUhsDdr50;
>> >> > } else if ((SwitchResp[13] & BIT1) != 0) {
>> >> > ClockFreq = 50;
>> >> > AccessMode = 1;
>> >> > + Timing = SdMmcUhsSdr25;
>> >> > } else {
>> >> > ClockFreq = 25;
>> >> > AccessMode = 0;
>> >> > + Timing = SdMmcUhsSdr12;
>> >> > }
>> >> >
>> >> > Status = SdCardSwitch (PassThru, Slot, AccessMode, 0xF, 0xF, 0xF, TRUE, SwitchResp);
>> >> > @@ -854,15 +859,27 @@ SdCardSetBusMode (
>> >> > }
>> >> > }
>> >> >
>> >> > - HostCtrl2 = (UINT8)~0x7;
>> >> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
>> >> > - if (EFI_ERROR (Status)) {
>> >> > - return Status;
>> >> > - }
>> >> > - HostCtrl2 = AccessMode;
>> >> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
>> >> > - if (EFI_ERROR (Status)) {
>> >> > - return Status;
>> >> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
>> >> > + Status = mOverride->NotifyPhase (
>> >> > + Private->ControllerHandle,
>> >> > + Slot,
>> >> > + EdkiiSdMmcUhsSignaling,
>> >> > + &Timing
>> >> > + );
>> >> > + if (EFI_ERROR (Status)) {
>> >> > + DEBUG ((
>> >> > + DEBUG_ERROR,
>> >> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
>> >> > + __FUNCTION__,
>> >> > + Status
>> >> > + ));
>> >> > + return Status;
>> >> > + }
>> >> > + } else {
>> >> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
>> >> > + if (EFI_ERROR (Status)) {
>> >> > + return Status;
>> >> > + }
>> >> > }
>> >> >
>> >> > Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capability);
>> >> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
>> >> > index 02eb4ad..38d6202 100644
>> >> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
>> >> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
>> >> > @@ -1137,6 +1137,75 @@ SdMmcHcInitHost (
>> >> > }
>> >> >
>> >> > /**
>> >> > + Set SD Host Controler control 2 registry according to selected speed.
>> >> > +
>> >> > + @param[in] PciIo The PCI IO protocol instance.
>> >> > + @param[in] Slot The slot number of the SD card to send the command to.
>> >> > + @param[in] Timing The timing to select.
>> >> > +
>> >> > + @retval EFI_SUCCESS The timing is set successfully.
>> >> > + @retval Others The timing isn't set successfully.
>> >> > +**/
>> >> > +EFI_STATUS
>> >> > +SdMmcHcUhsSignaling (
>> >> > + IN EFI_PCI_IO_PROTOCOL *PciIo,
>> >> > + IN UINT8 Slot,
>> >> > + IN SD_MMC_UHS_TIMING Timing
>> >> > + )
>> >> > +{
>> >> > + EFI_STATUS Status;
>> >> > + UINT8 HostCtrl2;
>> >> > +
>> >> > + HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;
>> >> > + Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
>> >> > + if (EFI_ERROR (Status)) {
>> >> > + return Status;
>> >> > + }
>> >> > +
>> >> > + switch (Timing) {
>> >> > + case SdMmcUhsSdr12:
>> >> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;
>> >> > + break;
>> >> > + case SdMmcUhsSdr25:
>> >> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;
>> >> > + break;
>> >> > + case SdMmcUhsSdr50:
>> >> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;
>> >> > + break;
>> >> > + case SdMmcUhsSdr104:
>> >> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;
>> >> > + break;
>> >> > + case SdMmcUhsDdr50:
>> >> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;
>> >> > + break;
>> >> > + case SdMmcMmcDdr52:
>> >> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_DDR52;
>> >> > + break;
>> >> > + case SdMmcMmcSdr50:
>> >> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR50;
>> >> > + break;
>> >> > + case SdMmcMmcSdr25:
>> >> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR25;
>> >> > + break;
>> >> > + case SdMmcMmcSdr12:
>> >> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR12;
>> >> > + break;
>> >> > + case SdMmcMmcHs200:
>> >> > + HostCtrl2 = SD_MMC_HC_CTRL_HS200;
>> >> > + break;
>> >> > + case SdMmcMmcHs400:
>> >> > + HostCtrl2 = SD_MMC_HC_CTRL_HS400;
>> >> > + break;
>> >> > + default:
>> >> > + HostCtrl2 = 0;
>> >> > + break;
>> >> > + }
>> >> > + Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
>> >> > +
>> >> > + return Status;
>> >> > +}
>> >> > +
>> >>
>> >> This function looks identical to the override that your are proposing
>> >> in your platform code. Why is that? Are the values of those defines
>> >> different?
>> >>
>> >
>> > This is exactly the reason. For Xenon, MMC_HS400 and MMC_HS200 values
>> > of UHS_MODE_SEL field in HostControl2Register are custom. Actually,
>> > non-generic UHS_MODE_SEL values are pretty common, from what I can see
>> > in the Linux code. The new callback allows overriding it. Looking
>> > forward to your feedback.
>> >
>> > Best regards,
>> > Marcin
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-08 13:27 ` Ard Biesheuvel
@ 2018-10-08 13:37 ` Marcin Wojtas
2018-10-08 13:43 ` Ard Biesheuvel
0 siblings, 1 reply; 47+ messages in thread
From: Marcin Wojtas @ 2018-10-08 13:37 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: Zeng, Star, eric.dong, Ni, Ruiyu, edk2-devel-01, Tian, Feng,
Kinney, Michael D, Gao, Liming, Leif Lindholm, hao.a.wu, nadavh,
jsd@semihalf.com, Tomasz Michalec
pon., 8 paź 2018 o 15:27 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
>
> On 8 October 2018 at 15:17, Marcin Wojtas <mw@semihalf.com> wrote:
> > pon., 8 paź 2018 o 15:07 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
> >>
> >> On 8 October 2018 at 14:59, Marcin Wojtas <mw@semihalf.com> wrote:
> >> > Hi Ard,
> >> >
> >> > pon., 8 paź 2018 o 14:41 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
> >> >>
> >> >> (add MdeModulePkg maintainers)
> >> >>
> >> >> On 5 October 2018 at 15:25, Marcin Wojtas <mw@semihalf.com> wrote:
> >> >> > From: Tomasz Michalec <tm@semihalf.com>
> >> >> >
> >> >> > Some SD Host Controlers use different values in Host Control 2 Register
> >> >> > to select UHS Mode. This patch adds a new UhsSignaling type routine to
> >> >> > the NotifyPhase of the SdMmcOverride protocol.
> >> >> >
> >> >> > UHS signaling configuration is moved to a common, default routine
> >> >> > (SdMmcHcUhsSignaling), which is called when SdMmcOverride does not
> >> >> > cover this functionality.
> >> >> >
> >> >> > Contributed-under: TianoCore Contribution Agreement 1.1
> >> >> > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> >> >> > ---
> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 50 +++++++
> >> >> > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 2 +
> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 153 ++++++++++++--------
> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 37 +++--
> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 69 +++++++++
> >> >> > 5 files changed, 243 insertions(+), 68 deletions(-)
> >> >> >
> >> >> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> >> >> > index e389d52..a03160d 100644
> >> >> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> >> >> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> >> >> > @@ -63,6 +63,39 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> >> >> > #define SD_MMC_HC_CTRL_VER 0xFE
> >> >> >
> >> >> > //
> >> >> > +// SD Host Controler bits to HOST_CTRL2 register
> >> >> > +//
> >> >> > +#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
> >> >> > +#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
> >> >> > +#define SD_MMC_HC_CTRL_MMC_DDR52 0x0004
> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR50 0x0002
> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR25 0x0001
> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR12 0x0000
> >> >> > +#define SD_MMC_HC_CTRL_HS200 0x0003
> >> >> > +#define SD_MMC_HC_CTRL_HS400 0x0005
> >> >> > +
In case we move enums to SdMmcOverride.h, would it be desired, to move
there register fields values as well? Or should I rather use Xenon
macros for all of above locally?
> >> >> > +//
> >> >> > +// Timing modes for uhs
> >> >> > +//
> >> >> > +typedef enum {
> >> >> > + SdMmcUhsSdr12,
> >> >> > + SdMmcUhsSdr25,
> >> >> > + SdMmcUhsSdr50,
> >> >> > + SdMmcUhsSdr104,
> >> >> > + SdMmcUhsDdr50,
> >> >> > + SdMmcMmcDdr52,
> >> >> > + SdMmcMmcSdr50,
> >> >> > + SdMmcMmcSdr25,
> >> >> > + SdMmcMmcSdr12,
> >> >> > + SdMmcMmcHs200,
> >> >> > + SdMmcMmcHs400,
> >> >> > +} SD_MMC_UHS_TIMING;
> >> >> > +
> >> >>
> >> >> Here, we end up with two sets of symbolic constants for the same
> >> >> thing, and I suppose this enum will be duplicated in your
> >> >> SdMmcOverride implementation?
> >> >>
> >> >
> >> > Why duplicated? Macros are for generic UHS_MODE_SEL field values for
> >> > SD and MMC in HostControl2Register.
> >> >
> >> > SD_MMC_UHS_TIMING is just a timing mode indicator, it can be used not
> >> > only in UhsSignaling routine (actually the next patch, with
> >> > SwitchClockFreqPost, use it...).
> >> >
> >> > In my SdMmcOverride implementation this enum is not duplicated,
> >> > because this file (SdMmcPciHci.h) is included via
> >> > Protocol/SdMmcOverride.h.
> >> >
> >>
> >> Ah ok. Please don't expose internal headers of the SD/MMC driver via
> >> Protocol/SdMmcOverride.h
> >>
> >
> > OK.
> >
> >> I think it should be fine to add the enum definition to
> >> Protocol/SdMmcOverride.h instead.
> >>
> >
> > OK.
> >
> >> But wouldn't it be much easier to have a hook for setting
> >> HostControl2Register that decodes the value and modifies it according
> >> to what the platform requires?
> >>
> >
> > Can you please explain, how it will be different from UhsSignaling in
> > current shape (read required timing value and update UHS_MODE_SEL
> > field)?
> >
>
> Well, you decode the value, and if, e.g., the SD_MMC_HC_CTRL_HS200
> bits are set, you substitute them with the appropriate xenon values.
Because values can be same for SD and MMC (e.g. UHS_104 and HS200),
from the controller driver perspective, how would I know, which mode
is requested?
>
> Also, how important is it to drive the SD/MMC at its max rated speed
> at boot time? On Synquacer, I just disable HS200 in the capability
> struct so I can forget about all this stuff
Some customers want it - a real life scenario from one of them:
applications, Linux binaries and rootfs stores in the MMC. Each boot a
couple of hundreds of MB to be loaded. Thanks to HS200 we have huge
time saving.
Best regards,
Marcin
>
>
> >>
> >>
> >> >>
> >> >>
> >> >> > +//
> >> >> > // The transfer modes supported by SD Host Controller
> >> >> > // Simplified Spec 3.0 Table 1-2
> >> >> > //
> >> >> > @@ -508,4 +541,21 @@ SdMmcHcInitTimeoutCtrl (
> >> >> > IN UINT8 Slot
> >> >> > );
> >> >> >
> >> >> > +/**
> >> >> > + Set SD Host Controler control 2 registry according to selected speed.
> >> >> > +
> >> >> > + @param[in] PciIo The PCI IO protocol instance.
> >> >> > + @param[in] Slot The slot number of the SD card to send the command to.
> >> >> > + @param[in] Timing The timing to select.
> >> >> > +
> >> >> > + @retval EFI_SUCCESS The timing is set successfully.
> >> >> > + @retval Others The timing isn't set successfully.
> >> >> > +**/
> >> >> > +EFI_STATUS
> >> >> > +SdMmcHcUhsSignaling (
> >> >> > + IN EFI_PCI_IO_PROTOCOL *PciIo,
> >> >> > + IN UINT8 Slot,
> >> >> > + IN SD_MMC_UHS_TIMING Timing
> >> >> > + );
> >> >> > +
> >> >> > #endif
> >> >> > diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> >> >> > index 178945f..25db98a 100644
> >> >> > --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> >> >> > +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> >> >> > @@ -17,6 +17,7 @@
> >> >> > #ifndef __SD_MMC_OVERRIDE_H__
> >> >> > #define __SD_MMC_OVERRIDE_H__
> >> >> >
> >> >> > +#include <Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h>
> >> >> > #include <Protocol/SdMmcPassThru.h>
> >> >> >
> >> >> > #define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \
> >> >> > @@ -31,6 +32,7 @@ typedef enum {
> >> >> > EdkiiSdMmcResetPost,
> >> >> > EdkiiSdMmcInitHostPre,
> >> >> > EdkiiSdMmcInitHostPost,
> >> >> > + EdkiiSdMmcUhsSignaling,
> >> >> > } EDKII_SD_MMC_PHASE_TYPE;
> >> >> >
> >> >> > /**
> >> >> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> >> >> > index c5fd214..05bd4a0 100755
> >> >> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> >> >> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> >> >> > @@ -740,10 +740,13 @@ EmmcSwitchToHighSpeed (
> >> >> > IN UINT8 BusWidth
> >> >> > )
> >> >> > {
> >> >> > - EFI_STATUS Status;
> >> >> > - UINT8 HsTiming;
> >> >> > - UINT8 HostCtrl1;
> >> >> > - UINT8 HostCtrl2;
> >> >> > + EFI_STATUS Status;
> >> >> > + UINT8 HsTiming;
> >> >> > + UINT8 HostCtrl1;
> >> >> > + SD_MMC_UHS_TIMING Timing;
> >> >> > + SD_MMC_HC_PRIVATE_DATA *Private;
> >> >> > +
> >> >> > + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> >> >> >
> >> >> > Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusWidth);
> >> >> > if (EFI_ERROR (Status)) {
> >> >> > @@ -758,27 +761,37 @@ EmmcSwitchToHighSpeed (
> >> >> > return Status;
> >> >> > }
> >> >> >
> >> >> > - //
> >> >> > - // Clean UHS Mode Select field of Host Control 2 reigster before update
> >> >> > - //
> >> >> > - HostCtrl2 = (UINT8)~0x7;
> >> >> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> >> >> > - if (EFI_ERROR (Status)) {
> >> >> > - return Status;
> >> >> > - }
> >> >> > - //
> >> >> > - // Set UHS Mode Select field of Host Control 2 reigster to SDR12/25/50
> >> >> > - //
> >> >> > if (IsDdr) {
> >> >> > - HostCtrl2 = BIT2;
> >> >> > + Timing = SdMmcMmcDdr52;
> >> >> > } else if (ClockFreq == 52) {
> >> >> > - HostCtrl2 = BIT0;
> >> >> > + Timing = SdMmcMmcSdr50;
> >> >> > + } else if (ClockFreq == 26) {
> >> >> > + Timing = SdMmcMmcSdr25;
> >> >> > } else {
> >> >> > - HostCtrl2 = 0;
> >> >> > + Timing = SdMmcMmcSdr12;
> >> >> > }
> >> >> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> >> >> > - if (EFI_ERROR (Status)) {
> >> >> > - return Status;
> >> >> > +
> >> >> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> >> >> > + Status = mOverride->NotifyPhase (
> >> >> > + Private->ControllerHandle,
> >> >> > + Slot,
> >> >> > + EdkiiSdMmcUhsSignaling,
> >> >> > + &Timing
> >> >> > + );
> >> >> > + if (EFI_ERROR (Status)) {
> >> >> > + DEBUG ((
> >> >> > + DEBUG_ERROR,
> >> >> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> >> >> > + __FUNCTION__,
> >> >> > + Status
> >> >> > + ));
> >> >> > + return Status;
> >> >> > + }
> >> >> > + } else {
> >> >> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> >> >> > + if (EFI_ERROR (Status)) {
> >> >> > + return Status;
> >> >> > + }
> >> >> > }
> >> >> >
> >> >> > HsTiming = 1;
> >> >> > @@ -814,10 +827,13 @@ EmmcSwitchToHS200 (
> >> >> > IN UINT8 BusWidth
> >> >> > )
> >> >> > {
> >> >> > - EFI_STATUS Status;
> >> >> > - UINT8 HsTiming;
> >> >> > - UINT8 HostCtrl2;
> >> >> > - UINT16 ClockCtrl;
> >> >> > + EFI_STATUS Status;
> >> >> > + UINT8 HsTiming;
> >> >> > + UINT16 ClockCtrl;
> >> >> > + SD_MMC_UHS_TIMING Timing;
> >> >> > + SD_MMC_HC_PRIVATE_DATA *Private;
> >> >> > +
> >> >> > + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> >> >> >
> >> >> > if ((BusWidth != 4) && (BusWidth != 8)) {
> >> >> > return EFI_INVALID_PARAMETER;
> >> >> > @@ -837,21 +853,30 @@ EmmcSwitchToHS200 (
> >> >> > if (EFI_ERROR (Status)) {
> >> >> > return Status;
> >> >> > }
> >> >> > - //
> >> >> > - // Clean UHS Mode Select field of Host Control 2 reigster before update
> >> >> > - //
> >> >> > - HostCtrl2 = (UINT8)~0x7;
> >> >> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> >> >> > - if (EFI_ERROR (Status)) {
> >> >> > - return Status;
> >> >> > - }
> >> >> > - //
> >> >> > - // Set UHS Mode Select field of Host Control 2 reigster to SDR104
> >> >> > - //
> >> >> > - HostCtrl2 = BIT0 | BIT1;
> >> >> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> >> >> > - if (EFI_ERROR (Status)) {
> >> >> > - return Status;
> >> >> > +
> >> >> > + Timing = SdMmcMmcHs200;
> >> >> > +
> >> >> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> >> >> > + Status = mOverride->NotifyPhase (
> >> >> > + Private->ControllerHandle,
> >> >> > + Slot,
> >> >> > + EdkiiSdMmcUhsSignaling,
> >> >> > + &Timing
> >> >> > + );
> >> >> > + if (EFI_ERROR (Status)) {
> >> >> > + DEBUG ((
> >> >> > + DEBUG_ERROR,
> >> >> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> >> >> > + __FUNCTION__,
> >> >> > + Status
> >> >> > + ));
> >> >> > + return Status;
> >> >> > + }
> >> >> > + } else {
> >> >> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> >> >> > + if (EFI_ERROR (Status)) {
> >> >> > + return Status;
> >> >> > + }
> >> >> > }
> >> >> > //
> >> >> > // Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit
> >> >> > @@ -910,9 +935,12 @@ EmmcSwitchToHS400 (
> >> >> > IN UINT32 ClockFreq
> >> >> > )
> >> >> > {
> >> >> > - EFI_STATUS Status;
> >> >> > - UINT8 HsTiming;
> >> >> > - UINT8 HostCtrl2;
> >> >> > + EFI_STATUS Status;
> >> >> > + UINT8 HsTiming;
> >> >> > + SD_MMC_UHS_TIMING Timing;
> >> >> > + SD_MMC_HC_PRIVATE_DATA *Private;
> >> >> > +
> >> >> > + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> >> >> >
> >> >> > Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, ClockFreq, 8);
> >> >> > if (EFI_ERROR (Status)) {
> >> >> > @@ -933,21 +961,30 @@ EmmcSwitchToHS400 (
> >> >> > if (EFI_ERROR (Status)) {
> >> >> > return Status;
> >> >> > }
> >> >> > - //
> >> >> > - // Clean UHS Mode Select field of Host Control 2 reigster before update
> >> >> > - //
> >> >> > - HostCtrl2 = (UINT8)~0x7;
> >> >> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> >> >> > - if (EFI_ERROR (Status)) {
> >> >> > - return Status;
> >> >> > - }
> >> >> > - //
> >> >> > - // Set UHS Mode Select field of Host Control 2 reigster to HS400
> >> >> > - //
> >> >> > - HostCtrl2 = BIT0 | BIT2;
> >> >> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> >> >> > - if (EFI_ERROR (Status)) {
> >> >> > - return Status;
> >> >> > +
> >> >> > + Timing = SdMmcMmcHs400;
> >> >> > +
> >> >> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> >> >> > + Status = mOverride->NotifyPhase (
> >> >> > + Private->ControllerHandle,
> >> >> > + Slot,
> >> >> > + EdkiiSdMmcUhsSignaling,
> >> >> > + &Timing
> >> >> > + );
> >> >> > + if (EFI_ERROR (Status)) {
> >> >> > + DEBUG ((
> >> >> > + DEBUG_ERROR,
> >> >> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> >> >> > + __FUNCTION__,
> >> >> > + Status
> >> >> > + ));
> >> >> > + return Status;
> >> >> > + }
> >> >> > + } else {
> >> >> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> >> >> > + if (EFI_ERROR (Status)) {
> >> >> > + return Status;
> >> >> > + }
> >> >> > }
> >> >> >
> >> >> > HsTiming = 3;
> >> >> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> >> >> > index 8c93933..5645a71 100644
> >> >> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> >> >> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> >> >> > @@ -784,8 +784,8 @@ SdCardSetBusMode (
> >> >> > UINT8 BusWidth;
> >> >> > UINT8 AccessMode;
> >> >> > UINT8 HostCtrl1;
> >> >> > - UINT8 HostCtrl2;
> >> >> > UINT8 SwitchResp[64];
> >> >> > + SD_MMC_UHS_TIMING Timing;
> >> >> > SD_MMC_HC_PRIVATE_DATA *Private;
> >> >> >
> >> >> > Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> >> >> > @@ -817,18 +817,23 @@ SdCardSetBusMode (
> >> >> > if (S18A && (Capability->Sdr104 != 0) && ((SwitchResp[13] & BIT3) != 0)) {
> >> >> > ClockFreq = 208;
> >> >> > AccessMode = 3;
> >> >> > + Timing = SdMmcUhsSdr104;
> >> >> > } else if (S18A && (Capability->Sdr50 != 0) && ((SwitchResp[13] & BIT2) != 0)) {
> >> >> > ClockFreq = 100;
> >> >> > AccessMode = 2;
> >> >> > + Timing = SdMmcUhsSdr50;
> >> >> > } else if (S18A && (Capability->Ddr50 != 0) && ((SwitchResp[13] & BIT4) != 0)) {
> >> >> > ClockFreq = 50;
> >> >> > AccessMode = 4;
> >> >> > + Timing = SdMmcUhsDdr50;
> >> >> > } else if ((SwitchResp[13] & BIT1) != 0) {
> >> >> > ClockFreq = 50;
> >> >> > AccessMode = 1;
> >> >> > + Timing = SdMmcUhsSdr25;
> >> >> > } else {
> >> >> > ClockFreq = 25;
> >> >> > AccessMode = 0;
> >> >> > + Timing = SdMmcUhsSdr12;
> >> >> > }
> >> >> >
> >> >> > Status = SdCardSwitch (PassThru, Slot, AccessMode, 0xF, 0xF, 0xF, TRUE, SwitchResp);
> >> >> > @@ -854,15 +859,27 @@ SdCardSetBusMode (
> >> >> > }
> >> >> > }
> >> >> >
> >> >> > - HostCtrl2 = (UINT8)~0x7;
> >> >> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> >> >> > - if (EFI_ERROR (Status)) {
> >> >> > - return Status;
> >> >> > - }
> >> >> > - HostCtrl2 = AccessMode;
> >> >> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> >> >> > - if (EFI_ERROR (Status)) {
> >> >> > - return Status;
> >> >> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> >> >> > + Status = mOverride->NotifyPhase (
> >> >> > + Private->ControllerHandle,
> >> >> > + Slot,
> >> >> > + EdkiiSdMmcUhsSignaling,
> >> >> > + &Timing
> >> >> > + );
> >> >> > + if (EFI_ERROR (Status)) {
> >> >> > + DEBUG ((
> >> >> > + DEBUG_ERROR,
> >> >> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> >> >> > + __FUNCTION__,
> >> >> > + Status
> >> >> > + ));
> >> >> > + return Status;
> >> >> > + }
> >> >> > + } else {
> >> >> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> >> >> > + if (EFI_ERROR (Status)) {
> >> >> > + return Status;
> >> >> > + }
> >> >> > }
> >> >> >
> >> >> > Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capability);
> >> >> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> >> >> > index 02eb4ad..38d6202 100644
> >> >> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> >> >> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> >> >> > @@ -1137,6 +1137,75 @@ SdMmcHcInitHost (
> >> >> > }
> >> >> >
> >> >> > /**
> >> >> > + Set SD Host Controler control 2 registry according to selected speed.
> >> >> > +
> >> >> > + @param[in] PciIo The PCI IO protocol instance.
> >> >> > + @param[in] Slot The slot number of the SD card to send the command to.
> >> >> > + @param[in] Timing The timing to select.
> >> >> > +
> >> >> > + @retval EFI_SUCCESS The timing is set successfully.
> >> >> > + @retval Others The timing isn't set successfully.
> >> >> > +**/
> >> >> > +EFI_STATUS
> >> >> > +SdMmcHcUhsSignaling (
> >> >> > + IN EFI_PCI_IO_PROTOCOL *PciIo,
> >> >> > + IN UINT8 Slot,
> >> >> > + IN SD_MMC_UHS_TIMING Timing
> >> >> > + )
> >> >> > +{
> >> >> > + EFI_STATUS Status;
> >> >> > + UINT8 HostCtrl2;
> >> >> > +
> >> >> > + HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;
> >> >> > + Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> >> >> > + if (EFI_ERROR (Status)) {
> >> >> > + return Status;
> >> >> > + }
> >> >> > +
> >> >> > + switch (Timing) {
> >> >> > + case SdMmcUhsSdr12:
> >> >> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;
> >> >> > + break;
> >> >> > + case SdMmcUhsSdr25:
> >> >> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;
> >> >> > + break;
> >> >> > + case SdMmcUhsSdr50:
> >> >> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;
> >> >> > + break;
> >> >> > + case SdMmcUhsSdr104:
> >> >> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;
> >> >> > + break;
> >> >> > + case SdMmcUhsDdr50:
> >> >> > + HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;
> >> >> > + break;
> >> >> > + case SdMmcMmcDdr52:
> >> >> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_DDR52;
> >> >> > + break;
> >> >> > + case SdMmcMmcSdr50:
> >> >> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR50;
> >> >> > + break;
> >> >> > + case SdMmcMmcSdr25:
> >> >> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR25;
> >> >> > + break;
> >> >> > + case SdMmcMmcSdr12:
> >> >> > + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR12;
> >> >> > + break;
> >> >> > + case SdMmcMmcHs200:
> >> >> > + HostCtrl2 = SD_MMC_HC_CTRL_HS200;
> >> >> > + break;
> >> >> > + case SdMmcMmcHs400:
> >> >> > + HostCtrl2 = SD_MMC_HC_CTRL_HS400;
> >> >> > + break;
> >> >> > + default:
> >> >> > + HostCtrl2 = 0;
> >> >> > + break;
> >> >> > + }
> >> >> > + Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);
> >> >> > +
> >> >> > + return Status;
> >> >> > +}
> >> >> > +
> >> >>
> >> >> This function looks identical to the override that your are proposing
> >> >> in your platform code. Why is that? Are the values of those defines
> >> >> different?
> >> >>
> >> >
> >> > This is exactly the reason. For Xenon, MMC_HS400 and MMC_HS200 values
> >> > of UHS_MODE_SEL field in HostControl2Register are custom. Actually,
> >> > non-generic UHS_MODE_SEL values are pretty common, from what I can see
> >> > in the Linux code. The new callback allows overriding it. Looking
> >> > forward to your feedback.
> >> >
> >> > Best regards,
> >> > Marcin
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-08 13:37 ` Marcin Wojtas
@ 2018-10-08 13:43 ` Ard Biesheuvel
2018-10-08 14:52 ` Marcin Wojtas
0 siblings, 1 reply; 47+ messages in thread
From: Ard Biesheuvel @ 2018-10-08 13:43 UTC (permalink / raw)
To: Marcin Wojtas
Cc: Zeng, Star, Eric Dong, Ni, Ruiyu, edk2-devel-01, Tian, Feng,
Kinney, Michael D, Gao, Liming, Leif Lindholm, Wu, Hao A,
Nadav Haklai, jsd@semihalf.com, Tomasz Michalec
On 8 October 2018 at 15:37, Marcin Wojtas <mw@semihalf.com> wrote:
> pon., 8 paź 2018 o 15:27 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
>>
>> On 8 October 2018 at 15:17, Marcin Wojtas <mw@semihalf.com> wrote:
>> > pon., 8 paź 2018 o 15:07 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
>> >>
>> >> On 8 October 2018 at 14:59, Marcin Wojtas <mw@semihalf.com> wrote:
>> >> > Hi Ard,
>> >> >
>> >> > pon., 8 paź 2018 o 14:41 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
>> >> >>
>> >> >> (add MdeModulePkg maintainers)
>> >> >>
>> >> >> On 5 October 2018 at 15:25, Marcin Wojtas <mw@semihalf.com> wrote:
>> >> >> > From: Tomasz Michalec <tm@semihalf.com>
>> >> >> >
>> >> >> > Some SD Host Controlers use different values in Host Control 2 Register
>> >> >> > to select UHS Mode. This patch adds a new UhsSignaling type routine to
>> >> >> > the NotifyPhase of the SdMmcOverride protocol.
>> >> >> >
>> >> >> > UHS signaling configuration is moved to a common, default routine
>> >> >> > (SdMmcHcUhsSignaling), which is called when SdMmcOverride does not
>> >> >> > cover this functionality.
>> >> >> >
>> >> >> > Contributed-under: TianoCore Contribution Agreement 1.1
>> >> >> > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>> >> >> > ---
>> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 50 +++++++
>> >> >> > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 2 +
>> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 153 ++++++++++++--------
>> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 37 +++--
>> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 69 +++++++++
>> >> >> > 5 files changed, 243 insertions(+), 68 deletions(-)
>> >> >> >
>> >> >> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
>> >> >> > index e389d52..a03160d 100644
>> >> >> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
>> >> >> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
>> >> >> > @@ -63,6 +63,39 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> >> >> > #define SD_MMC_HC_CTRL_VER 0xFE
>> >> >> >
>> >> >> > //
>> >> >> > +// SD Host Controler bits to HOST_CTRL2 register
>> >> >> > +//
>> >> >> > +#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
>> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
>> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
>> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
>> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
>> >> >> > +#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
>> >> >> > +#define SD_MMC_HC_CTRL_MMC_DDR52 0x0004
>> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR50 0x0002
>> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR25 0x0001
>> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR12 0x0000
>> >> >> > +#define SD_MMC_HC_CTRL_HS200 0x0003
>> >> >> > +#define SD_MMC_HC_CTRL_HS400 0x0005
>> >> >> > +
>
> In case we move enums to SdMmcOverride.h, would it be desired, to move
> there register fields values as well? Or should I rather use Xenon
> macros for all of above locally?
>
No, I think the macros should be kept locally.
>> >> >> > +//
>> >> >> > +// Timing modes for uhs
>> >> >> > +//
>> >> >> > +typedef enum {
>> >> >> > + SdMmcUhsSdr12,
>> >> >> > + SdMmcUhsSdr25,
>> >> >> > + SdMmcUhsSdr50,
>> >> >> > + SdMmcUhsSdr104,
>> >> >> > + SdMmcUhsDdr50,
>> >> >> > + SdMmcMmcDdr52,
>> >> >> > + SdMmcMmcSdr50,
>> >> >> > + SdMmcMmcSdr25,
>> >> >> > + SdMmcMmcSdr12,
>> >> >> > + SdMmcMmcHs200,
>> >> >> > + SdMmcMmcHs400,
>> >> >> > +} SD_MMC_UHS_TIMING;
>> >> >> > +
>> >> >>
>> >> >> Here, we end up with two sets of symbolic constants for the same
>> >> >> thing, and I suppose this enum will be duplicated in your
>> >> >> SdMmcOverride implementation?
>> >> >>
>> >> >
>> >> > Why duplicated? Macros are for generic UHS_MODE_SEL field values for
>> >> > SD and MMC in HostControl2Register.
>> >> >
>> >> > SD_MMC_UHS_TIMING is just a timing mode indicator, it can be used not
>> >> > only in UhsSignaling routine (actually the next patch, with
>> >> > SwitchClockFreqPost, use it...).
>> >> >
>> >> > In my SdMmcOverride implementation this enum is not duplicated,
>> >> > because this file (SdMmcPciHci.h) is included via
>> >> > Protocol/SdMmcOverride.h.
>> >> >
>> >>
>> >> Ah ok. Please don't expose internal headers of the SD/MMC driver via
>> >> Protocol/SdMmcOverride.h
>> >>
>> >
>> > OK.
>> >
>> >> I think it should be fine to add the enum definition to
>> >> Protocol/SdMmcOverride.h instead.
>> >>
>> >
>> > OK.
>> >
>> >> But wouldn't it be much easier to have a hook for setting
>> >> HostControl2Register that decodes the value and modifies it according
>> >> to what the platform requires?
>> >>
>> >
>> > Can you please explain, how it will be different from UhsSignaling in
>> > current shape (read required timing value and update UHS_MODE_SEL
>> > field)?
>> >
>>
>> Well, you decode the value, and if, e.g., the SD_MMC_HC_CTRL_HS200
>> bits are set, you substitute them with the appropriate xenon values.
>
> Because values can be same for SD and MMC (e.g. UHS_104 and HS200),
> from the controller driver perspective, how would I know, which mode
> is requested?
>
Good point.
>>
>> Also, how important is it to drive the SD/MMC at its max rated speed
>> at boot time? On Synquacer, I just disable HS200 in the capability
>> struct so I can forget about all this stuff
>
> Some customers want it - a real life scenario from one of them:
> applications, Linux binaries and rootfs stores in the MMC. Each boot a
> couple of hundreds of MB to be loaded. Thanks to HS200 we have huge
> time saving.
>
Do you mean in the initrd? Because otherwise, Linux will use its own
driver and select its own mode.
And btw, does the spec permit using different HC2 values for HS200 / HS400 ?
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-08 13:43 ` Ard Biesheuvel
@ 2018-10-08 14:52 ` Marcin Wojtas
2018-10-08 15:10 ` Ard Biesheuvel
0 siblings, 1 reply; 47+ messages in thread
From: Marcin Wojtas @ 2018-10-08 14:52 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: Zeng, Star, eric.dong, Ni, Ruiyu, edk2-devel-01, Tian, Feng,
Kinney, Michael D, Gao, Liming, Leif Lindholm, hao.a.wu, nadavh,
jsd@semihalf.com, Tomasz Michalec
pon., 8 paź 2018 o 15:43 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
>
> On 8 October 2018 at 15:37, Marcin Wojtas <mw@semihalf.com> wrote:
> > pon., 8 paź 2018 o 15:27 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
> >>
> >> On 8 October 2018 at 15:17, Marcin Wojtas <mw@semihalf.com> wrote:
> >> > pon., 8 paź 2018 o 15:07 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
> >> >>
> >> >> On 8 October 2018 at 14:59, Marcin Wojtas <mw@semihalf.com> wrote:
> >> >> > Hi Ard,
> >> >> >
> >> >> > pon., 8 paź 2018 o 14:41 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
> >> >> >>
> >> >> >> (add MdeModulePkg maintainers)
> >> >> >>
> >> >> >> On 5 October 2018 at 15:25, Marcin Wojtas <mw@semihalf.com> wrote:
> >> >> >> > From: Tomasz Michalec <tm@semihalf.com>
> >> >> >> >
> >> >> >> > Some SD Host Controlers use different values in Host Control 2 Register
> >> >> >> > to select UHS Mode. This patch adds a new UhsSignaling type routine to
> >> >> >> > the NotifyPhase of the SdMmcOverride protocol.
> >> >> >> >
> >> >> >> > UHS signaling configuration is moved to a common, default routine
> >> >> >> > (SdMmcHcUhsSignaling), which is called when SdMmcOverride does not
> >> >> >> > cover this functionality.
> >> >> >> >
> >> >> >> > Contributed-under: TianoCore Contribution Agreement 1.1
> >> >> >> > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> >> >> >> > ---
> >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 50 +++++++
> >> >> >> > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 2 +
> >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 153 ++++++++++++--------
> >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 37 +++--
> >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 69 +++++++++
> >> >> >> > 5 files changed, 243 insertions(+), 68 deletions(-)
> >> >> >> >
> >> >> >> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> >> >> >> > index e389d52..a03160d 100644
> >> >> >> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> >> >> >> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> >> >> >> > @@ -63,6 +63,39 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> >> >> >> > #define SD_MMC_HC_CTRL_VER 0xFE
> >> >> >> >
> >> >> >> > //
> >> >> >> > +// SD Host Controler bits to HOST_CTRL2 register
> >> >> >> > +//
> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
> >> >> >> > +#define SD_MMC_HC_CTRL_MMC_DDR52 0x0004
> >> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR50 0x0002
> >> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR25 0x0001
> >> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR12 0x0000
> >> >> >> > +#define SD_MMC_HC_CTRL_HS200 0x0003
> >> >> >> > +#define SD_MMC_HC_CTRL_HS400 0x0005
> >> >> >> > +
> >
> > In case we move enums to SdMmcOverride.h, would it be desired, to move
> > there register fields values as well? Or should I rather use Xenon
> > macros for all of above locally?
> >
>
> No, I think the macros should be kept locally.
>
> >> >> >> > +//
> >> >> >> > +// Timing modes for uhs
> >> >> >> > +//
> >> >> >> > +typedef enum {
> >> >> >> > + SdMmcUhsSdr12,
> >> >> >> > + SdMmcUhsSdr25,
> >> >> >> > + SdMmcUhsSdr50,
> >> >> >> > + SdMmcUhsSdr104,
> >> >> >> > + SdMmcUhsDdr50,
> >> >> >> > + SdMmcMmcDdr52,
> >> >> >> > + SdMmcMmcSdr50,
> >> >> >> > + SdMmcMmcSdr25,
> >> >> >> > + SdMmcMmcSdr12,
> >> >> >> > + SdMmcMmcHs200,
> >> >> >> > + SdMmcMmcHs400,
> >> >> >> > +} SD_MMC_UHS_TIMING;
> >> >> >> > +
> >> >> >>
> >> >> >> Here, we end up with two sets of symbolic constants for the same
> >> >> >> thing, and I suppose this enum will be duplicated in your
> >> >> >> SdMmcOverride implementation?
> >> >> >>
> >> >> >
> >> >> > Why duplicated? Macros are for generic UHS_MODE_SEL field values for
> >> >> > SD and MMC in HostControl2Register.
> >> >> >
> >> >> > SD_MMC_UHS_TIMING is just a timing mode indicator, it can be used not
> >> >> > only in UhsSignaling routine (actually the next patch, with
> >> >> > SwitchClockFreqPost, use it...).
> >> >> >
> >> >> > In my SdMmcOverride implementation this enum is not duplicated,
> >> >> > because this file (SdMmcPciHci.h) is included via
> >> >> > Protocol/SdMmcOverride.h.
> >> >> >
> >> >>
> >> >> Ah ok. Please don't expose internal headers of the SD/MMC driver via
> >> >> Protocol/SdMmcOverride.h
> >> >>
> >> >
> >> > OK.
> >> >
> >> >> I think it should be fine to add the enum definition to
> >> >> Protocol/SdMmcOverride.h instead.
> >> >>
> >> >
> >> > OK.
> >> >
> >> >> But wouldn't it be much easier to have a hook for setting
> >> >> HostControl2Register that decodes the value and modifies it according
> >> >> to what the platform requires?
> >> >>
> >> >
> >> > Can you please explain, how it will be different from UhsSignaling in
> >> > current shape (read required timing value and update UHS_MODE_SEL
> >> > field)?
> >> >
> >>
> >> Well, you decode the value, and if, e.g., the SD_MMC_HC_CTRL_HS200
> >> bits are set, you substitute them with the appropriate xenon values.
> >
> > Because values can be same for SD and MMC (e.g. UHS_104 and HS200),
> > from the controller driver perspective, how would I know, which mode
> > is requested?
> >
>
> Good point.
>
> >>
> >> Also, how important is it to drive the SD/MMC at its max rated speed
> >> at boot time? On Synquacer, I just disable HS200 in the capability
> >> struct so I can forget about all this stuff
> >
> > Some customers want it - a real life scenario from one of them:
> > applications, Linux binaries and rootfs stores in the MMC. Each boot a
> > couple of hundreds of MB to be loaded. Thanks to HS200 we have huge
> > time saving.
> >
>
> Do you mean in the initrd? Because otherwise, Linux will use its own
> driver and select its own mode.
No, I mean loading >300MB images from eMMC to memory in the DXE phase,
before booting anything.
>
> And btw, does the spec permit using different HC2 values for HS200 / HS400 ?
According to SD Host Controller Specification v4.20, UHS_MODE_SEL
values 0x5 and 0x6 are "reserved". According to Linux code, HS400
value is treated as "non-standard" and HS200 should be same as for
SDR104 (0x3). Nothing is written about permiting different values, but
given Linux 'sdhci_set_uhs_signaling' and whole bunch of other quirks
used under drivers/mmc overriding standard behavior is very common.
Please let know your desired way of handling custom UhsSignaling.
Best regards,
MArcin
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-08 14:52 ` Marcin Wojtas
@ 2018-10-08 15:10 ` Ard Biesheuvel
2018-10-09 11:22 ` Wu, Hao A
0 siblings, 1 reply; 47+ messages in thread
From: Ard Biesheuvel @ 2018-10-08 15:10 UTC (permalink / raw)
To: Marcin Wojtas, Ni, Ruiyu, Wu, Hao A
Cc: Zeng, Star, Eric Dong, edk2-devel-01, Tian, Feng,
Kinney, Michael D, Gao, Liming, Leif Lindholm, Nadav Haklai,
jsd@semihalf.com, Tomasz Michalec
On 8 October 2018 at 16:52, Marcin Wojtas <mw@semihalf.com> wrote:
> pon., 8 paź 2018 o 15:43 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
>>
>> On 8 October 2018 at 15:37, Marcin Wojtas <mw@semihalf.com> wrote:
>> > pon., 8 paź 2018 o 15:27 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
>> >>
>> >> On 8 October 2018 at 15:17, Marcin Wojtas <mw@semihalf.com> wrote:
>> >> > pon., 8 paź 2018 o 15:07 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
>> >> >>
>> >> >> On 8 October 2018 at 14:59, Marcin Wojtas <mw@semihalf.com> wrote:
>> >> >> > Hi Ard,
>> >> >> >
>> >> >> > pon., 8 paź 2018 o 14:41 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
>> >> >> >>
>> >> >> >> (add MdeModulePkg maintainers)
>> >> >> >>
>> >> >> >> On 5 October 2018 at 15:25, Marcin Wojtas <mw@semihalf.com> wrote:
>> >> >> >> > From: Tomasz Michalec <tm@semihalf.com>
>> >> >> >> >
>> >> >> >> > Some SD Host Controlers use different values in Host Control 2 Register
>> >> >> >> > to select UHS Mode. This patch adds a new UhsSignaling type routine to
>> >> >> >> > the NotifyPhase of the SdMmcOverride protocol.
>> >> >> >> >
>> >> >> >> > UHS signaling configuration is moved to a common, default routine
>> >> >> >> > (SdMmcHcUhsSignaling), which is called when SdMmcOverride does not
>> >> >> >> > cover this functionality.
>> >> >> >> >
>> >> >> >> > Contributed-under: TianoCore Contribution Agreement 1.1
>> >> >> >> > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>> >> >> >> > ---
>> >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 50 +++++++
>> >> >> >> > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 2 +
>> >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 153 ++++++++++++--------
>> >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 37 +++--
>> >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 69 +++++++++
>> >> >> >> > 5 files changed, 243 insertions(+), 68 deletions(-)
>> >> >> >> >
>> >> >> >> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
>> >> >> >> > index e389d52..a03160d 100644
>> >> >> >> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
>> >> >> >> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
>> >> >> >> > @@ -63,6 +63,39 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> >> >> >> > #define SD_MMC_HC_CTRL_VER 0xFE
>> >> >> >> >
>> >> >> >> > //
>> >> >> >> > +// SD Host Controler bits to HOST_CTRL2 register
>> >> >> >> > +//
>> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
>> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
>> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
>> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
>> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
>> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
>> >> >> >> > +#define SD_MMC_HC_CTRL_MMC_DDR52 0x0004
>> >> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR50 0x0002
>> >> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR25 0x0001
>> >> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR12 0x0000
>> >> >> >> > +#define SD_MMC_HC_CTRL_HS200 0x0003
>> >> >> >> > +#define SD_MMC_HC_CTRL_HS400 0x0005
>> >> >> >> > +
>> >
>> > In case we move enums to SdMmcOverride.h, would it be desired, to move
>> > there register fields values as well? Or should I rather use Xenon
>> > macros for all of above locally?
>> >
>>
>> No, I think the macros should be kept locally.
>>
>> >> >> >> > +//
>> >> >> >> > +// Timing modes for uhs
>> >> >> >> > +//
>> >> >> >> > +typedef enum {
>> >> >> >> > + SdMmcUhsSdr12,
>> >> >> >> > + SdMmcUhsSdr25,
>> >> >> >> > + SdMmcUhsSdr50,
>> >> >> >> > + SdMmcUhsSdr104,
>> >> >> >> > + SdMmcUhsDdr50,
>> >> >> >> > + SdMmcMmcDdr52,
>> >> >> >> > + SdMmcMmcSdr50,
>> >> >> >> > + SdMmcMmcSdr25,
>> >> >> >> > + SdMmcMmcSdr12,
>> >> >> >> > + SdMmcMmcHs200,
>> >> >> >> > + SdMmcMmcHs400,
>> >> >> >> > +} SD_MMC_UHS_TIMING;
>> >> >> >> > +
>> >> >> >>
>> >> >> >> Here, we end up with two sets of symbolic constants for the same
>> >> >> >> thing, and I suppose this enum will be duplicated in your
>> >> >> >> SdMmcOverride implementation?
>> >> >> >>
>> >> >> >
>> >> >> > Why duplicated? Macros are for generic UHS_MODE_SEL field values for
>> >> >> > SD and MMC in HostControl2Register.
>> >> >> >
>> >> >> > SD_MMC_UHS_TIMING is just a timing mode indicator, it can be used not
>> >> >> > only in UhsSignaling routine (actually the next patch, with
>> >> >> > SwitchClockFreqPost, use it...).
>> >> >> >
>> >> >> > In my SdMmcOverride implementation this enum is not duplicated,
>> >> >> > because this file (SdMmcPciHci.h) is included via
>> >> >> > Protocol/SdMmcOverride.h.
>> >> >> >
>> >> >>
>> >> >> Ah ok. Please don't expose internal headers of the SD/MMC driver via
>> >> >> Protocol/SdMmcOverride.h
>> >> >>
>> >> >
>> >> > OK.
>> >> >
>> >> >> I think it should be fine to add the enum definition to
>> >> >> Protocol/SdMmcOverride.h instead.
>> >> >>
>> >> >
>> >> > OK.
>> >> >
>> >> >> But wouldn't it be much easier to have a hook for setting
>> >> >> HostControl2Register that decodes the value and modifies it according
>> >> >> to what the platform requires?
>> >> >>
>> >> >
>> >> > Can you please explain, how it will be different from UhsSignaling in
>> >> > current shape (read required timing value and update UHS_MODE_SEL
>> >> > field)?
>> >> >
>> >>
>> >> Well, you decode the value, and if, e.g., the SD_MMC_HC_CTRL_HS200
>> >> bits are set, you substitute them with the appropriate xenon values.
>> >
>> > Because values can be same for SD and MMC (e.g. UHS_104 and HS200),
>> > from the controller driver perspective, how would I know, which mode
>> > is requested?
>> >
>>
>> Good point.
>>
>> >>
>> >> Also, how important is it to drive the SD/MMC at its max rated speed
>> >> at boot time? On Synquacer, I just disable HS200 in the capability
>> >> struct so I can forget about all this stuff
>> >
>> > Some customers want it - a real life scenario from one of them:
>> > applications, Linux binaries and rootfs stores in the MMC. Each boot a
>> > couple of hundreds of MB to be loaded. Thanks to HS200 we have huge
>> > time saving.
>> >
>>
>> Do you mean in the initrd? Because otherwise, Linux will use its own
>> driver and select its own mode.
>
> No, I mean loading >300MB images from eMMC to memory in the DXE phase,
> before booting anything.
>
Yikes
>>
>> And btw, does the spec permit using different HC2 values for HS200 / HS400 ?
>
> According to SD Host Controller Specification v4.20, UHS_MODE_SEL
> values 0x5 and 0x6 are "reserved". According to Linux code, HS400
> value is treated as "non-standard" and HS200 should be same as for
> SDR104 (0x3). Nothing is written about permiting different values, but
> given Linux 'sdhci_set_uhs_signaling' and whole bunch of other quirks
> used under drivers/mmc overriding standard behavior is very common.
> Please let know your desired way of handling custom UhsSignaling.
>
I suppose this is defined by the eMMC spec.
Ruiyu, Hao, could you clarify? Are the host control 2 register values
for HS200/HS400 defined by the eMMC spec?
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-08 15:10 ` Ard Biesheuvel
@ 2018-10-09 11:22 ` Wu, Hao A
2018-10-09 11:32 ` Marcin Wojtas
0 siblings, 1 reply; 47+ messages in thread
From: Wu, Hao A @ 2018-10-09 11:22 UTC (permalink / raw)
To: Ard Biesheuvel, Marcin Wojtas, Ni, Ruiyu
Cc: Tian, Feng, Tomasz Michalec, Dong, Eric, edk2-devel-01,
Gao, Liming, Nadav Haklai, Kinney, Michael D, Zeng, Star
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Ard
> Biesheuvel
> Sent: Monday, October 08, 2018 11:10 PM
> To: Marcin Wojtas; Ni, Ruiyu; Wu, Hao A
> Cc: Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-devel-01; Gao, Liming;
> Nadav Haklai; Kinney, Michael D; Zeng, Star
> Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add
> UhsSignaling to SdMmcOverride protocol
>
> On 8 October 2018 at 16:52, Marcin Wojtas <mw@semihalf.com> wrote:
> > pon., 8 paź 2018 o 15:43 Ard Biesheuvel <ard.biesheuvel@linaro.org>
> napisał(a):
> >>
> >> On 8 October 2018 at 15:37, Marcin Wojtas <mw@semihalf.com> wrote:
> >> > pon., 8 paź 2018 o 15:27 Ard Biesheuvel <ard.biesheuvel@linaro.org>
> napisał(a):
> >> >>
> >> >> On 8 October 2018 at 15:17, Marcin Wojtas <mw@semihalf.com> wrote:
> >> >> > pon., 8 paź 2018 o 15:07 Ard Biesheuvel <ard.biesheuvel@linaro.org>
> napisał(a):
> >> >> >>
> >> >> >> On 8 October 2018 at 14:59, Marcin Wojtas <mw@semihalf.com>
> wrote:
> >> >> >> > Hi Ard,
> >> >> >> >
> >> >> >> > pon., 8 paź 2018 o 14:41 Ard Biesheuvel <ard.biesheuvel@linaro.org>
> napisał(a):
> >> >> >> >>
> >> >> >> >> (add MdeModulePkg maintainers)
> >> >> >> >>
> >> >> >> >> On 5 October 2018 at 15:25, Marcin Wojtas <mw@semihalf.com>
> wrote:
> >> >> >> >> > From: Tomasz Michalec <tm@semihalf.com>
> >> >> >> >> >
> >> >> >> >> > Some SD Host Controlers use different values in Host Control 2
> Register
> >> >> >> >> > to select UHS Mode. This patch adds a new UhsSignaling type
> routine to
> >> >> >> >> > the NotifyPhase of the SdMmcOverride protocol.
> >> >> >> >> >
> >> >> >> >> > UHS signaling configuration is moved to a common, default
> routine
> >> >> >> >> > (SdMmcHcUhsSignaling), which is called when SdMmcOverride
> does not
> >> >> >> >> > cover this functionality.
> >> >> >> >> >
> >> >> >> >> > Contributed-under: TianoCore Contribution Agreement 1.1
> >> >> >> >> > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> >> >> >> >> > ---
> >> >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 50
> +++++++
> >> >> >> >> > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 2 +
> >> >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 153
> ++++++++++++--------
> >> >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 37
> +++--
> >> >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 69
> +++++++++
> >> >> >> >> > 5 files changed, 243 insertions(+), 68 deletions(-)
> >> >> >> >> >
> >> >> >> >> > diff --git
> a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> >> >> >> >> > index e389d52..a03160d 100644
> >> >> >> >> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> >> >> >> >> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> >> >> >> >> > @@ -63,6 +63,39 @@ WITHOUT WARRANTIES OR
> REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> >> >> >> >> > #define SD_MMC_HC_CTRL_VER 0xFE
> >> >> >> >> >
> >> >> >> >> > //
> >> >> >> >> > +// SD Host Controler bits to HOST_CTRL2 register
> >> >> >> >> > +//
> >> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
> >> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
> >> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
> >> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
> >> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
> >> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
> >> >> >> >> > +#define SD_MMC_HC_CTRL_MMC_DDR52 0x0004
> >> >> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR50 0x0002
> >> >> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR25 0x0001
> >> >> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR12 0x0000
> >> >> >> >> > +#define SD_MMC_HC_CTRL_HS200 0x0003
> >> >> >> >> > +#define SD_MMC_HC_CTRL_HS400 0x0005
> >> >> >> >> > +
> >> >
> >> > In case we move enums to SdMmcOverride.h, would it be desired, to
> move
> >> > there register fields values as well? Or should I rather use Xenon
> >> > macros for all of above locally?
> >> >
> >>
> >> No, I think the macros should be kept locally.
> >>
> >> >> >> >> > +//
> >> >> >> >> > +// Timing modes for uhs
> >> >> >> >> > +//
> >> >> >> >> > +typedef enum {
> >> >> >> >> > + SdMmcUhsSdr12,
> >> >> >> >> > + SdMmcUhsSdr25,
> >> >> >> >> > + SdMmcUhsSdr50,
> >> >> >> >> > + SdMmcUhsSdr104,
> >> >> >> >> > + SdMmcUhsDdr50,
> >> >> >> >> > + SdMmcMmcDdr52,
> >> >> >> >> > + SdMmcMmcSdr50,
> >> >> >> >> > + SdMmcMmcSdr25,
> >> >> >> >> > + SdMmcMmcSdr12,
> >> >> >> >> > + SdMmcMmcHs200,
> >> >> >> >> > + SdMmcMmcHs400,
> >> >> >> >> > +} SD_MMC_UHS_TIMING;
> >> >> >> >> > +
> >> >> >> >>
> >> >> >> >> Here, we end up with two sets of symbolic constants for the same
> >> >> >> >> thing, and I suppose this enum will be duplicated in your
> >> >> >> >> SdMmcOverride implementation?
> >> >> >> >>
> >> >> >> >
> >> >> >> > Why duplicated? Macros are for generic UHS_MODE_SEL field
> values for
> >> >> >> > SD and MMC in HostControl2Register.
> >> >> >> >
> >> >> >> > SD_MMC_UHS_TIMING is just a timing mode indicator, it can be
> used not
> >> >> >> > only in UhsSignaling routine (actually the next patch, with
> >> >> >> > SwitchClockFreqPost, use it...).
> >> >> >> >
> >> >> >> > In my SdMmcOverride implementation this enum is not duplicated,
> >> >> >> > because this file (SdMmcPciHci.h) is included via
> >> >> >> > Protocol/SdMmcOverride.h.
> >> >> >> >
> >> >> >>
> >> >> >> Ah ok. Please don't expose internal headers of the SD/MMC driver via
> >> >> >> Protocol/SdMmcOverride.h
> >> >> >>
> >> >> >
> >> >> > OK.
> >> >> >
> >> >> >> I think it should be fine to add the enum definition to
> >> >> >> Protocol/SdMmcOverride.h instead.
> >> >> >>
> >> >> >
> >> >> > OK.
> >> >> >
> >> >> >> But wouldn't it be much easier to have a hook for setting
> >> >> >> HostControl2Register that decodes the value and modifies it according
> >> >> >> to what the platform requires?
> >> >> >>
> >> >> >
> >> >> > Can you please explain, how it will be different from UhsSignaling in
> >> >> > current shape (read required timing value and update UHS_MODE_SEL
> >> >> > field)?
> >> >> >
> >> >>
> >> >> Well, you decode the value, and if, e.g., the SD_MMC_HC_CTRL_HS200
> >> >> bits are set, you substitute them with the appropriate xenon values.
> >> >
> >> > Because values can be same for SD and MMC (e.g. UHS_104 and HS200),
> >> > from the controller driver perspective, how would I know, which mode
> >> > is requested?
> >> >
> >>
> >> Good point.
> >>
> >> >>
> >> >> Also, how important is it to drive the SD/MMC at its max rated speed
> >> >> at boot time? On Synquacer, I just disable HS200 in the capability
> >> >> struct so I can forget about all this stuff
> >> >
> >> > Some customers want it - a real life scenario from one of them:
> >> > applications, Linux binaries and rootfs stores in the MMC. Each boot a
> >> > couple of hundreds of MB to be loaded. Thanks to HS200 we have huge
> >> > time saving.
> >> >
> >>
> >> Do you mean in the initrd? Because otherwise, Linux will use its own
> >> driver and select its own mode.
> >
> > No, I mean loading >300MB images from eMMC to memory in the DXE phase,
> > before booting anything.
> >
>
> Yikes
>
> >>
> >> And btw, does the spec permit using different HC2 values for HS200 / HS400 ?
> >
> > According to SD Host Controller Specification v4.20, UHS_MODE_SEL
> > values 0x5 and 0x6 are "reserved". According to Linux code, HS400
> > value is treated as "non-standard" and HS200 should be same as for
> > SDR104 (0x3). Nothing is written about permiting different values, but
> > given Linux 'sdhci_set_uhs_signaling' and whole bunch of other quirks
> > used under drivers/mmc overriding standard behavior is very common.
> > Please let know your desired way of handling custom UhsSignaling.
> >
>
> I suppose this is defined by the eMMC spec.
>
> Ruiyu, Hao, could you clarify? Are the host control 2 register values
> for HS200/HS400 defined by the eMMC spec?
Hi Ard and Marcin,
As far as I know, the EMMC Electrical Standard Spec 5.1 (latest) does not
mention on how to set the "UHS Mode Select" field of the Host Control 2
Register when switching to HS200/HS400. (Actually, the EMMC spec does not
mention Host Control 2 Register at all)
When it comes to setting the bus mode for EMMC devices, the current
implementation of the SdMmcPciHcDxe driver does a mapping when setting the
Host Control 2 Register:
EMMC High Speed SDR - Freq: 0-52 MHz, Data Rate: Single
matches
SD SDR25 - Freq: 0-50 MHz, Data Rate: Single
EMMC High Speed DDR - Freq: 0-52 MHz, Data Rate: Dual
matches
SD DDR50 - Freq: 0-50 MHz, Data Rate: Dual
EMMC HS200 - Freq: 0-200 MHz, Data Rate: Single
matches
SD SDR104 - Freq: 0-208 MHz, Data Rate: Single
EMMC HS400 - Freq: 0-200 MHz, Data Rate: Dual
matches
SD None
And there is no obvious counterpart for the EMMC HS400 mode in the SD
spec. The driver currently sets the "UHS Mode Select" field to a reserved
value 0x5.
Best Regards,
Hao Wu
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-09 11:22 ` Wu, Hao A
@ 2018-10-09 11:32 ` Marcin Wojtas
2018-10-09 11:45 ` Ard Biesheuvel
0 siblings, 1 reply; 47+ messages in thread
From: Marcin Wojtas @ 2018-10-09 11:32 UTC (permalink / raw)
To: hao.a.wu, Ard Biesheuvel
Cc: Ni, Ruiyu, Tian, Feng, Tomasz Michalec, eric.dong, edk2-devel-01,
Gao, Liming, nadavh, Kinney, Michael D, Zeng, Star
wt., 9 paź 2018 o 13:28 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
>
> > -----Original Message-----
> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Ard
> > Biesheuvel
> > Sent: Monday, October 08, 2018 11:10 PM
> > To: Marcin Wojtas; Ni, Ruiyu; Wu, Hao A
> > Cc: Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-devel-01; Gao, Liming;
> > Nadav Haklai; Kinney, Michael D; Zeng, Star
> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add
> > UhsSignaling to SdMmcOverride protocol
> >
> > On 8 October 2018 at 16:52, Marcin Wojtas <mw@semihalf.com> wrote:
> > > pon., 8 paź 2018 o 15:43 Ard Biesheuvel <ard.biesheuvel@linaro.org>
> > napisał(a):
> > >>
> > >> On 8 October 2018 at 15:37, Marcin Wojtas <mw@semihalf.com> wrote:
> > >> > pon., 8 paź 2018 o 15:27 Ard Biesheuvel <ard.biesheuvel@linaro.org>
> > napisał(a):
> > >> >>
> > >> >> On 8 October 2018 at 15:17, Marcin Wojtas <mw@semihalf.com> wrote:
> > >> >> > pon., 8 paź 2018 o 15:07 Ard Biesheuvel <ard.biesheuvel@linaro.org>
> > napisał(a):
> > >> >> >>
> > >> >> >> On 8 October 2018 at 14:59, Marcin Wojtas <mw@semihalf.com>
> > wrote:
> > >> >> >> > Hi Ard,
> > >> >> >> >
> > >> >> >> > pon., 8 paź 2018 o 14:41 Ard Biesheuvel <ard.biesheuvel@linaro.org>
> > napisał(a):
> > >> >> >> >>
> > >> >> >> >> (add MdeModulePkg maintainers)
> > >> >> >> >>
> > >> >> >> >> On 5 October 2018 at 15:25, Marcin Wojtas <mw@semihalf.com>
> > wrote:
> > >> >> >> >> > From: Tomasz Michalec <tm@semihalf.com>
> > >> >> >> >> >
> > >> >> >> >> > Some SD Host Controlers use different values in Host Control 2
> > Register
> > >> >> >> >> > to select UHS Mode. This patch adds a new UhsSignaling type
> > routine to
> > >> >> >> >> > the NotifyPhase of the SdMmcOverride protocol.
> > >> >> >> >> >
> > >> >> >> >> > UHS signaling configuration is moved to a common, default
> > routine
> > >> >> >> >> > (SdMmcHcUhsSignaling), which is called when SdMmcOverride
> > does not
> > >> >> >> >> > cover this functionality.
> > >> >> >> >> >
> > >> >> >> >> > Contributed-under: TianoCore Contribution Agreement 1.1
> > >> >> >> >> > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> > >> >> >> >> > ---
> > >> >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 50
> > +++++++
> > >> >> >> >> > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 2 +
> > >> >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 153
> > ++++++++++++--------
> > >> >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 37
> > +++--
> > >> >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 69
> > +++++++++
> > >> >> >> >> > 5 files changed, 243 insertions(+), 68 deletions(-)
> > >> >> >> >> >
> > >> >> >> >> > diff --git
> > a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > >> >> >> >> > index e389d52..a03160d 100644
> > >> >> >> >> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > >> >> >> >> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > >> >> >> >> > @@ -63,6 +63,39 @@ WITHOUT WARRANTIES OR
> > REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> > >> >> >> >> > #define SD_MMC_HC_CTRL_VER 0xFE
> > >> >> >> >> >
> > >> >> >> >> > //
> > >> >> >> >> > +// SD Host Controler bits to HOST_CTRL2 register
> > >> >> >> >> > +//
> > >> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
> > >> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
> > >> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
> > >> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
> > >> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
> > >> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
> > >> >> >> >> > +#define SD_MMC_HC_CTRL_MMC_DDR52 0x0004
> > >> >> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR50 0x0002
> > >> >> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR25 0x0001
> > >> >> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR12 0x0000
> > >> >> >> >> > +#define SD_MMC_HC_CTRL_HS200 0x0003
> > >> >> >> >> > +#define SD_MMC_HC_CTRL_HS400 0x0005
> > >> >> >> >> > +
> > >> >
> > >> > In case we move enums to SdMmcOverride.h, would it be desired, to
> > move
> > >> > there register fields values as well? Or should I rather use Xenon
> > >> > macros for all of above locally?
> > >> >
> > >>
> > >> No, I think the macros should be kept locally.
> > >>
> > >> >> >> >> > +//
> > >> >> >> >> > +// Timing modes for uhs
> > >> >> >> >> > +//
> > >> >> >> >> > +typedef enum {
> > >> >> >> >> > + SdMmcUhsSdr12,
> > >> >> >> >> > + SdMmcUhsSdr25,
> > >> >> >> >> > + SdMmcUhsSdr50,
> > >> >> >> >> > + SdMmcUhsSdr104,
> > >> >> >> >> > + SdMmcUhsDdr50,
> > >> >> >> >> > + SdMmcMmcDdr52,
> > >> >> >> >> > + SdMmcMmcSdr50,
> > >> >> >> >> > + SdMmcMmcSdr25,
> > >> >> >> >> > + SdMmcMmcSdr12,
> > >> >> >> >> > + SdMmcMmcHs200,
> > >> >> >> >> > + SdMmcMmcHs400,
> > >> >> >> >> > +} SD_MMC_UHS_TIMING;
> > >> >> >> >> > +
> > >> >> >> >>
> > >> >> >> >> Here, we end up with two sets of symbolic constants for the same
> > >> >> >> >> thing, and I suppose this enum will be duplicated in your
> > >> >> >> >> SdMmcOverride implementation?
> > >> >> >> >>
> > >> >> >> >
> > >> >> >> > Why duplicated? Macros are for generic UHS_MODE_SEL field
> > values for
> > >> >> >> > SD and MMC in HostControl2Register.
> > >> >> >> >
> > >> >> >> > SD_MMC_UHS_TIMING is just a timing mode indicator, it can be
> > used not
> > >> >> >> > only in UhsSignaling routine (actually the next patch, with
> > >> >> >> > SwitchClockFreqPost, use it...).
> > >> >> >> >
> > >> >> >> > In my SdMmcOverride implementation this enum is not duplicated,
> > >> >> >> > because this file (SdMmcPciHci.h) is included via
> > >> >> >> > Protocol/SdMmcOverride.h.
> > >> >> >> >
> > >> >> >>
> > >> >> >> Ah ok. Please don't expose internal headers of the SD/MMC driver via
> > >> >> >> Protocol/SdMmcOverride.h
> > >> >> >>
> > >> >> >
> > >> >> > OK.
> > >> >> >
> > >> >> >> I think it should be fine to add the enum definition to
> > >> >> >> Protocol/SdMmcOverride.h instead.
> > >> >> >>
> > >> >> >
> > >> >> > OK.
> > >> >> >
> > >> >> >> But wouldn't it be much easier to have a hook for setting
> > >> >> >> HostControl2Register that decodes the value and modifies it according
> > >> >> >> to what the platform requires?
> > >> >> >>
> > >> >> >
> > >> >> > Can you please explain, how it will be different from UhsSignaling in
> > >> >> > current shape (read required timing value and update UHS_MODE_SEL
> > >> >> > field)?
> > >> >> >
> > >> >>
> > >> >> Well, you decode the value, and if, e.g., the SD_MMC_HC_CTRL_HS200
> > >> >> bits are set, you substitute them with the appropriate xenon values.
> > >> >
> > >> > Because values can be same for SD and MMC (e.g. UHS_104 and HS200),
> > >> > from the controller driver perspective, how would I know, which mode
> > >> > is requested?
> > >> >
> > >>
> > >> Good point.
> > >>
> > >> >>
> > >> >> Also, how important is it to drive the SD/MMC at its max rated speed
> > >> >> at boot time? On Synquacer, I just disable HS200 in the capability
> > >> >> struct so I can forget about all this stuff
> > >> >
> > >> > Some customers want it - a real life scenario from one of them:
> > >> > applications, Linux binaries and rootfs stores in the MMC. Each boot a
> > >> > couple of hundreds of MB to be loaded. Thanks to HS200 we have huge
> > >> > time saving.
> > >> >
> > >>
> > >> Do you mean in the initrd? Because otherwise, Linux will use its own
> > >> driver and select its own mode.
> > >
> > > No, I mean loading >300MB images from eMMC to memory in the DXE phase,
> > > before booting anything.
> > >
> >
> > Yikes
> >
> > >>
> > >> And btw, does the spec permit using different HC2 values for HS200 / HS400 ?
> > >
> > > According to SD Host Controller Specification v4.20, UHS_MODE_SEL
> > > values 0x5 and 0x6 are "reserved". According to Linux code, HS400
> > > value is treated as "non-standard" and HS200 should be same as for
> > > SDR104 (0x3). Nothing is written about permiting different values, but
> > > given Linux 'sdhci_set_uhs_signaling' and whole bunch of other quirks
> > > used under drivers/mmc overriding standard behavior is very common.
> > > Please let know your desired way of handling custom UhsSignaling.
> > >
> >
> > I suppose this is defined by the eMMC spec.
> >
> > Ruiyu, Hao, could you clarify? Are the host control 2 register values
> > for HS200/HS400 defined by the eMMC spec?
>
> Hi Ard and Marcin,
>
> As far as I know, the EMMC Electrical Standard Spec 5.1 (latest) does not
> mention on how to set the "UHS Mode Select" field of the Host Control 2
> Register when switching to HS200/HS400. (Actually, the EMMC spec does not
> mention Host Control 2 Register at all)
>
> When it comes to setting the bus mode for EMMC devices, the current
> implementation of the SdMmcPciHcDxe driver does a mapping when setting the
> Host Control 2 Register:
>
> EMMC High Speed SDR - Freq: 0-52 MHz, Data Rate: Single
> matches
> SD SDR25 - Freq: 0-50 MHz, Data Rate: Single
>
> EMMC High Speed DDR - Freq: 0-52 MHz, Data Rate: Dual
> matches
> SD DDR50 - Freq: 0-50 MHz, Data Rate: Dual
>
> EMMC HS200 - Freq: 0-200 MHz, Data Rate: Single
> matches
> SD SDR104 - Freq: 0-208 MHz, Data Rate: Single
>
> EMMC HS400 - Freq: 0-200 MHz, Data Rate: Dual
> matches
> SD None
>
> And there is no obvious counterpart for the EMMC HS400 mode in the SD
> spec. The driver currently sets the "UHS Mode Select" field to a reserved
> value 0x5.
>
Thank you Hao, above is on par with what the default UhsSignaling
routine does in this patch. IMO especially in case the EMMC standard
is not unequivocal regarding UHS_MODE_SEL, I'd encourage to accept
some way of updating HostControl2 register, depending on the
implementation. What is your opinion Ard?
Best regards,
Marcin
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-09 11:32 ` Marcin Wojtas
@ 2018-10-09 11:45 ` Ard Biesheuvel
2018-10-09 11:51 ` Marcin Wojtas
0 siblings, 1 reply; 47+ messages in thread
From: Ard Biesheuvel @ 2018-10-09 11:45 UTC (permalink / raw)
To: Marcin Wojtas
Cc: Wu, Hao A, Ni, Ruiyu, Tian, Feng, Tomasz Michalec, Eric Dong,
edk2-devel-01, Gao, Liming, Nadav Haklai, Kinney, Michael D,
Zeng, Star
On 9 October 2018 at 13:32, Marcin Wojtas <mw@semihalf.com> wrote:
> wt., 9 paź 2018 o 13:28 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
>>
>> > -----Original Message-----
>> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Ard
>> > Biesheuvel
>> > Sent: Monday, October 08, 2018 11:10 PM
>> > To: Marcin Wojtas; Ni, Ruiyu; Wu, Hao A
>> > Cc: Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-devel-01; Gao, Liming;
>> > Nadav Haklai; Kinney, Michael D; Zeng, Star
>> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add
>> > UhsSignaling to SdMmcOverride protocol
>> >
...
>> >
>> > I suppose this is defined by the eMMC spec.
>> >
>> > Ruiyu, Hao, could you clarify? Are the host control 2 register values
>> > for HS200/HS400 defined by the eMMC spec?
>>
>> Hi Ard and Marcin,
>>
>> As far as I know, the EMMC Electrical Standard Spec 5.1 (latest) does not
>> mention on how to set the "UHS Mode Select" field of the Host Control 2
>> Register when switching to HS200/HS400. (Actually, the EMMC spec does not
>> mention Host Control 2 Register at all)
>>
>> When it comes to setting the bus mode for EMMC devices, the current
>> implementation of the SdMmcPciHcDxe driver does a mapping when setting the
>> Host Control 2 Register:
>>
>> EMMC High Speed SDR - Freq: 0-52 MHz, Data Rate: Single
>> matches
>> SD SDR25 - Freq: 0-50 MHz, Data Rate: Single
>>
>> EMMC High Speed DDR - Freq: 0-52 MHz, Data Rate: Dual
>> matches
>> SD DDR50 - Freq: 0-50 MHz, Data Rate: Dual
>>
>> EMMC HS200 - Freq: 0-200 MHz, Data Rate: Single
>> matches
>> SD SDR104 - Freq: 0-208 MHz, Data Rate: Single
>>
>> EMMC HS400 - Freq: 0-200 MHz, Data Rate: Dual
>> matches
>> SD None
>>
>> And there is no obvious counterpart for the EMMC HS400 mode in the SD
>> spec. The driver currently sets the "UHS Mode Select" field to a reserved
>> value 0x5.
>>
>
> Thank you Hao, above is on par with what the default UhsSignaling
> routine does in this patch. IMO especially in case the EMMC standard
> is not unequivocal regarding UHS_MODE_SEL, I'd encourage to accept
> some way of updating HostControl2 register, depending on the
> implementation. What is your opinion Ard?
>
I would like to know where the current values in SdMmcPciHcDxe come
from if they are not defined in any spec.
How do we know which ones are the correct ones?
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-09 11:45 ` Ard Biesheuvel
@ 2018-10-09 11:51 ` Marcin Wojtas
2018-10-11 15:43 ` Marcin Wojtas
0 siblings, 1 reply; 47+ messages in thread
From: Marcin Wojtas @ 2018-10-09 11:51 UTC (permalink / raw)
To: Ard Biesheuvel, hao.a.wu
Cc: Ni, Ruiyu, Tian, Feng, Tomasz Michalec, eric.dong, edk2-devel-01,
Gao, Liming, nadavh, Kinney, Michael D, Zeng, Star
wt., 9 paź 2018 o 13:45 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
>
> On 9 October 2018 at 13:32, Marcin Wojtas <mw@semihalf.com> wrote:
> > wt., 9 paź 2018 o 13:28 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
> >>
> >> > -----Original Message-----
> >> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Ard
> >> > Biesheuvel
> >> > Sent: Monday, October 08, 2018 11:10 PM
> >> > To: Marcin Wojtas; Ni, Ruiyu; Wu, Hao A
> >> > Cc: Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-devel-01; Gao, Liming;
> >> > Nadav Haklai; Kinney, Michael D; Zeng, Star
> >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add
> >> > UhsSignaling to SdMmcOverride protocol
> >> >
> ...
> >> >
> >> > I suppose this is defined by the eMMC spec.
> >> >
> >> > Ruiyu, Hao, could you clarify? Are the host control 2 register values
> >> > for HS200/HS400 defined by the eMMC spec?
> >>
> >> Hi Ard and Marcin,
> >>
> >> As far as I know, the EMMC Electrical Standard Spec 5.1 (latest) does not
> >> mention on how to set the "UHS Mode Select" field of the Host Control 2
> >> Register when switching to HS200/HS400. (Actually, the EMMC spec does not
> >> mention Host Control 2 Register at all)
> >>
> >> When it comes to setting the bus mode for EMMC devices, the current
> >> implementation of the SdMmcPciHcDxe driver does a mapping when setting the
> >> Host Control 2 Register:
> >>
> >> EMMC High Speed SDR - Freq: 0-52 MHz, Data Rate: Single
> >> matches
> >> SD SDR25 - Freq: 0-50 MHz, Data Rate: Single
> >>
> >> EMMC High Speed DDR - Freq: 0-52 MHz, Data Rate: Dual
> >> matches
> >> SD DDR50 - Freq: 0-50 MHz, Data Rate: Dual
> >>
> >> EMMC HS200 - Freq: 0-200 MHz, Data Rate: Single
> >> matches
> >> SD SDR104 - Freq: 0-208 MHz, Data Rate: Single
> >>
> >> EMMC HS400 - Freq: 0-200 MHz, Data Rate: Dual
> >> matches
> >> SD None
> >>
> >> And there is no obvious counterpart for the EMMC HS400 mode in the SD
> >> spec. The driver currently sets the "UHS Mode Select" field to a reserved
> >> value 0x5.
> >>
> >
> > Thank you Hao, above is on par with what the default UhsSignaling
> > routine does in this patch. IMO especially in case the EMMC standard
> > is not unequivocal regarding UHS_MODE_SEL, I'd encourage to accept
> > some way of updating HostControl2 register, depending on the
> > implementation. What is your opinion Ard?
> >
>
> I would like to know where the current values in SdMmcPciHcDxe come
> from if they are not defined in any spec.
>
> How do we know which ones are the correct ones?
Hao, can you justify used values?
Thanks,
Marcin
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-09 11:51 ` Marcin Wojtas
@ 2018-10-11 15:43 ` Marcin Wojtas
2018-10-12 1:39 ` Wu, Hao A
0 siblings, 1 reply; 47+ messages in thread
From: Marcin Wojtas @ 2018-10-11 15:43 UTC (permalink / raw)
To: hao.a.wu
Cc: Ni, Ruiyu, Ard Biesheuvel, Tian, Feng, Tomasz Michalec, eric.dong,
edk2-devel-01, Gao, Liming, nadavh, Kinney, Michael D, Zeng, Star
wt., 9 paź 2018 o 13:51 Marcin Wojtas <mw@semihalf.com> napisał(a):
>
> wt., 9 paź 2018 o 13:45 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
> >
> > On 9 October 2018 at 13:32, Marcin Wojtas <mw@semihalf.com> wrote:
> > > wt., 9 paź 2018 o 13:28 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
> > >>
> > >> > -----Original Message-----
> > >> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Ard
> > >> > Biesheuvel
> > >> > Sent: Monday, October 08, 2018 11:10 PM
> > >> > To: Marcin Wojtas; Ni, Ruiyu; Wu, Hao A
> > >> > Cc: Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-devel-01; Gao, Liming;
> > >> > Nadav Haklai; Kinney, Michael D; Zeng, Star
> > >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add
> > >> > UhsSignaling to SdMmcOverride protocol
> > >> >
> > ...
> > >> >
> > >> > I suppose this is defined by the eMMC spec.
> > >> >
> > >> > Ruiyu, Hao, could you clarify? Are the host control 2 register values
> > >> > for HS200/HS400 defined by the eMMC spec?
> > >>
> > >> Hi Ard and Marcin,
> > >>
> > >> As far as I know, the EMMC Electrical Standard Spec 5.1 (latest) does not
> > >> mention on how to set the "UHS Mode Select" field of the Host Control 2
> > >> Register when switching to HS200/HS400. (Actually, the EMMC spec does not
> > >> mention Host Control 2 Register at all)
> > >>
> > >> When it comes to setting the bus mode for EMMC devices, the current
> > >> implementation of the SdMmcPciHcDxe driver does a mapping when setting the
> > >> Host Control 2 Register:
> > >>
> > >> EMMC High Speed SDR - Freq: 0-52 MHz, Data Rate: Single
> > >> matches
> > >> SD SDR25 - Freq: 0-50 MHz, Data Rate: Single
> > >>
> > >> EMMC High Speed DDR - Freq: 0-52 MHz, Data Rate: Dual
> > >> matches
> > >> SD DDR50 - Freq: 0-50 MHz, Data Rate: Dual
> > >>
> > >> EMMC HS200 - Freq: 0-200 MHz, Data Rate: Single
> > >> matches
> > >> SD SDR104 - Freq: 0-208 MHz, Data Rate: Single
> > >>
> > >> EMMC HS400 - Freq: 0-200 MHz, Data Rate: Dual
> > >> matches
> > >> SD None
> > >>
> > >> And there is no obvious counterpart for the EMMC HS400 mode in the SD
> > >> spec. The driver currently sets the "UHS Mode Select" field to a reserved
> > >> value 0x5.
> > >>
> > >
> > > Thank you Hao, above is on par with what the default UhsSignaling
> > > routine does in this patch. IMO especially in case the EMMC standard
> > > is not unequivocal regarding UHS_MODE_SEL, I'd encourage to accept
> > > some way of updating HostControl2 register, depending on the
> > > implementation. What is your opinion Ard?
> > >
> >
> > I would like to know where the current values in SdMmcPciHcDxe come
> > from if they are not defined in any spec.
> >
> > How do we know which ones are the correct ones?
>
> Hao, can you justify used values?
>
Hi Hao,
Can you please take a look at the UHS_MODE_SEL values source for eMMC?
Thanks,
Marcin
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-11 15:43 ` Marcin Wojtas
@ 2018-10-12 1:39 ` Wu, Hao A
2018-10-12 5:06 ` Marcin Wojtas
0 siblings, 1 reply; 47+ messages in thread
From: Wu, Hao A @ 2018-10-12 1:39 UTC (permalink / raw)
To: Marcin Wojtas
Cc: Ni, Ruiyu, Ard Biesheuvel, Tian, Feng, Tomasz Michalec,
Dong, Eric, edk2-devel-01, Gao, Liming, nadavh@marvell.com,
Kinney, Michael D, Zeng, Star
> -----Original Message-----
> From: Marcin Wojtas [mailto:mw@semihalf.com]
> Sent: Thursday, October 11, 2018 11:43 PM
> To: Wu, Hao A
> Cc: Ni, Ruiyu; Ard Biesheuvel; Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-
> devel-01; Gao, Liming; nadavh@marvell.com; Kinney, Michael D; Zeng, Star
> Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add
> UhsSignaling to SdMmcOverride protocol
>
> wt., 9 paź 2018 o 13:51 Marcin Wojtas <mw@semihalf.com> napisał(a):
> >
> > wt., 9 paź 2018 o 13:45 Ard Biesheuvel <ard.biesheuvel@linaro.org>
> napisał(a):
> > >
> > > On 9 October 2018 at 13:32, Marcin Wojtas <mw@semihalf.com> wrote:
> > > > wt., 9 paź 2018 o 13:28 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
> > > >>
> > > >> > -----Original Message-----
> > > >> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On
> Behalf Of Ard
> > > >> > Biesheuvel
> > > >> > Sent: Monday, October 08, 2018 11:10 PM
> > > >> > To: Marcin Wojtas; Ni, Ruiyu; Wu, Hao A
> > > >> > Cc: Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-devel-01; Gao,
> Liming;
> > > >> > Nadav Haklai; Kinney, Michael D; Zeng, Star
> > > >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe:
> Add
> > > >> > UhsSignaling to SdMmcOverride protocol
> > > >> >
> > > ...
> > > >> >
> > > >> > I suppose this is defined by the eMMC spec.
> > > >> >
> > > >> > Ruiyu, Hao, could you clarify? Are the host control 2 register values
> > > >> > for HS200/HS400 defined by the eMMC spec?
> > > >>
> > > >> Hi Ard and Marcin,
> > > >>
> > > >> As far as I know, the EMMC Electrical Standard Spec 5.1 (latest) does
> not
> > > >> mention on how to set the "UHS Mode Select" field of the Host
> Control 2
> > > >> Register when switching to HS200/HS400. (Actually, the EMMC spec
> does not
> > > >> mention Host Control 2 Register at all)
> > > >>
> > > >> When it comes to setting the bus mode for EMMC devices, the current
> > > >> implementation of the SdMmcPciHcDxe driver does a mapping when
> setting the
> > > >> Host Control 2 Register:
> > > >>
> > > >> EMMC High Speed SDR - Freq: 0-52 MHz, Data Rate: Single
> > > >> matches
> > > >> SD SDR25 - Freq: 0-50 MHz, Data Rate: Single
> > > >>
> > > >> EMMC High Speed DDR - Freq: 0-52 MHz, Data Rate: Dual
> > > >> matches
> > > >> SD DDR50 - Freq: 0-50 MHz, Data Rate: Dual
> > > >>
> > > >> EMMC HS200 - Freq: 0-200 MHz, Data Rate: Single
> > > >> matches
> > > >> SD SDR104 - Freq: 0-208 MHz, Data Rate: Single
> > > >>
> > > >> EMMC HS400 - Freq: 0-200 MHz, Data Rate: Dual
> > > >> matches
> > > >> SD None
> > > >>
> > > >> And there is no obvious counterpart for the EMMC HS400 mode in the
> SD
> > > >> spec. The driver currently sets the "UHS Mode Select" field to a
> reserved
> > > >> value 0x5.
> > > >>
> > > >
> > > > Thank you Hao, above is on par with what the default UhsSignaling
> > > > routine does in this patch. IMO especially in case the EMMC standard
> > > > is not unequivocal regarding UHS_MODE_SEL, I'd encourage to accept
> > > > some way of updating HostControl2 register, depending on the
> > > > implementation. What is your opinion Ard?
> > > >
> > >
> > > I would like to know where the current values in SdMmcPciHcDxe come
> > > from if they are not defined in any spec.
> > >
> > > How do we know which ones are the correct ones?
> >
> > Hao, can you justify used values?
> >
>
> Hi Hao,
>
> Can you please take a look at the UHS_MODE_SEL values source for eMMC?
Hi Marcin,
Sorry for the delayed response.
For the current implementation of the SdMmcPciHcDxe driver, the selecting
of "UHS Mode Select" field value of the Host Control 2 Register is based
on a Max Clock Frequency & Data Rate (Single or Dual) matching
relationship between the:
A. Table 3-6 of the SD Specifications Part 1 Physical Layer Simplified
Specification Version 4.10
and
B. Table 4 of the EMMC Electrical Standard Spec 5.1
The matching details was included in my previous reply. The only missing
part is there seems no matching for the EMMC HS400 mode in the SD
specifications. For this case, we are currently using the same approach
with the Linux implementation, that is to set the "UHS Mode Select" to a
value of 0x5 (not standard).
Best Regards,
Hao Wu
>
> Thanks,
> Marcin
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-12 1:39 ` Wu, Hao A
@ 2018-10-12 5:06 ` Marcin Wojtas
2018-10-12 15:55 ` Ard Biesheuvel
0 siblings, 1 reply; 47+ messages in thread
From: Marcin Wojtas @ 2018-10-12 5:06 UTC (permalink / raw)
To: hao.a.wu, Ard Biesheuvel
Cc: Ni, Ruiyu, Tian, Feng, Tomasz Michalec, eric.dong, edk2-devel-01,
Gao, Liming, nadavh, Kinney, Michael D, Zeng, Star
pt., 12 paź 2018 o 03:41 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
>
> > -----Original Message-----
> > From: Marcin Wojtas [mailto:mw@semihalf.com]
> > Sent: Thursday, October 11, 2018 11:43 PM
> > To: Wu, Hao A
> > Cc: Ni, Ruiyu; Ard Biesheuvel; Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-
> > devel-01; Gao, Liming; nadavh@marvell.com; Kinney, Michael D; Zeng, Star
> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add
> > UhsSignaling to SdMmcOverride protocol
> >
> > wt., 9 paź 2018 o 13:51 Marcin Wojtas <mw@semihalf.com> napisał(a):
> > >
> > > wt., 9 paź 2018 o 13:45 Ard Biesheuvel <ard.biesheuvel@linaro.org>
> > napisał(a):
> > > >
> > > > On 9 October 2018 at 13:32, Marcin Wojtas <mw@semihalf.com> wrote:
> > > > > wt., 9 paź 2018 o 13:28 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
> > > > >>
> > > > >> > -----Original Message-----
> > > > >> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On
> > Behalf Of Ard
> > > > >> > Biesheuvel
> > > > >> > Sent: Monday, October 08, 2018 11:10 PM
> > > > >> > To: Marcin Wojtas; Ni, Ruiyu; Wu, Hao A
> > > > >> > Cc: Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-devel-01; Gao,
> > Liming;
> > > > >> > Nadav Haklai; Kinney, Michael D; Zeng, Star
> > > > >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe:
> > Add
> > > > >> > UhsSignaling to SdMmcOverride protocol
> > > > >> >
> > > > ...
> > > > >> >
> > > > >> > I suppose this is defined by the eMMC spec.
> > > > >> >
> > > > >> > Ruiyu, Hao, could you clarify? Are the host control 2 register values
> > > > >> > for HS200/HS400 defined by the eMMC spec?
> > > > >>
> > > > >> Hi Ard and Marcin,
> > > > >>
> > > > >> As far as I know, the EMMC Electrical Standard Spec 5.1 (latest) does
> > not
> > > > >> mention on how to set the "UHS Mode Select" field of the Host
> > Control 2
> > > > >> Register when switching to HS200/HS400. (Actually, the EMMC spec
> > does not
> > > > >> mention Host Control 2 Register at all)
> > > > >>
> > > > >> When it comes to setting the bus mode for EMMC devices, the current
> > > > >> implementation of the SdMmcPciHcDxe driver does a mapping when
> > setting the
> > > > >> Host Control 2 Register:
> > > > >>
> > > > >> EMMC High Speed SDR - Freq: 0-52 MHz, Data Rate: Single
> > > > >> matches
> > > > >> SD SDR25 - Freq: 0-50 MHz, Data Rate: Single
> > > > >>
> > > > >> EMMC High Speed DDR - Freq: 0-52 MHz, Data Rate: Dual
> > > > >> matches
> > > > >> SD DDR50 - Freq: 0-50 MHz, Data Rate: Dual
> > > > >>
> > > > >> EMMC HS200 - Freq: 0-200 MHz, Data Rate: Single
> > > > >> matches
> > > > >> SD SDR104 - Freq: 0-208 MHz, Data Rate: Single
> > > > >>
> > > > >> EMMC HS400 - Freq: 0-200 MHz, Data Rate: Dual
> > > > >> matches
> > > > >> SD None
> > > > >>
> > > > >> And there is no obvious counterpart for the EMMC HS400 mode in the
> > SD
> > > > >> spec. The driver currently sets the "UHS Mode Select" field to a
> > reserved
> > > > >> value 0x5.
> > > > >>
> > > > >
> > > > > Thank you Hao, above is on par with what the default UhsSignaling
> > > > > routine does in this patch. IMO especially in case the EMMC standard
> > > > > is not unequivocal regarding UHS_MODE_SEL, I'd encourage to accept
> > > > > some way of updating HostControl2 register, depending on the
> > > > > implementation. What is your opinion Ard?
> > > > >
> > > >
> > > > I would like to know where the current values in SdMmcPciHcDxe come
> > > > from if they are not defined in any spec.
> > > >
> > > > How do we know which ones are the correct ones?
> > >
> > > Hao, can you justify used values?
> > >
> >
> > Hi Hao,
> >
> > Can you please take a look at the UHS_MODE_SEL values source for eMMC?
>
> Hi Marcin,
>
> Sorry for the delayed response.
>
> For the current implementation of the SdMmcPciHcDxe driver, the selecting
> of "UHS Mode Select" field value of the Host Control 2 Register is based
> on a Max Clock Frequency & Data Rate (Single or Dual) matching
> relationship between the:
>
> A. Table 3-6 of the SD Specifications Part 1 Physical Layer Simplified
> Specification Version 4.10
>
> and
>
> B. Table 4 of the EMMC Electrical Standard Spec 5.1
>
> The matching details was included in my previous reply. The only missing
> part is there seems no matching for the EMMC HS400 mode in the SD
> specifications. For this case, we are currently using the same approach
> with the Linux implementation, that is to set the "UHS Mode Select" to a
> value of 0x5 (not standard).
>
Hao,
Thanks a lot for the clarification.
Ard,
Knowing the numbers details, what is your view of the UhsSignaling handling?
Best regards,
Marcin
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 0/4] SdMmcOverride extension
2018-10-05 13:25 [PATCH v2 0/4] SdMmcOverride extension Marcin Wojtas
` (3 preceding siblings ...)
2018-10-05 13:25 ` [PATCH v2 4/4] MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequency Marcin Wojtas
@ 2018-10-12 5:24 ` Wu, Hao A
2018-10-12 5:33 ` Marcin Wojtas
2018-11-01 7:11 ` Wu, Hao A
5 siblings, 1 reply; 47+ messages in thread
From: Wu, Hao A @ 2018-10-12 5:24 UTC (permalink / raw)
To: Marcin Wojtas, edk2-devel@lists.01.org
Cc: Tian, Feng, Kinney, Michael D, Gao, Liming,
leif.lindholm@linaro.org, ard.biesheuvel@linaro.org,
nadavh@marvell.com, jsd@semihalf.com, tm@semihalf.com
Hi Marcin,
Please grant me some time for this series.
Since I found that the extension of the SdMmc override protocol (mainly
the 3rd and 4th patch of the series) may have something overlaps with a
(internal) request to configure the driver strength parameter and operating
clock frequency of the SD/EMMC devices.
For the (driver strength/operating freq) customize, we already have a
proposal on the way. So I am wondering if you could grant me some time to
investigate whether both the cases can be addressed together based on your
proposed patch.
Thanks in advance.
Best Regards,
Hao Wu
> -----Original Message-----
> From: Marcin Wojtas [mailto:mw@semihalf.com]
> Sent: Friday, October 05, 2018 9:25 PM
> To: edk2-devel@lists.01.org
> Cc: Tian, Feng; Kinney, Michael D; Gao, Liming; leif.lindholm@linaro.org; Wu,
> Hao A; ard.biesheuvel@linaro.org; nadavh@marvell.com;
> mw@semihalf.com; jsd@semihalf.com; tm@semihalf.com
> Subject: [PATCH v2 0/4] SdMmcOverride extension
>
> Hi,
>
> This is the second version of the patchset. Initial one was
> interleaved with the fixes, which after split got already merged.
> The biggest change is - resigning from the new callbacks
> and extending parameter lists of both NotifyPhase and Capability
> routines.
>
> Patches are available in the github:
> https://github.com/MarvellEmbeddedProcessors/edk2-open-
> platform/commits/sdmmc-override-upstream-r20181005
>
> Please note that extending SdMmcOverride protocol was impacting
> so far the only user of it (Synquacer controller). In paralel
> edk2-platforms patchset, a patch can be found:
> ("Silicon/SynQuacer/PlatformDxe: adjust to updated SdMmcOverride")
> which immunizes for above and future extensions of the protocol:
> https://github.com/MarvellEmbeddedProcessors/edk2-open-
> platform/commits/xenon-upstream-r20181005
>
> I'm looking forward to the comments and remarks.
>
> Best regards,
> Marcin
>
> Changelog:
> v1 -> v2
> * Rebase onto newest master
> * 1/4 [new patch] - preparation for extending NotifyPhase
> * 2/4 - UhsSignaling as a part of NotifyPhase
> * 3/4 - SwitchClockFreqPost as a part of NotifyPhase
> * 4/4 - Allow updating BaseClkFreq via Capability instead of the
> independent callback.
>
> Marcin Wojtas (2):
> MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in
> NotifyPhase
> MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequency
>
> Tomasz Michalec (2):
> MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride
> protocol
> MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to
> SdMmcOverride
>
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 6 +
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 62 +++++-
> MdeModulePkg/Include/Protocol/SdMmcOverride.h | 12 +-
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 215
> ++++++++++++++------
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 57 +++++-
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 18 +-
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 108 ++++++++-
> -
> 7 files changed, 383 insertions(+), 95 deletions(-)
>
> --
> 2.7.4
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 0/4] SdMmcOverride extension
2018-10-12 5:24 ` [PATCH v2 0/4] SdMmcOverride extension Wu, Hao A
@ 2018-10-12 5:33 ` Marcin Wojtas
2018-10-12 12:48 ` Wu, Hao A
0 siblings, 1 reply; 47+ messages in thread
From: Marcin Wojtas @ 2018-10-12 5:33 UTC (permalink / raw)
To: hao.a.wu
Cc: edk2-devel-01, Tian, Feng, Kinney, Michael D, Gao, Liming,
Leif Lindholm, Ard Biesheuvel, nadavh, jsd@semihalf.com,
Tomasz Michalec
Hi Hao,
pt., 12 paź 2018 o 07:25 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
>
> Hi Marcin,
>
> Please grant me some time for this series.
>
> Since I found that the extension of the SdMmc override protocol (mainly
> the 3rd and 4th patch of the series) may have something overlaps with a
> (internal) request to configure the driver strength parameter and operating
> clock frequency of the SD/EMMC devices.
>
> For the (driver strength/operating freq) customize, we already have a
> proposal on the way. So I am wondering if you could grant me some time to
> investigate whether both the cases can be addressed together based on your
> proposed patch.
>
Sure. I'm only wondering if it's not best to collect all remarks and
maybe update to v3 both edk2 and edk2-platforms sides (so far the
issues have been not critical, such as typos, parameters' names,
etc.). In the meantime you would be able to validate if the solution
is sufficient for you as well. What do you think? When do you expect
to be able to look at it vs your internal requirements more deeply?
Best regards,
Marcin
> Thanks in advance.
>
> Best Regards,
> Hao Wu
>
>
> > -----Original Message-----
> > From: Marcin Wojtas [mailto:mw@semihalf.com]
> > Sent: Friday, October 05, 2018 9:25 PM
> > To: edk2-devel@lists.01.org
> > Cc: Tian, Feng; Kinney, Michael D; Gao, Liming; leif.lindholm@linaro.org; Wu,
> > Hao A; ard.biesheuvel@linaro.org; nadavh@marvell.com;
> > mw@semihalf.com; jsd@semihalf.com; tm@semihalf.com
> > Subject: [PATCH v2 0/4] SdMmcOverride extension
> >
> > Hi,
> >
> > This is the second version of the patchset. Initial one was
> > interleaved with the fixes, which after split got already merged.
> > The biggest change is - resigning from the new callbacks
> > and extending parameter lists of both NotifyPhase and Capability
> > routines.
> >
> > Patches are available in the github:
> > https://github.com/MarvellEmbeddedProcessors/edk2-open-
> > platform/commits/sdmmc-override-upstream-r20181005
> >
> > Please note that extending SdMmcOverride protocol was impacting
> > so far the only user of it (Synquacer controller). In paralel
> > edk2-platforms patchset, a patch can be found:
> > ("Silicon/SynQuacer/PlatformDxe: adjust to updated SdMmcOverride")
> > which immunizes for above and future extensions of the protocol:
> > https://github.com/MarvellEmbeddedProcessors/edk2-open-
> > platform/commits/xenon-upstream-r20181005
> >
> > I'm looking forward to the comments and remarks.
> >
> > Best regards,
> > Marcin
> >
> > Changelog:
> > v1 -> v2
> > * Rebase onto newest master
> > * 1/4 [new patch] - preparation for extending NotifyPhase
> > * 2/4 - UhsSignaling as a part of NotifyPhase
> > * 3/4 - SwitchClockFreqPost as a part of NotifyPhase
> > * 4/4 - Allow updating BaseClkFreq via Capability instead of the
> > independent callback.
> >
> > Marcin Wojtas (2):
> > MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in
> > NotifyPhase
> > MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequency
> >
> > Tomasz Michalec (2):
> > MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride
> > protocol
> > MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to
> > SdMmcOverride
> >
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 6 +
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 62 +++++-
> > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 12 +-
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 215
> > ++++++++++++++------
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 57 +++++-
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 18 +-
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 108 ++++++++-
> > -
> > 7 files changed, 383 insertions(+), 95 deletions(-)
> >
> > --
> > 2.7.4
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 0/4] SdMmcOverride extension
2018-10-12 5:33 ` Marcin Wojtas
@ 2018-10-12 12:48 ` Wu, Hao A
2018-10-12 12:50 ` Marcin Wojtas
0 siblings, 1 reply; 47+ messages in thread
From: Wu, Hao A @ 2018-10-12 12:48 UTC (permalink / raw)
To: Marcin Wojtas
Cc: edk2-devel-01, Tian, Feng, Kinney, Michael D, Gao, Liming,
Leif Lindholm, Ard Biesheuvel, nadavh@marvell.com,
jsd@semihalf.com, Tomasz Michalec
> -----Original Message-----
> From: Marcin Wojtas [mailto:mw@semihalf.com]
> Sent: Friday, October 12, 2018 1:33 PM
> To: Wu, Hao A
> Cc: edk2-devel-01; Tian, Feng; Kinney, Michael D; Gao, Liming; Leif Lindholm;
> Ard Biesheuvel; nadavh@marvell.com; jsd@semihalf.com; Tomasz Michalec
> Subject: Re: [PATCH v2 0/4] SdMmcOverride extension
>
> Hi Hao,
>
> pt., 12 paź 2018 o 07:25 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
> >
> > Hi Marcin,
> >
> > Please grant me some time for this series.
> >
> > Since I found that the extension of the SdMmc override protocol (mainly
> > the 3rd and 4th patch of the series) may have something overlaps with a
> > (internal) request to configure the driver strength parameter and operating
> > clock frequency of the SD/EMMC devices.
> >
> > For the (driver strength/operating freq) customize, we already have a
> > proposal on the way. So I am wondering if you could grant me some time
> to
> > investigate whether both the cases can be addressed together based on
> your
> > proposed patch.
> >
>
> Sure. I'm only wondering if it's not best to collect all remarks and
> maybe update to v3 both edk2 and edk2-platforms sides (so far the
> issues have been not critical, such as typos, parameters' names,
> etc.). In the meantime you would be able to validate if the solution
> is sufficient for you as well. What do you think? When do you expect
> to be able to look at it vs your internal requirements more deeply?
>
> Best regards,
> Marcin
I think you can hold the new version of the patch if the feedbacks do not
lead to considerable changes. At this moment, I can barely take time for
the evaluation. I think I will be able to fully shift to this in about 2
weeks. Does it sound acceptable to you with regard to the urgency level
for the series?
I will try my best to move up the process. Sorry again for the possible
delay.
Best Regards,
Hao Wu
>
>
> > Thanks in advance.
> >
> > Best Regards,
> > Hao Wu
> >
> >
> > > -----Original Message-----
> > > From: Marcin Wojtas [mailto:mw@semihalf.com]
> > > Sent: Friday, October 05, 2018 9:25 PM
> > > To: edk2-devel@lists.01.org
> > > Cc: Tian, Feng; Kinney, Michael D; Gao, Liming; leif.lindholm@linaro.org;
> Wu,
> > > Hao A; ard.biesheuvel@linaro.org; nadavh@marvell.com;
> > > mw@semihalf.com; jsd@semihalf.com; tm@semihalf.com
> > > Subject: [PATCH v2 0/4] SdMmcOverride extension
> > >
> > > Hi,
> > >
> > > This is the second version of the patchset. Initial one was
> > > interleaved with the fixes, which after split got already merged.
> > > The biggest change is - resigning from the new callbacks
> > > and extending parameter lists of both NotifyPhase and Capability
> > > routines.
> > >
> > > Patches are available in the github:
> > > https://github.com/MarvellEmbeddedProcessors/edk2-open-
> > > platform/commits/sdmmc-override-upstream-r20181005
> > >
> > > Please note that extending SdMmcOverride protocol was impacting
> > > so far the only user of it (Synquacer controller). In paralel
> > > edk2-platforms patchset, a patch can be found:
> > > ("Silicon/SynQuacer/PlatformDxe: adjust to updated SdMmcOverride")
> > > which immunizes for above and future extensions of the protocol:
> > > https://github.com/MarvellEmbeddedProcessors/edk2-open-
> > > platform/commits/xenon-upstream-r20181005
> > >
> > > I'm looking forward to the comments and remarks.
> > >
> > > Best regards,
> > > Marcin
> > >
> > > Changelog:
> > > v1 -> v2
> > > * Rebase onto newest master
> > > * 1/4 [new patch] - preparation for extending NotifyPhase
> > > * 2/4 - UhsSignaling as a part of NotifyPhase
> > > * 3/4 - SwitchClockFreqPost as a part of NotifyPhase
> > > * 4/4 - Allow updating BaseClkFreq via Capability instead of the
> > > independent callback.
> > >
> > > Marcin Wojtas (2):
> > > MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in
> > > NotifyPhase
> > > MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequency
> > >
> > > Tomasz Michalec (2):
> > > MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride
> > > protocol
> > > MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to
> > > SdMmcOverride
> > >
> > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 6 +
> > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 62 +++++-
> > > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 12 +-
> > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 215
> > > ++++++++++++++------
> > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 57 +++++-
> > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 18 +-
> > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 108
> ++++++++-
> > > -
> > > 7 files changed, 383 insertions(+), 95 deletions(-)
> > >
> > > --
> > > 2.7.4
> >
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 0/4] SdMmcOverride extension
2018-10-12 12:48 ` Wu, Hao A
@ 2018-10-12 12:50 ` Marcin Wojtas
2018-10-25 12:43 ` Marcin Wojtas
0 siblings, 1 reply; 47+ messages in thread
From: Marcin Wojtas @ 2018-10-12 12:50 UTC (permalink / raw)
To: hao.a.wu
Cc: edk2-devel-01, Tian, Feng, Kinney, Michael D, Gao, Liming,
Leif Lindholm, Ard Biesheuvel, nadavh, jsd@semihalf.com,
Tomasz Michalec
pt., 12 paź 2018 o 14:48 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
>
> > -----Original Message-----
> > From: Marcin Wojtas [mailto:mw@semihalf.com]
> > Sent: Friday, October 12, 2018 1:33 PM
> > To: Wu, Hao A
> > Cc: edk2-devel-01; Tian, Feng; Kinney, Michael D; Gao, Liming; Leif Lindholm;
> > Ard Biesheuvel; nadavh@marvell.com; jsd@semihalf.com; Tomasz Michalec
> > Subject: Re: [PATCH v2 0/4] SdMmcOverride extension
> >
> > Hi Hao,
> >
> > pt., 12 paź 2018 o 07:25 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
> > >
> > > Hi Marcin,
> > >
> > > Please grant me some time for this series.
> > >
> > > Since I found that the extension of the SdMmc override protocol (mainly
> > > the 3rd and 4th patch of the series) may have something overlaps with a
> > > (internal) request to configure the driver strength parameter and operating
> > > clock frequency of the SD/EMMC devices.
> > >
> > > For the (driver strength/operating freq) customize, we already have a
> > > proposal on the way. So I am wondering if you could grant me some time
> > to
> > > investigate whether both the cases can be addressed together based on
> > your
> > > proposed patch.
> > >
> >
> > Sure. I'm only wondering if it's not best to collect all remarks and
> > maybe update to v3 both edk2 and edk2-platforms sides (so far the
> > issues have been not critical, such as typos, parameters' names,
> > etc.). In the meantime you would be able to validate if the solution
> > is sufficient for you as well. What do you think? When do you expect
> > to be able to look at it vs your internal requirements more deeply?
> >
> > Best regards,
> > Marcin
>
> I think you can hold the new version of the patch if the feedbacks do not
> lead to considerable changes. At this moment, I can barely take time for
> the evaluation. I think I will be able to fully shift to this in about 2
> weeks. Does it sound acceptable to you with regard to the urgency level
> for the series?
>
> I will try my best to move up the process. Sorry again for the possible
> delay.
I will proceed with other remaining items for my platforms and allow
myself to ping you about status around end of October :)
Best regards,
Marcin
>
> >
> >
> > > Thanks in advance.
> > >
> > > Best Regards,
> > > Hao Wu
> > >
> > >
> > > > -----Original Message-----
> > > > From: Marcin Wojtas [mailto:mw@semihalf.com]
> > > > Sent: Friday, October 05, 2018 9:25 PM
> > > > To: edk2-devel@lists.01.org
> > > > Cc: Tian, Feng; Kinney, Michael D; Gao, Liming; leif.lindholm@linaro.org;
> > Wu,
> > > > Hao A; ard.biesheuvel@linaro.org; nadavh@marvell.com;
> > > > mw@semihalf.com; jsd@semihalf.com; tm@semihalf.com
> > > > Subject: [PATCH v2 0/4] SdMmcOverride extension
> > > >
> > > > Hi,
> > > >
> > > > This is the second version of the patchset. Initial one was
> > > > interleaved with the fixes, which after split got already merged.
> > > > The biggest change is - resigning from the new callbacks
> > > > and extending parameter lists of both NotifyPhase and Capability
> > > > routines.
> > > >
> > > > Patches are available in the github:
> > > > https://github.com/MarvellEmbeddedProcessors/edk2-open-
> > > > platform/commits/sdmmc-override-upstream-r20181005
> > > >
> > > > Please note that extending SdMmcOverride protocol was impacting
> > > > so far the only user of it (Synquacer controller). In paralel
> > > > edk2-platforms patchset, a patch can be found:
> > > > ("Silicon/SynQuacer/PlatformDxe: adjust to updated SdMmcOverride")
> > > > which immunizes for above and future extensions of the protocol:
> > > > https://github.com/MarvellEmbeddedProcessors/edk2-open-
> > > > platform/commits/xenon-upstream-r20181005
> > > >
> > > > I'm looking forward to the comments and remarks.
> > > >
> > > > Best regards,
> > > > Marcin
> > > >
> > > > Changelog:
> > > > v1 -> v2
> > > > * Rebase onto newest master
> > > > * 1/4 [new patch] - preparation for extending NotifyPhase
> > > > * 2/4 - UhsSignaling as a part of NotifyPhase
> > > > * 3/4 - SwitchClockFreqPost as a part of NotifyPhase
> > > > * 4/4 - Allow updating BaseClkFreq via Capability instead of the
> > > > independent callback.
> > > >
> > > > Marcin Wojtas (2):
> > > > MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in
> > > > NotifyPhase
> > > > MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequency
> > > >
> > > > Tomasz Michalec (2):
> > > > MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride
> > > > protocol
> > > > MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to
> > > > SdMmcOverride
> > > >
> > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 6 +
> > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 62 +++++-
> > > > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 12 +-
> > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 215
> > > > ++++++++++++++------
> > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 57 +++++-
> > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 18 +-
> > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 108
> > ++++++++-
> > > > -
> > > > 7 files changed, 383 insertions(+), 95 deletions(-)
> > > >
> > > > --
> > > > 2.7.4
> > >
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-12 5:06 ` Marcin Wojtas
@ 2018-10-12 15:55 ` Ard Biesheuvel
2018-10-12 16:04 ` Marcin Wojtas
0 siblings, 1 reply; 47+ messages in thread
From: Ard Biesheuvel @ 2018-10-12 15:55 UTC (permalink / raw)
To: Marcin Wojtas
Cc: Wu, Hao A, Ni, Ruiyu, Tian, Feng, Tomasz Michalec, Eric Dong,
edk2-devel-01, Gao, Liming, Nadav Haklai, Kinney, Michael D,
Zeng, Star
On 12 October 2018 at 07:06, Marcin Wojtas <mw@semihalf.com> wrote:
> pt., 12 paź 2018 o 03:41 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
>>
>> > -----Original Message-----
>> > From: Marcin Wojtas [mailto:mw@semihalf.com]
>> > Sent: Thursday, October 11, 2018 11:43 PM
>> > To: Wu, Hao A
>> > Cc: Ni, Ruiyu; Ard Biesheuvel; Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-
>> > devel-01; Gao, Liming; nadavh@marvell.com; Kinney, Michael D; Zeng, Star
>> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add
>> > UhsSignaling to SdMmcOverride protocol
>> >
>> > wt., 9 paź 2018 o 13:51 Marcin Wojtas <mw@semihalf.com> napisał(a):
>> > >
>> > > wt., 9 paź 2018 o 13:45 Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> > napisał(a):
>> > > >
>> > > > On 9 October 2018 at 13:32, Marcin Wojtas <mw@semihalf.com> wrote:
>> > > > > wt., 9 paź 2018 o 13:28 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
>> > > > >>
>> > > > >> > -----Original Message-----
>> > > > >> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On
>> > Behalf Of Ard
>> > > > >> > Biesheuvel
>> > > > >> > Sent: Monday, October 08, 2018 11:10 PM
>> > > > >> > To: Marcin Wojtas; Ni, Ruiyu; Wu, Hao A
>> > > > >> > Cc: Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-devel-01; Gao,
>> > Liming;
>> > > > >> > Nadav Haklai; Kinney, Michael D; Zeng, Star
>> > > > >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe:
>> > Add
>> > > > >> > UhsSignaling to SdMmcOverride protocol
>> > > > >> >
>> > > > ...
>> > > > >> >
>> > > > >> > I suppose this is defined by the eMMC spec.
>> > > > >> >
>> > > > >> > Ruiyu, Hao, could you clarify? Are the host control 2 register values
>> > > > >> > for HS200/HS400 defined by the eMMC spec?
>> > > > >>
>> > > > >> Hi Ard and Marcin,
>> > > > >>
>> > > > >> As far as I know, the EMMC Electrical Standard Spec 5.1 (latest) does
>> > not
>> > > > >> mention on how to set the "UHS Mode Select" field of the Host
>> > Control 2
>> > > > >> Register when switching to HS200/HS400. (Actually, the EMMC spec
>> > does not
>> > > > >> mention Host Control 2 Register at all)
>> > > > >>
>> > > > >> When it comes to setting the bus mode for EMMC devices, the current
>> > > > >> implementation of the SdMmcPciHcDxe driver does a mapping when
>> > setting the
>> > > > >> Host Control 2 Register:
>> > > > >>
>> > > > >> EMMC High Speed SDR - Freq: 0-52 MHz, Data Rate: Single
>> > > > >> matches
>> > > > >> SD SDR25 - Freq: 0-50 MHz, Data Rate: Single
>> > > > >>
>> > > > >> EMMC High Speed DDR - Freq: 0-52 MHz, Data Rate: Dual
>> > > > >> matches
>> > > > >> SD DDR50 - Freq: 0-50 MHz, Data Rate: Dual
>> > > > >>
>> > > > >> EMMC HS200 - Freq: 0-200 MHz, Data Rate: Single
>> > > > >> matches
>> > > > >> SD SDR104 - Freq: 0-208 MHz, Data Rate: Single
>> > > > >>
>> > > > >> EMMC HS400 - Freq: 0-200 MHz, Data Rate: Dual
>> > > > >> matches
>> > > > >> SD None
>> > > > >>
>> > > > >> And there is no obvious counterpart for the EMMC HS400 mode in the
>> > SD
>> > > > >> spec. The driver currently sets the "UHS Mode Select" field to a
>> > reserved
>> > > > >> value 0x5.
>> > > > >>
>> > > > >
>> > > > > Thank you Hao, above is on par with what the default UhsSignaling
>> > > > > routine does in this patch. IMO especially in case the EMMC standard
>> > > > > is not unequivocal regarding UHS_MODE_SEL, I'd encourage to accept
>> > > > > some way of updating HostControl2 register, depending on the
>> > > > > implementation. What is your opinion Ard?
>> > > > >
>> > > >
>> > > > I would like to know where the current values in SdMmcPciHcDxe come
>> > > > from if they are not defined in any spec.
>> > > >
>> > > > How do we know which ones are the correct ones?
>> > >
>> > > Hao, can you justify used values?
>> > >
>> >
>> > Hi Hao,
>> >
>> > Can you please take a look at the UHS_MODE_SEL values source for eMMC?
>>
>> Hi Marcin,
>>
>> Sorry for the delayed response.
>>
>> For the current implementation of the SdMmcPciHcDxe driver, the selecting
>> of "UHS Mode Select" field value of the Host Control 2 Register is based
>> on a Max Clock Frequency & Data Rate (Single or Dual) matching
>> relationship between the:
>>
>> A. Table 3-6 of the SD Specifications Part 1 Physical Layer Simplified
>> Specification Version 4.10
>>
>> and
>>
>> B. Table 4 of the EMMC Electrical Standard Spec 5.1
>>
>> The matching details was included in my previous reply. The only missing
>> part is there seems no matching for the EMMC HS400 mode in the SD
>> specifications. For this case, we are currently using the same approach
>> with the Linux implementation, that is to set the "UHS Mode Select" to a
>> value of 0x5 (not standard).
>>
>
> Hao,
>
> Thanks a lot for the clarification.
>
> Ard,
>
> Knowing the numbers details, what is your view of the UhsSignaling handling?
>
I think it makes sense to be able to override the SD->MMC mapping for
HC2 attributes. But it seems to me that this mapping is rather ad-hoc
and so it should apply to all configuration that is inferred:
UhsSignalling does not quite cover it.
So I think the approach is correct, but we need a better name.
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-12 15:55 ` Ard Biesheuvel
@ 2018-10-12 16:04 ` Marcin Wojtas
2018-10-12 16:24 ` Ard Biesheuvel
0 siblings, 1 reply; 47+ messages in thread
From: Marcin Wojtas @ 2018-10-12 16:04 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: hao.a.wu, Ni, Ruiyu, Tian, Feng, Tomasz Michalec, eric.dong,
edk2-devel-01, Gao, Liming, nadavh, Kinney, Michael D, Zeng, Star
pt., 12 paź 2018 o 17:55 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
>
> On 12 October 2018 at 07:06, Marcin Wojtas <mw@semihalf.com> wrote:
> > pt., 12 paź 2018 o 03:41 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
> >>
> >> > -----Original Message-----
> >> > From: Marcin Wojtas [mailto:mw@semihalf.com]
> >> > Sent: Thursday, October 11, 2018 11:43 PM
> >> > To: Wu, Hao A
> >> > Cc: Ni, Ruiyu; Ard Biesheuvel; Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-
> >> > devel-01; Gao, Liming; nadavh@marvell.com; Kinney, Michael D; Zeng, Star
> >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add
> >> > UhsSignaling to SdMmcOverride protocol
> >> >
> >> > wt., 9 paź 2018 o 13:51 Marcin Wojtas <mw@semihalf.com> napisał(a):
> >> > >
> >> > > wt., 9 paź 2018 o 13:45 Ard Biesheuvel <ard.biesheuvel@linaro.org>
> >> > napisał(a):
> >> > > >
> >> > > > On 9 October 2018 at 13:32, Marcin Wojtas <mw@semihalf.com> wrote:
> >> > > > > wt., 9 paź 2018 o 13:28 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
> >> > > > >>
> >> > > > >> > -----Original Message-----
> >> > > > >> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On
> >> > Behalf Of Ard
> >> > > > >> > Biesheuvel
> >> > > > >> > Sent: Monday, October 08, 2018 11:10 PM
> >> > > > >> > To: Marcin Wojtas; Ni, Ruiyu; Wu, Hao A
> >> > > > >> > Cc: Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-devel-01; Gao,
> >> > Liming;
> >> > > > >> > Nadav Haklai; Kinney, Michael D; Zeng, Star
> >> > > > >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe:
> >> > Add
> >> > > > >> > UhsSignaling to SdMmcOverride protocol
> >> > > > >> >
> >> > > > ...
> >> > > > >> >
> >> > > > >> > I suppose this is defined by the eMMC spec.
> >> > > > >> >
> >> > > > >> > Ruiyu, Hao, could you clarify? Are the host control 2 register values
> >> > > > >> > for HS200/HS400 defined by the eMMC spec?
> >> > > > >>
> >> > > > >> Hi Ard and Marcin,
> >> > > > >>
> >> > > > >> As far as I know, the EMMC Electrical Standard Spec 5.1 (latest) does
> >> > not
> >> > > > >> mention on how to set the "UHS Mode Select" field of the Host
> >> > Control 2
> >> > > > >> Register when switching to HS200/HS400. (Actually, the EMMC spec
> >> > does not
> >> > > > >> mention Host Control 2 Register at all)
> >> > > > >>
> >> > > > >> When it comes to setting the bus mode for EMMC devices, the current
> >> > > > >> implementation of the SdMmcPciHcDxe driver does a mapping when
> >> > setting the
> >> > > > >> Host Control 2 Register:
> >> > > > >>
> >> > > > >> EMMC High Speed SDR - Freq: 0-52 MHz, Data Rate: Single
> >> > > > >> matches
> >> > > > >> SD SDR25 - Freq: 0-50 MHz, Data Rate: Single
> >> > > > >>
> >> > > > >> EMMC High Speed DDR - Freq: 0-52 MHz, Data Rate: Dual
> >> > > > >> matches
> >> > > > >> SD DDR50 - Freq: 0-50 MHz, Data Rate: Dual
> >> > > > >>
> >> > > > >> EMMC HS200 - Freq: 0-200 MHz, Data Rate: Single
> >> > > > >> matches
> >> > > > >> SD SDR104 - Freq: 0-208 MHz, Data Rate: Single
> >> > > > >>
> >> > > > >> EMMC HS400 - Freq: 0-200 MHz, Data Rate: Dual
> >> > > > >> matches
> >> > > > >> SD None
> >> > > > >>
> >> > > > >> And there is no obvious counterpart for the EMMC HS400 mode in the
> >> > SD
> >> > > > >> spec. The driver currently sets the "UHS Mode Select" field to a
> >> > reserved
> >> > > > >> value 0x5.
> >> > > > >>
> >> > > > >
> >> > > > > Thank you Hao, above is on par with what the default UhsSignaling
> >> > > > > routine does in this patch. IMO especially in case the EMMC standard
> >> > > > > is not unequivocal regarding UHS_MODE_SEL, I'd encourage to accept
> >> > > > > some way of updating HostControl2 register, depending on the
> >> > > > > implementation. What is your opinion Ard?
> >> > > > >
> >> > > >
> >> > > > I would like to know where the current values in SdMmcPciHcDxe come
> >> > > > from if they are not defined in any spec.
> >> > > >
> >> > > > How do we know which ones are the correct ones?
> >> > >
> >> > > Hao, can you justify used values?
> >> > >
> >> >
> >> > Hi Hao,
> >> >
> >> > Can you please take a look at the UHS_MODE_SEL values source for eMMC?
> >>
> >> Hi Marcin,
> >>
> >> Sorry for the delayed response.
> >>
> >> For the current implementation of the SdMmcPciHcDxe driver, the selecting
> >> of "UHS Mode Select" field value of the Host Control 2 Register is based
> >> on a Max Clock Frequency & Data Rate (Single or Dual) matching
> >> relationship between the:
> >>
> >> A. Table 3-6 of the SD Specifications Part 1 Physical Layer Simplified
> >> Specification Version 4.10
> >>
> >> and
> >>
> >> B. Table 4 of the EMMC Electrical Standard Spec 5.1
> >>
> >> The matching details was included in my previous reply. The only missing
> >> part is there seems no matching for the EMMC HS400 mode in the SD
> >> specifications. For this case, we are currently using the same approach
> >> with the Linux implementation, that is to set the "UHS Mode Select" to a
> >> value of 0x5 (not standard).
> >>
> >
> > Hao,
> >
> > Thanks a lot for the clarification.
> >
> > Ard,
> >
> > Knowing the numbers details, what is your view of the UhsSignaling handling?
> >
>
> I think it makes sense to be able to override the SD->MMC mapping for
> HC2 attributes. But it seems to me that this mapping is rather ad-hoc
> and so it should apply to all configuration that is inferred:
> UhsSignalling does not quite cover it.
>
> So I think the approach is correct, but we need a better name.
Do you mean to update more fields in HC2 than UHS_MODE_SEL?
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-12 16:04 ` Marcin Wojtas
@ 2018-10-12 16:24 ` Ard Biesheuvel
2018-10-12 16:49 ` Marcin Wojtas
0 siblings, 1 reply; 47+ messages in thread
From: Ard Biesheuvel @ 2018-10-12 16:24 UTC (permalink / raw)
To: Marcin Wojtas
Cc: Gao, Liming, Kinney, Michael D, Ni, Ruiyu, Tian, Feng,
Tomasz Michalec, Zeng, Star, edk2-devel-01, Eric Dong, Wu, Hao A,
Nadav Haklai
On Fri 12 Oct 2018 at 18:04, Marcin Wojtas <mw@semihalf.com> wrote:
>
> pt., 12 paź 2018 o 17:55 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
> >
> > On 12 October 2018 at 07:06, Marcin Wojtas <mw@semihalf.com> wrote:
> > > pt., 12 paź 2018 o 03:41 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
> > >>
> > >> > -----Original Message-----
> > >> > From: Marcin Wojtas [mailto:mw@semihalf.com]
> > >> > Sent: Thursday, October 11, 2018 11:43 PM
> > >> > To: Wu, Hao A
> > >> > Cc: Ni, Ruiyu; Ard Biesheuvel; Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-
> > >> > devel-01; Gao, Liming; nadavh@marvell.com; Kinney, Michael D; Zeng, Star
> > >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add
> > >> > UhsSignaling to SdMmcOverride protocol
> > >> >
> > >> > wt., 9 paź 2018 o 13:51 Marcin Wojtas <mw@semihalf.com> napisał(a):
> > >> > >
> > >> > > wt., 9 paź 2018 o 13:45 Ard Biesheuvel <ard.biesheuvel@linaro.org>
> > >> > napisał(a):
> > >> > > >
> > >> > > > On 9 October 2018 at 13:32, Marcin Wojtas <mw@semihalf.com> wrote:
> > >> > > > > wt., 9 paź 2018 o 13:28 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
> > >> > > > >>
> > >> > > > >> > -----Original Message-----
> > >> > > > >> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On
> > >> > Behalf Of Ard
> > >> > > > >> > Biesheuvel
> > >> > > > >> > Sent: Monday, October 08, 2018 11:10 PM
> > >> > > > >> > To: Marcin Wojtas; Ni, Ruiyu; Wu, Hao A
> > >> > > > >> > Cc: Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-devel-01; Gao,
> > >> > Liming;
> > >> > > > >> > Nadav Haklai; Kinney, Michael D; Zeng, Star
> > >> > > > >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe:
> > >> > Add
> > >> > > > >> > UhsSignaling to SdMmcOverride protocol
> > >> > > > >> >
> > >> > > > ...
> > >> > > > >> >
> > >> > > > >> > I suppose this is defined by the eMMC spec.
> > >> > > > >> >
> > >> > > > >> > Ruiyu, Hao, could you clarify? Are the host control 2 register values
> > >> > > > >> > for HS200/HS400 defined by the eMMC spec?
> > >> > > > >>
> > >> > > > >> Hi Ard and Marcin,
> > >> > > > >>
> > >> > > > >> As far as I know, the EMMC Electrical Standard Spec 5.1 (latest) does
> > >> > not
> > >> > > > >> mention on how to set the "UHS Mode Select" field of the Host
> > >> > Control 2
> > >> > > > >> Register when switching to HS200/HS400. (Actually, the EMMC spec
> > >> > does not
> > >> > > > >> mention Host Control 2 Register at all)
> > >> > > > >>
> > >> > > > >> When it comes to setting the bus mode for EMMC devices, the current
> > >> > > > >> implementation of the SdMmcPciHcDxe driver does a mapping when
> > >> > setting the
> > >> > > > >> Host Control 2 Register:
> > >> > > > >>
> > >> > > > >> EMMC High Speed SDR - Freq: 0-52 MHz, Data Rate: Single
> > >> > > > >> matches
> > >> > > > >> SD SDR25 - Freq: 0-50 MHz, Data Rate: Single
> > >> > > > >>
> > >> > > > >> EMMC High Speed DDR - Freq: 0-52 MHz, Data Rate: Dual
> > >> > > > >> matches
> > >> > > > >> SD DDR50 - Freq: 0-50 MHz, Data Rate: Dual
> > >> > > > >>
> > >> > > > >> EMMC HS200 - Freq: 0-200 MHz, Data Rate: Single
> > >> > > > >> matches
> > >> > > > >> SD SDR104 - Freq: 0-208 MHz, Data Rate: Single
> > >> > > > >>
> > >> > > > >> EMMC HS400 - Freq: 0-200 MHz, Data Rate: Dual
> > >> > > > >> matches
> > >> > > > >> SD None
> > >> > > > >>
> > >> > > > >> And there is no obvious counterpart for the EMMC HS400 mode in the
> > >> > SD
> > >> > > > >> spec. The driver currently sets the "UHS Mode Select" field to a
> > >> > reserved
> > >> > > > >> value 0x5.
> > >> > > > >>
> > >> > > > >
> > >> > > > > Thank you Hao, above is on par with what the default UhsSignaling
> > >> > > > > routine does in this patch. IMO especially in case the EMMC standard
> > >> > > > > is not unequivocal regarding UHS_MODE_SEL, I'd encourage to accept
> > >> > > > > some way of updating HostControl2 register, depending on the
> > >> > > > > implementation. What is your opinion Ard?
> > >> > > > >
> > >> > > >
> > >> > > > I would like to know where the current values in SdMmcPciHcDxe come
> > >> > > > from if they are not defined in any spec.
> > >> > > >
> > >> > > > How do we know which ones are the correct ones?
> > >> > >
> > >> > > Hao, can you justify used values?
> > >> > >
> > >> >
> > >> > Hi Hao,
> > >> >
> > >> > Can you please take a look at the UHS_MODE_SEL values source for eMMC?
> > >>
> > >> Hi Marcin,
> > >>
> > >> Sorry for the delayed response.
> > >>
> > >> For the current implementation of the SdMmcPciHcDxe driver, the selecting
> > >> of "UHS Mode Select" field value of the Host Control 2 Register is based
> > >> on a Max Clock Frequency & Data Rate (Single or Dual) matching
> > >> relationship between the:
> > >>
> > >> A. Table 3-6 of the SD Specifications Part 1 Physical Layer Simplified
> > >> Specification Version 4.10
> > >>
> > >> and
> > >>
> > >> B. Table 4 of the EMMC Electrical Standard Spec 5.1
> > >>
> > >> The matching details was included in my previous reply. The only missing
> > >> part is there seems no matching for the EMMC HS400 mode in the SD
> > >> specifications. For this case, we are currently using the same approach
> > >> with the Linux implementation, that is to set the "UHS Mode Select" to a
> > >> value of 0x5 (not standard).
> > >>
> > >
> > > Hao,
> > >
> > > Thanks a lot for the clarification.
> > >
> > > Ard,
> > >
> > > Knowing the numbers details, what is your view of the UhsSignaling handling?
> > >
> >
> > I think it makes sense to be able to override the SD->MMC mapping for
> > HC2 attributes. But it seems to me that this mapping is rather ad-hoc
> > and so it should apply to all configuration that is inferred:
> > UhsSignalling does not quite cover it.
> >
> > So I think the approach is correct, but we need a better name.
>
> Do you mean to update more fields in HC2 than UHS_MODE_SEL?
AIUI the EMMC spec does not mention HC2 at all, and yet we have to set
it to a sane value, and we are currently using fuzzy logic for it.
Or are the other fields less ambiguous?
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-12 16:24 ` Ard Biesheuvel
@ 2018-10-12 16:49 ` Marcin Wojtas
0 siblings, 0 replies; 47+ messages in thread
From: Marcin Wojtas @ 2018-10-12 16:49 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: Gao, Liming, Kinney, Michael D, Ni, Ruiyu, Tian, Feng,
Tomasz Michalec, Zeng, Star, edk2-devel-01, eric.dong, hao.a.wu,
nadavh
pt., 12 paź 2018 o 18:24 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
>
> On Fri 12 Oct 2018 at 18:04, Marcin Wojtas <mw@semihalf.com> wrote:
> >
> > pt., 12 paź 2018 o 17:55 Ard Biesheuvel <ard.biesheuvel@linaro.org> napisał(a):
> > >
> > > On 12 October 2018 at 07:06, Marcin Wojtas <mw@semihalf.com> wrote:
> > > > pt., 12 paź 2018 o 03:41 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
> > > >>
> > > >> > -----Original Message-----
> > > >> > From: Marcin Wojtas [mailto:mw@semihalf.com]
> > > >> > Sent: Thursday, October 11, 2018 11:43 PM
> > > >> > To: Wu, Hao A
> > > >> > Cc: Ni, Ruiyu; Ard Biesheuvel; Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-
> > > >> > devel-01; Gao, Liming; nadavh@marvell.com; Kinney, Michael D; Zeng, Star
> > > >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add
> > > >> > UhsSignaling to SdMmcOverride protocol
> > > >> >
> > > >> > wt., 9 paź 2018 o 13:51 Marcin Wojtas <mw@semihalf.com> napisał(a):
> > > >> > >
> > > >> > > wt., 9 paź 2018 o 13:45 Ard Biesheuvel <ard.biesheuvel@linaro.org>
> > > >> > napisał(a):
> > > >> > > >
> > > >> > > > On 9 October 2018 at 13:32, Marcin Wojtas <mw@semihalf.com> wrote:
> > > >> > > > > wt., 9 paź 2018 o 13:28 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
> > > >> > > > >>
> > > >> > > > >> > -----Original Message-----
> > > >> > > > >> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On
> > > >> > Behalf Of Ard
> > > >> > > > >> > Biesheuvel
> > > >> > > > >> > Sent: Monday, October 08, 2018 11:10 PM
> > > >> > > > >> > To: Marcin Wojtas; Ni, Ruiyu; Wu, Hao A
> > > >> > > > >> > Cc: Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-devel-01; Gao,
> > > >> > Liming;
> > > >> > > > >> > Nadav Haklai; Kinney, Michael D; Zeng, Star
> > > >> > > > >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe:
> > > >> > Add
> > > >> > > > >> > UhsSignaling to SdMmcOverride protocol
> > > >> > > > >> >
> > > >> > > > ...
> > > >> > > > >> >
> > > >> > > > >> > I suppose this is defined by the eMMC spec.
> > > >> > > > >> >
> > > >> > > > >> > Ruiyu, Hao, could you clarify? Are the host control 2 register values
> > > >> > > > >> > for HS200/HS400 defined by the eMMC spec?
> > > >> > > > >>
> > > >> > > > >> Hi Ard and Marcin,
> > > >> > > > >>
> > > >> > > > >> As far as I know, the EMMC Electrical Standard Spec 5.1 (latest) does
> > > >> > not
> > > >> > > > >> mention on how to set the "UHS Mode Select" field of the Host
> > > >> > Control 2
> > > >> > > > >> Register when switching to HS200/HS400. (Actually, the EMMC spec
> > > >> > does not
> > > >> > > > >> mention Host Control 2 Register at all)
> > > >> > > > >>
> > > >> > > > >> When it comes to setting the bus mode for EMMC devices, the current
> > > >> > > > >> implementation of the SdMmcPciHcDxe driver does a mapping when
> > > >> > setting the
> > > >> > > > >> Host Control 2 Register:
> > > >> > > > >>
> > > >> > > > >> EMMC High Speed SDR - Freq: 0-52 MHz, Data Rate: Single
> > > >> > > > >> matches
> > > >> > > > >> SD SDR25 - Freq: 0-50 MHz, Data Rate: Single
> > > >> > > > >>
> > > >> > > > >> EMMC High Speed DDR - Freq: 0-52 MHz, Data Rate: Dual
> > > >> > > > >> matches
> > > >> > > > >> SD DDR50 - Freq: 0-50 MHz, Data Rate: Dual
> > > >> > > > >>
> > > >> > > > >> EMMC HS200 - Freq: 0-200 MHz, Data Rate: Single
> > > >> > > > >> matches
> > > >> > > > >> SD SDR104 - Freq: 0-208 MHz, Data Rate: Single
> > > >> > > > >>
> > > >> > > > >> EMMC HS400 - Freq: 0-200 MHz, Data Rate: Dual
> > > >> > > > >> matches
> > > >> > > > >> SD None
> > > >> > > > >>
> > > >> > > > >> And there is no obvious counterpart for the EMMC HS400 mode in the
> > > >> > SD
> > > >> > > > >> spec. The driver currently sets the "UHS Mode Select" field to a
> > > >> > reserved
> > > >> > > > >> value 0x5.
> > > >> > > > >>
> > > >> > > > >
> > > >> > > > > Thank you Hao, above is on par with what the default UhsSignaling
> > > >> > > > > routine does in this patch. IMO especially in case the EMMC standard
> > > >> > > > > is not unequivocal regarding UHS_MODE_SEL, I'd encourage to accept
> > > >> > > > > some way of updating HostControl2 register, depending on the
> > > >> > > > > implementation. What is your opinion Ard?
> > > >> > > > >
> > > >> > > >
> > > >> > > > I would like to know where the current values in SdMmcPciHcDxe come
> > > >> > > > from if they are not defined in any spec.
> > > >> > > >
> > > >> > > > How do we know which ones are the correct ones?
> > > >> > >
> > > >> > > Hao, can you justify used values?
> > > >> > >
> > > >> >
> > > >> > Hi Hao,
> > > >> >
> > > >> > Can you please take a look at the UHS_MODE_SEL values source for eMMC?
> > > >>
> > > >> Hi Marcin,
> > > >>
> > > >> Sorry for the delayed response.
> > > >>
> > > >> For the current implementation of the SdMmcPciHcDxe driver, the selecting
> > > >> of "UHS Mode Select" field value of the Host Control 2 Register is based
> > > >> on a Max Clock Frequency & Data Rate (Single or Dual) matching
> > > >> relationship between the:
> > > >>
> > > >> A. Table 3-6 of the SD Specifications Part 1 Physical Layer Simplified
> > > >> Specification Version 4.10
> > > >>
> > > >> and
> > > >>
> > > >> B. Table 4 of the EMMC Electrical Standard Spec 5.1
> > > >>
> > > >> The matching details was included in my previous reply. The only missing
> > > >> part is there seems no matching for the EMMC HS400 mode in the SD
> > > >> specifications. For this case, we are currently using the same approach
> > > >> with the Linux implementation, that is to set the "UHS Mode Select" to a
> > > >> value of 0x5 (not standard).
> > > >>
> > > >
> > > > Hao,
> > > >
> > > > Thanks a lot for the clarification.
> > > >
> > > > Ard,
> > > >
> > > > Knowing the numbers details, what is your view of the UhsSignaling handling?
> > > >
> > >
> > > I think it makes sense to be able to override the SD->MMC mapping for
> > > HC2 attributes. But it seems to me that this mapping is rather ad-hoc
> > > and so it should apply to all configuration that is inferred:
> > > UhsSignalling does not quite cover it.
> > >
> > > So I think the approach is correct, but we need a better name.
> >
> > Do you mean to update more fields in HC2 than UHS_MODE_SEL?
>
> AIUI the EMMC spec does not mention HC2 at all, and yet we have to set
> it to a sane value, and we are currently using fuzzy logic for it.
> Or are the other fields less ambiguous?
I don't think so. How about renaming the phase type to:
EdkiiSdMmcBusSpeedModeSelect?
Best regards,
Marcin
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 0/4] SdMmcOverride extension
2018-10-12 12:50 ` Marcin Wojtas
@ 2018-10-25 12:43 ` Marcin Wojtas
2018-10-26 7:22 ` Wu, Hao A
0 siblings, 1 reply; 47+ messages in thread
From: Marcin Wojtas @ 2018-10-25 12:43 UTC (permalink / raw)
To: hao.a.wu
Cc: edk2-devel-01, Tian, Feng, Kinney, Michael D, Gao, Liming,
Leif Lindholm, Ard Biesheuvel, nadavh, jsd@semihalf.com,
Tomasz Michalec
Hi Hao,
Were you able to find time for evaluating my patchset?
Best regards,
Marcin
pt., 12 paź 2018 o 14:50 Marcin Wojtas <mw@semihalf.com> napisał(a):
>
> pt., 12 paź 2018 o 14:48 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
> >
> > > -----Original Message-----
> > > From: Marcin Wojtas [mailto:mw@semihalf.com]
> > > Sent: Friday, October 12, 2018 1:33 PM
> > > To: Wu, Hao A
> > > Cc: edk2-devel-01; Tian, Feng; Kinney, Michael D; Gao, Liming; Leif Lindholm;
> > > Ard Biesheuvel; nadavh@marvell.com; jsd@semihalf.com; Tomasz Michalec
> > > Subject: Re: [PATCH v2 0/4] SdMmcOverride extension
> > >
> > > Hi Hao,
> > >
> > > pt., 12 paź 2018 o 07:25 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
> > > >
> > > > Hi Marcin,
> > > >
> > > > Please grant me some time for this series.
> > > >
> > > > Since I found that the extension of the SdMmc override protocol (mainly
> > > > the 3rd and 4th patch of the series) may have something overlaps with a
> > > > (internal) request to configure the driver strength parameter and operating
> > > > clock frequency of the SD/EMMC devices.
> > > >
> > > > For the (driver strength/operating freq) customize, we already have a
> > > > proposal on the way. So I am wondering if you could grant me some time
> > > to
> > > > investigate whether both the cases can be addressed together based on
> > > your
> > > > proposed patch.
> > > >
> > >
> > > Sure. I'm only wondering if it's not best to collect all remarks and
> > > maybe update to v3 both edk2 and edk2-platforms sides (so far the
> > > issues have been not critical, such as typos, parameters' names,
> > > etc.). In the meantime you would be able to validate if the solution
> > > is sufficient for you as well. What do you think? When do you expect
> > > to be able to look at it vs your internal requirements more deeply?
> > >
> > > Best regards,
> > > Marcin
> >
> > I think you can hold the new version of the patch if the feedbacks do not
> > lead to considerable changes. At this moment, I can barely take time for
> > the evaluation. I think I will be able to fully shift to this in about 2
> > weeks. Does it sound acceptable to you with regard to the urgency level
> > for the series?
> >
> > I will try my best to move up the process. Sorry again for the possible
> > delay.
>
> I will proceed with other remaining items for my platforms and allow
> myself to ping you about status around end of October :)
>
> Best regards,
> Marcin
>
> >
> > >
> > >
> > > > Thanks in advance.
> > > >
> > > > Best Regards,
> > > > Hao Wu
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: Marcin Wojtas [mailto:mw@semihalf.com]
> > > > > Sent: Friday, October 05, 2018 9:25 PM
> > > > > To: edk2-devel@lists.01.org
> > > > > Cc: Tian, Feng; Kinney, Michael D; Gao, Liming; leif.lindholm@linaro.org;
> > > Wu,
> > > > > Hao A; ard.biesheuvel@linaro.org; nadavh@marvell.com;
> > > > > mw@semihalf.com; jsd@semihalf.com; tm@semihalf.com
> > > > > Subject: [PATCH v2 0/4] SdMmcOverride extension
> > > > >
> > > > > Hi,
> > > > >
> > > > > This is the second version of the patchset. Initial one was
> > > > > interleaved with the fixes, which after split got already merged.
> > > > > The biggest change is - resigning from the new callbacks
> > > > > and extending parameter lists of both NotifyPhase and Capability
> > > > > routines.
> > > > >
> > > > > Patches are available in the github:
> > > > > https://github.com/MarvellEmbeddedProcessors/edk2-open-
> > > > > platform/commits/sdmmc-override-upstream-r20181005
> > > > >
> > > > > Please note that extending SdMmcOverride protocol was impacting
> > > > > so far the only user of it (Synquacer controller). In paralel
> > > > > edk2-platforms patchset, a patch can be found:
> > > > > ("Silicon/SynQuacer/PlatformDxe: adjust to updated SdMmcOverride")
> > > > > which immunizes for above and future extensions of the protocol:
> > > > > https://github.com/MarvellEmbeddedProcessors/edk2-open-
> > > > > platform/commits/xenon-upstream-r20181005
> > > > >
> > > > > I'm looking forward to the comments and remarks.
> > > > >
> > > > > Best regards,
> > > > > Marcin
> > > > >
> > > > > Changelog:
> > > > > v1 -> v2
> > > > > * Rebase onto newest master
> > > > > * 1/4 [new patch] - preparation for extending NotifyPhase
> > > > > * 2/4 - UhsSignaling as a part of NotifyPhase
> > > > > * 3/4 - SwitchClockFreqPost as a part of NotifyPhase
> > > > > * 4/4 - Allow updating BaseClkFreq via Capability instead of the
> > > > > independent callback.
> > > > >
> > > > > Marcin Wojtas (2):
> > > > > MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in
> > > > > NotifyPhase
> > > > > MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequency
> > > > >
> > > > > Tomasz Michalec (2):
> > > > > MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride
> > > > > protocol
> > > > > MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to
> > > > > SdMmcOverride
> > > > >
> > > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 6 +
> > > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 62 +++++-
> > > > > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 12 +-
> > > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 215
> > > > > ++++++++++++++------
> > > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 57 +++++-
> > > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 18 +-
> > > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 108
> > > ++++++++-
> > > > > -
> > > > > 7 files changed, 383 insertions(+), 95 deletions(-)
> > > > >
> > > > > --
> > > > > 2.7.4
> > > >
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 0/4] SdMmcOverride extension
2018-10-25 12:43 ` Marcin Wojtas
@ 2018-10-26 7:22 ` Wu, Hao A
0 siblings, 0 replies; 47+ messages in thread
From: Wu, Hao A @ 2018-10-26 7:22 UTC (permalink / raw)
To: Marcin Wojtas
Cc: edk2-devel-01, Tian, Feng, Kinney, Michael D, Gao, Liming,
Leif Lindholm, Ard Biesheuvel, nadavh@marvell.com,
jsd@semihalf.com, Tomasz Michalec
> -----Original Message-----
> From: Marcin Wojtas [mailto:mw@semihalf.com]
> Sent: Thursday, October 25, 2018 8:43 PM
> To: Wu, Hao A
> Cc: edk2-devel-01; Tian, Feng; Kinney, Michael D; Gao, Liming; Leif Lindholm;
> Ard Biesheuvel; nadavh@marvell.com; jsd@semihalf.com; Tomasz Michalec
> Subject: Re: [PATCH v2 0/4] SdMmcOverride extension
>
> Hi Hao,
>
> Were you able to find time for evaluating my patchset?
Hi Marcin,
I plan to start looking into your series sometime next week.
I will give you some updates then.
Best Regards,
Hao Wu
>
> Best regards,
> Marcin
> pt., 12 paź 2018 o 14:50 Marcin Wojtas <mw@semihalf.com> napisał(a):
> >
> > pt., 12 paź 2018 o 14:48 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
> > >
> > > > -----Original Message-----
> > > > From: Marcin Wojtas [mailto:mw@semihalf.com]
> > > > Sent: Friday, October 12, 2018 1:33 PM
> > > > To: Wu, Hao A
> > > > Cc: edk2-devel-01; Tian, Feng; Kinney, Michael D; Gao, Liming; Leif
> Lindholm;
> > > > Ard Biesheuvel; nadavh@marvell.com; jsd@semihalf.com; Tomasz
> Michalec
> > > > Subject: Re: [PATCH v2 0/4] SdMmcOverride extension
> > > >
> > > > Hi Hao,
> > > >
> > > > pt., 12 paź 2018 o 07:25 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
> > > > >
> > > > > Hi Marcin,
> > > > >
> > > > > Please grant me some time for this series.
> > > > >
> > > > > Since I found that the extension of the SdMmc override protocol
> (mainly
> > > > > the 3rd and 4th patch of the series) may have something overlaps
> with a
> > > > > (internal) request to configure the driver strength parameter and
> operating
> > > > > clock frequency of the SD/EMMC devices.
> > > > >
> > > > > For the (driver strength/operating freq) customize, we already have a
> > > > > proposal on the way. So I am wondering if you could grant me some
> time
> > > > to
> > > > > investigate whether both the cases can be addressed together based
> on
> > > > your
> > > > > proposed patch.
> > > > >
> > > >
> > > > Sure. I'm only wondering if it's not best to collect all remarks and
> > > > maybe update to v3 both edk2 and edk2-platforms sides (so far the
> > > > issues have been not critical, such as typos, parameters' names,
> > > > etc.). In the meantime you would be able to validate if the solution
> > > > is sufficient for you as well. What do you think? When do you expect
> > > > to be able to look at it vs your internal requirements more deeply?
> > > >
> > > > Best regards,
> > > > Marcin
> > >
> > > I think you can hold the new version of the patch if the feedbacks do not
> > > lead to considerable changes. At this moment, I can barely take time for
> > > the evaluation. I think I will be able to fully shift to this in about 2
> > > weeks. Does it sound acceptable to you with regard to the urgency level
> > > for the series?
> > >
> > > I will try my best to move up the process. Sorry again for the possible
> > > delay.
> >
> > I will proceed with other remaining items for my platforms and allow
> > myself to ping you about status around end of October :)
> >
> > Best regards,
> > Marcin
> >
> > >
> > > >
> > > >
> > > > > Thanks in advance.
> > > > >
> > > > > Best Regards,
> > > > > Hao Wu
> > > > >
> > > > >
> > > > > > -----Original Message-----
> > > > > > From: Marcin Wojtas [mailto:mw@semihalf.com]
> > > > > > Sent: Friday, October 05, 2018 9:25 PM
> > > > > > To: edk2-devel@lists.01.org
> > > > > > Cc: Tian, Feng; Kinney, Michael D; Gao, Liming;
> leif.lindholm@linaro.org;
> > > > Wu,
> > > > > > Hao A; ard.biesheuvel@linaro.org; nadavh@marvell.com;
> > > > > > mw@semihalf.com; jsd@semihalf.com; tm@semihalf.com
> > > > > > Subject: [PATCH v2 0/4] SdMmcOverride extension
> > > > > >
> > > > > > Hi,
> > > > > >
> > > > > > This is the second version of the patchset. Initial one was
> > > > > > interleaved with the fixes, which after split got already merged.
> > > > > > The biggest change is - resigning from the new callbacks
> > > > > > and extending parameter lists of both NotifyPhase and Capability
> > > > > > routines.
> > > > > >
> > > > > > Patches are available in the github:
> > > > > > https://github.com/MarvellEmbeddedProcessors/edk2-open-
> > > > > > platform/commits/sdmmc-override-upstream-r20181005
> > > > > >
> > > > > > Please note that extending SdMmcOverride protocol was impacting
> > > > > > so far the only user of it (Synquacer controller). In paralel
> > > > > > edk2-platforms patchset, a patch can be found:
> > > > > > ("Silicon/SynQuacer/PlatformDxe: adjust to updated
> SdMmcOverride")
> > > > > > which immunizes for above and future extensions of the protocol:
> > > > > > https://github.com/MarvellEmbeddedProcessors/edk2-open-
> > > > > > platform/commits/xenon-upstream-r20181005
> > > > > >
> > > > > > I'm looking forward to the comments and remarks.
> > > > > >
> > > > > > Best regards,
> > > > > > Marcin
> > > > > >
> > > > > > Changelog:
> > > > > > v1 -> v2
> > > > > > * Rebase onto newest master
> > > > > > * 1/4 [new patch] - preparation for extending NotifyPhase
> > > > > > * 2/4 - UhsSignaling as a part of NotifyPhase
> > > > > > * 3/4 - SwitchClockFreqPost as a part of NotifyPhase
> > > > > > * 4/4 - Allow updating BaseClkFreq via Capability instead of the
> > > > > > independent callback.
> > > > > >
> > > > > > Marcin Wojtas (2):
> > > > > > MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in
> > > > > > NotifyPhase
> > > > > > MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock
> frequency
> > > > > >
> > > > > > Tomasz Michalec (2):
> > > > > > MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to
> SdMmcOverride
> > > > > > protocol
> > > > > > MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to
> > > > > > SdMmcOverride
> > > > > >
> > > > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 6 +
> > > > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 62
> +++++-
> > > > > > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 12 +-
> > > > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 215
> > > > > > ++++++++++++++------
> > > > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 57
> +++++-
> > > > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 18
> +-
> > > > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 108
> > > > ++++++++-
> > > > > > -
> > > > > > 7 files changed, 383 insertions(+), 95 deletions(-)
> > > > > >
> > > > > > --
> > > > > > 2.7.4
> > > > >
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-10-05 13:25 ` [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol Marcin Wojtas
2018-10-05 15:12 ` Philippe Mathieu-Daudé
2018-10-08 12:41 ` Ard Biesheuvel
@ 2018-11-01 7:04 ` Wu, Hao A
2018-11-02 8:21 ` Marcin Wojtas
2 siblings, 1 reply; 47+ messages in thread
From: Wu, Hao A @ 2018-11-01 7:04 UTC (permalink / raw)
To: 'Marcin Wojtas', edk2-devel@lists.01.org
Cc: Kinney, Michael D, Gao, Liming, leif.lindholm@linaro.org,
ard.biesheuvel@linaro.org, nadavh@marvell.com, jsd@semihalf.com,
tm@semihalf.com
Hi Marcin,
> -----Original Message-----
> From: Marcin Wojtas [mailto:mw@semihalf.com]
> Sent: Friday, October 05, 2018 9:25 PM
> To: edk2-devel@lists.01.org
> Cc: Tian, Feng; Kinney, Michael D; Gao, Liming; leif.lindholm@linaro.org; Wu,
> Hao A; ard.biesheuvel@linaro.org; nadavh@marvell.com;
> mw@semihalf.com; jsd@semihalf.com; tm@semihalf.com
> Subject: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling
> to SdMmcOverride protocol
>
> From: Tomasz Michalec <tm@semihalf.com>
>
> Some SD Host Controlers use different values in Host Control 2 Register
> to select UHS Mode. This patch adds a new UhsSignaling type routine to
> the NotifyPhase of the SdMmcOverride protocol.
>
> UHS signaling configuration is moved to a common, default routine
> (SdMmcHcUhsSignaling), which is called when SdMmcOverride does not
> cover this functionality.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 50 +++++++
> MdeModulePkg/Include/Protocol/SdMmcOverride.h | 2 +
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 153
> ++++++++++++--------
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 37 +++--
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 69 +++++++++
> 5 files changed, 243 insertions(+), 68 deletions(-)
>
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> index e389d52..a03160d 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> @@ -63,6 +63,39 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF
> ANY KIND, EITHER EXPRESS OR IMPLIED.
> #define SD_MMC_HC_CTRL_VER 0xFE
>
> //
> +// SD Host Controler bits to HOST_CTRL2 register
> +//
> +#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
> +#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
> +#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
> +#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
> +#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
> +#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
> +#define SD_MMC_HC_CTRL_MMC_DDR52 0x0004
> +#define SD_MMC_HC_CTRL_MMC_SDR50 0x0002
I think SD_MMC_HC_CTRL_MMC_SDR50 is not needed here.
Since according to the SD Physical Layer Simplified Specification, max clock
frequency for SD bus mode SDR50 is 100MHz. And there is no eMMC bus mode whose
max clock frequency is at 100MHz in Embedded Multi-Media Card Electrical
Standard (5.1).
> +#define SD_MMC_HC_CTRL_MMC_SDR25 0x0001
> +#define SD_MMC_HC_CTRL_MMC_SDR12 0x0000
> +#define SD_MMC_HC_CTRL_HS200 0x0003
> +#define SD_MMC_HC_CTRL_HS400 0x0005
How about the below renames & reorder?
SD_MMC_HC_CTRL_MMC_LEGACY 0x0000
SD_MMC_HC_CTRL_MMC_HS_SDR 0x0001
SD_MMC_HC_CTRL_MMC_HS_DDR 0x0004
SD_MMC_HC_CTRL_MMC_HS200 0x0003
SD_MMC_HC_CTRL_MMC_HS400 0x0005
> +
> +//
> +// Timing modes for uhs
> +//
> +typedef enum {
> + SdMmcUhsSdr12,
> + SdMmcUhsSdr25,
> + SdMmcUhsSdr50,
> + SdMmcUhsSdr104,
> + SdMmcUhsDdr50,
> + SdMmcMmcDdr52,
> + SdMmcMmcSdr50,
> + SdMmcMmcSdr25,
> + SdMmcMmcSdr12,
> + SdMmcMmcHs200,
> + SdMmcMmcHs400,
> +} SD_MMC_UHS_TIMING;
Suggest a similar drop of 'SdMmcMmcSdr50' and rename according to the above
comments upon HOST_CTRL2 register value definitions. Also, how about a rename
for enum to SD_MMC_BUS_MODE?
> +
> +//
> // The transfer modes supported by SD Host Controller
> // Simplified Spec 3.0 Table 1-2
> //
> @@ -508,4 +541,21 @@ SdMmcHcInitTimeoutCtrl (
> IN UINT8 Slot
> );
>
> +/**
> + Set SD Host Controler control 2 registry according to selected speed.
> +
> + @param[in] PciIo The PCI IO protocol instance.
> + @param[in] Slot The slot number of the SD card to send the
> command to.
> + @param[in] Timing The timing to select.
> +
> + @retval EFI_SUCCESS The timing is set successfully.
> + @retval Others The timing isn't set successfully.
> +**/
> +EFI_STATUS
> +SdMmcHcUhsSignaling (
> + IN EFI_PCI_IO_PROTOCOL *PciIo,
> + IN UINT8 Slot,
> + IN SD_MMC_UHS_TIMING Timing
> + );
> +
> #endif
> diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> index 178945f..25db98a 100644
> --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> @@ -17,6 +17,7 @@
> #ifndef __SD_MMC_OVERRIDE_H__
> #define __SD_MMC_OVERRIDE_H__
>
> +#include <Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h>
Please do not expose a module private header file here.
One approach comes to me is to keep the SD/MMC bus mode enumeration structure
in this protocol header file. SdMmcPciHcDxe driver and producers of the
Override protocol keep a version of the HOST_CTRL2 register value macros of
their own.
> #include <Protocol/SdMmcPassThru.h>
>
> #define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \
> @@ -31,6 +32,7 @@ typedef enum {
> EdkiiSdMmcResetPost,
> EdkiiSdMmcInitHostPre,
> EdkiiSdMmcInitHostPost,
> + EdkiiSdMmcUhsSignaling,
> } EDKII_SD_MMC_PHASE_TYPE;
>
> /**
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> index c5fd214..05bd4a0 100755
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> @@ -740,10 +740,13 @@ EmmcSwitchToHighSpeed (
> IN UINT8 BusWidth
> )
> {
> - EFI_STATUS Status;
> - UINT8 HsTiming;
> - UINT8 HostCtrl1;
> - UINT8 HostCtrl2;
> + EFI_STATUS Status;
> + UINT8 HsTiming;
> + UINT8 HostCtrl1;
> + SD_MMC_UHS_TIMING Timing;
> + SD_MMC_HC_PRIVATE_DATA *Private;
> +
> + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
>
> Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusWidth);
> if (EFI_ERROR (Status)) {
> @@ -758,27 +761,37 @@ EmmcSwitchToHighSpeed (
> return Status;
> }
>
> - //
> - // Clean UHS Mode Select field of Host Control 2 reigster before update
> - //
> - HostCtrl2 = (UINT8)~0x7;
> - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2,
> sizeof (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> - }
> - //
> - // Set UHS Mode Select field of Host Control 2 reigster to SDR12/25/50
> - //
> if (IsDdr) {
> - HostCtrl2 = BIT2;
> + Timing = SdMmcMmcDdr52;
> } else if (ClockFreq == 52) {
> - HostCtrl2 = BIT0;
> + Timing = SdMmcMmcSdr50;
> + } else if (ClockFreq == 26) {
> + Timing = SdMmcMmcSdr25;
> } else {
> - HostCtrl2 = 0;
> + Timing = SdMmcMmcSdr12;
> }
As mentioned above, "SdMmcMmcSdr50" can be dropped here.
And considering the rename above, how about:
if (IsDdr) {
Timing = SdMmcMmcHsDdr;
} else if (ClockFreq == 52) {
Timing = SdMmcMmcHsSdr;
} else {
Timing = SdMmcMmcLegacy;
}
> - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof
> (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> +
> + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> + Status = mOverride->NotifyPhase (
> + Private->ControllerHandle,
> + Slot,
> + EdkiiSdMmcUhsSignaling,
> + &Timing
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> + __FUNCTION__,
> + Status
> + ));
> + return Status;
> + }
> + } else {
> + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> }
I have concern for this, current existing hook points for the NotifyPhase()
service are performing additional operations during the controller
initialization process.
Producer of the override protocol can simply return EFI_SUCCESS, if there is
nothing to do for a specific hook point.
But this hook here is to override the behavior when setting the "UHS Mode
Select" field of Host Control 2 Register. If the override protocol producer
does not want to override the behavior at the 'EdkiiSdMmcUhsSignaling' hook,
but has to do something in other hooks, one cannot directly return EFI_SUCCESS
for the 'EdkiiSdMmcUhsSignaling' hook. For this case, one has to implement the
'EdkiiSdMmcUhsSignaling' hook even if the behavior will be exactly the same as
the SdMmcPciHcDxe driver.
Best Regards,
Hao Wu
>
> HsTiming = 1;
> @@ -814,10 +827,13 @@ EmmcSwitchToHS200 (
> IN UINT8 BusWidth
> )
> {
> - EFI_STATUS Status;
> - UINT8 HsTiming;
> - UINT8 HostCtrl2;
> - UINT16 ClockCtrl;
> + EFI_STATUS Status;
> + UINT8 HsTiming;
> + UINT16 ClockCtrl;
> + SD_MMC_UHS_TIMING Timing;
> + SD_MMC_HC_PRIVATE_DATA *Private;
> +
> + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
>
> if ((BusWidth != 4) && (BusWidth != 8)) {
> return EFI_INVALID_PARAMETER;
> @@ -837,21 +853,30 @@ EmmcSwitchToHS200 (
> if (EFI_ERROR (Status)) {
> return Status;
> }
> - //
> - // Clean UHS Mode Select field of Host Control 2 reigster before update
> - //
> - HostCtrl2 = (UINT8)~0x7;
> - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2,
> sizeof (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> - }
> - //
> - // Set UHS Mode Select field of Host Control 2 reigster to SDR104
> - //
> - HostCtrl2 = BIT0 | BIT1;
> - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof
> (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> +
> + Timing = SdMmcMmcHs200;
> +
> + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> + Status = mOverride->NotifyPhase (
> + Private->ControllerHandle,
> + Slot,
> + EdkiiSdMmcUhsSignaling,
> + &Timing
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> + __FUNCTION__,
> + Status
> + ));
> + return Status;
> + }
> + } else {
> + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> }
> //
> // Wait Internal Clock Stable in the Clock Control register to be 1 before set
> SD Clock Enable bit
> @@ -910,9 +935,12 @@ EmmcSwitchToHS400 (
> IN UINT32 ClockFreq
> )
> {
> - EFI_STATUS Status;
> - UINT8 HsTiming;
> - UINT8 HostCtrl2;
> + EFI_STATUS Status;
> + UINT8 HsTiming;
> + SD_MMC_UHS_TIMING Timing;
> + SD_MMC_HC_PRIVATE_DATA *Private;
> +
> + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
>
> Status = EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, ClockFreq, 8);
> if (EFI_ERROR (Status)) {
> @@ -933,21 +961,30 @@ EmmcSwitchToHS400 (
> if (EFI_ERROR (Status)) {
> return Status;
> }
> - //
> - // Clean UHS Mode Select field of Host Control 2 reigster before update
> - //
> - HostCtrl2 = (UINT8)~0x7;
> - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2,
> sizeof (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> - }
> - //
> - // Set UHS Mode Select field of Host Control 2 reigster to HS400
> - //
> - HostCtrl2 = BIT0 | BIT2;
> - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof
> (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> +
> + Timing = SdMmcMmcHs400;
> +
> + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> + Status = mOverride->NotifyPhase (
> + Private->ControllerHandle,
> + Slot,
> + EdkiiSdMmcUhsSignaling,
> + &Timing
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> + __FUNCTION__,
> + Status
> + ));
> + return Status;
> + }
> + } else {
> + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> }
>
> HsTiming = 3;
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> index 8c93933..5645a71 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> @@ -784,8 +784,8 @@ SdCardSetBusMode (
> UINT8 BusWidth;
> UINT8 AccessMode;
> UINT8 HostCtrl1;
> - UINT8 HostCtrl2;
> UINT8 SwitchResp[64];
> + SD_MMC_UHS_TIMING Timing;
> SD_MMC_HC_PRIVATE_DATA *Private;
>
> Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> @@ -817,18 +817,23 @@ SdCardSetBusMode (
> if (S18A && (Capability->Sdr104 != 0) && ((SwitchResp[13] & BIT3) != 0)) {
> ClockFreq = 208;
> AccessMode = 3;
> + Timing = SdMmcUhsSdr104;
> } else if (S18A && (Capability->Sdr50 != 0) && ((SwitchResp[13] & BIT2) != 0))
> {
> ClockFreq = 100;
> AccessMode = 2;
> + Timing = SdMmcUhsSdr50;
> } else if (S18A && (Capability->Ddr50 != 0) && ((SwitchResp[13] & BIT4) !=
> 0)) {
> ClockFreq = 50;
> AccessMode = 4;
> + Timing = SdMmcUhsDdr50;
> } else if ((SwitchResp[13] & BIT1) != 0) {
> ClockFreq = 50;
> AccessMode = 1;
> + Timing = SdMmcUhsSdr25;
> } else {
> ClockFreq = 25;
> AccessMode = 0;
> + Timing = SdMmcUhsSdr12;
> }
>
> Status = SdCardSwitch (PassThru, Slot, AccessMode, 0xF, 0xF, 0xF, TRUE,
> SwitchResp);
> @@ -854,15 +859,27 @@ SdCardSetBusMode (
> }
> }
>
> - HostCtrl2 = (UINT8)~0x7;
> - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2,
> sizeof (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> - }
> - HostCtrl2 = AccessMode;
> - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof
> (HostCtrl2), &HostCtrl2);
> - if (EFI_ERROR (Status)) {
> - return Status;
> + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> + Status = mOverride->NotifyPhase (
> + Private->ControllerHandle,
> + Slot,
> + EdkiiSdMmcUhsSignaling,
> + &Timing
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> + __FUNCTION__,
> + Status
> + ));
> + return Status;
> + }
> + } else {
> + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> }
>
> Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capability);
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> index 02eb4ad..38d6202 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> @@ -1137,6 +1137,75 @@ SdMmcHcInitHost (
> }
>
> /**
> + Set SD Host Controler control 2 registry according to selected speed.
> +
> + @param[in] PciIo The PCI IO protocol instance.
> + @param[in] Slot The slot number of the SD card to send the
> command to.
> + @param[in] Timing The timing to select.
> +
> + @retval EFI_SUCCESS The timing is set successfully.
> + @retval Others The timing isn't set successfully.
> +**/
> +EFI_STATUS
> +SdMmcHcUhsSignaling (
> + IN EFI_PCI_IO_PROTOCOL *PciIo,
> + IN UINT8 Slot,
> + IN SD_MMC_UHS_TIMING Timing
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 HostCtrl2;
> +
> + HostCtrl2 = (UINT8)~SD_MMC_HC_CTRL_UHS_MASK;
> + Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2,
> sizeof (HostCtrl2), &HostCtrl2);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + switch (Timing) {
> + case SdMmcUhsSdr12:
> + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR12;
> + break;
> + case SdMmcUhsSdr25:
> + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR25;
> + break;
> + case SdMmcUhsSdr50:
> + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR50;
> + break;
> + case SdMmcUhsSdr104:
> + HostCtrl2 = SD_MMC_HC_CTRL_UHS_SDR104;
> + break;
> + case SdMmcUhsDdr50:
> + HostCtrl2 = SD_MMC_HC_CTRL_UHS_DDR50;
> + break;
> + case SdMmcMmcDdr52:
> + HostCtrl2 = SD_MMC_HC_CTRL_MMC_DDR52;
> + break;
> + case SdMmcMmcSdr50:
> + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR50;
> + break;
> + case SdMmcMmcSdr25:
> + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR25;
> + break;
> + case SdMmcMmcSdr12:
> + HostCtrl2 = SD_MMC_HC_CTRL_MMC_SDR12;
> + break;
> + case SdMmcMmcHs200:
> + HostCtrl2 = SD_MMC_HC_CTRL_HS200;
> + break;
> + case SdMmcMmcHs400:
> + HostCtrl2 = SD_MMC_HC_CTRL_HS400;
> + break;
> + default:
> + HostCtrl2 = 0;
> + break;
> + }
> + Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof
> (HostCtrl2), &HostCtrl2);
> +
> + return Status;
> +}
> +
> +/**
> Turn on/off LED.
>
> @param[in] PciIo The PCI IO protocol instance.
> --
> 2.7.4
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 3/4] MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to SdMmcOverride
2018-10-05 13:25 ` [PATCH v2 3/4] MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to SdMmcOverride Marcin Wojtas
2018-10-08 12:44 ` Ard Biesheuvel
@ 2018-11-01 7:06 ` Wu, Hao A
2018-11-02 9:39 ` Marcin Wojtas
1 sibling, 1 reply; 47+ messages in thread
From: Wu, Hao A @ 2018-11-01 7:06 UTC (permalink / raw)
To: 'Marcin Wojtas', edk2-devel@lists.01.org
Cc: tm@semihalf.com, nadavh@marvell.com, Gao, Liming,
Kinney, Michael D
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> Marcin Wojtas
> Sent: Friday, October 05, 2018 9:25 PM
> To: edk2-devel@lists.01.org
> Cc: Tian, Feng; tm@semihalf.com; Wu, Hao A; nadavh@marvell.com; Gao,
> Liming; Kinney, Michael D
> Subject: [edk2] [PATCH v2 3/4] MdeModulePkg/SdMmcPciHcDxe: Add
> SwitchClockFreqPost to SdMmcOverride
>
> From: Tomasz Michalec <tm@semihalf.com>
>
> Some SD Host Controlers need to do additional opperations after clock
> frequency switch.
>
> This patch add new callback type to NotifyPhase of the SdMmcOverride
> protocol. It is called after EmmcSwitchClockFreq and SdMmcHcClockSupply.
Hi Marcin,
Just curious, I had a quick glance at the implementation of the
XenonSwitchClockFreqPost() in your platform part changes. Are those operations
within the function mandatory during the HC initialization? Are they mainly for
performance or stability consideration?
I am wondering if this kind of customization is common among the SD & eMMC
devices.
Best Regards,
Hao Wu
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
> MdeModulePkg/Include/Protocol/SdMmcOverride.h | 1 +
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 60
> ++++++++++++++++++++
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 18 ++++++
> 3 files changed, 79 insertions(+)
>
> diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> index 25db98a..d9daada 100644
> --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> @@ -33,6 +33,7 @@ typedef enum {
> EdkiiSdMmcInitHostPre,
> EdkiiSdMmcInitHostPost,
> EdkiiSdMmcUhsSignaling,
> + EdkiiSdMmcSwitchClockFreqPost,
> } EDKII_SD_MMC_PHASE_TYPE;
>
> /**
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> index 05bd4a0..7e75283 100755
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> @@ -796,6 +796,27 @@ EmmcSwitchToHighSpeed (
>
> HsTiming = 1;
> Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming,
> ClockFreq);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> + Status = mOverride->NotifyPhase (
> + Private->ControllerHandle,
> + Slot,
> + EdkiiSdMmcSwitchClockFreqPost,
> + &Timing
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
> + __FUNCTION__,
> + Status
> + ));
> + return Status;
> + }
> + }
>
> return Status;
> }
> @@ -905,6 +926,24 @@ EmmcSwitchToHS200 (
> return Status;
> }
>
> + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> + Status = mOverride->NotifyPhase (
> + Private->ControllerHandle,
> + Slot,
> + EdkiiSdMmcSwitchClockFreqPost,
> + &Timing
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
> + __FUNCTION__,
> + Status
> + ));
> + return Status;
> + }
> + }
> +
> Status = EmmcTuningClkForHs200 (PciIo, PassThru, Slot, BusWidth);
>
> return Status;
> @@ -989,6 +1028,27 @@ EmmcSwitchToHS400 (
>
> HsTiming = 3;
> Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming,
> ClockFreq);
> + if (EFI_ERROR (Status)) {
> + return Status;
> + }
> +
> + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> + Status = mOverride->NotifyPhase (
> + Private->ControllerHandle,
> + Slot,
> + EdkiiSdMmcSwitchClockFreqPost,
> + &Timing
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
> + __FUNCTION__,
> + Status
> + ));
> + return Status;
> + }
> + }
>
> return Status;
> }
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> index 5645a71..057a4e2 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> @@ -887,6 +887,24 @@ SdCardSetBusMode (
> return Status;
> }
>
> + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> + Status = mOverride->NotifyPhase (
> + Private->ControllerHandle,
> + Slot,
> + EdkiiSdMmcSwitchClockFreqPost,
> + &Timing
> + );
> + if (EFI_ERROR (Status)) {
> + DEBUG ((
> + DEBUG_ERROR,
> + "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
> + __FUNCTION__,
> + Status
> + ));
> + return Status;
> + }
> + }
> +
> if ((AccessMode == 3) || ((AccessMode == 2) && (Capability-
> >TuningSDR50 != 0))) {
> Status = SdCardTuningClock (PciIo, PassThru, Slot);
> if (EFI_ERROR (Status)) {
> --
> 2.7.4
>
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 4/4] MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequency
2018-10-05 13:25 ` [PATCH v2 4/4] MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequency Marcin Wojtas
2018-10-08 12:49 ` Ard Biesheuvel
@ 2018-11-01 7:11 ` Wu, Hao A
2018-11-02 9:52 ` Marcin Wojtas
1 sibling, 1 reply; 47+ messages in thread
From: Wu, Hao A @ 2018-11-01 7:11 UTC (permalink / raw)
To: 'Marcin Wojtas', edk2-devel@lists.01.org
Cc: Kinney, Michael D, Gao, Liming, leif.lindholm@linaro.org,
ard.biesheuvel@linaro.org, nadavh@marvell.com, jsd@semihalf.com,
tm@semihalf.com
Hi Marcin,
> -----Original Message-----
> From: Marcin Wojtas [mailto:mw@semihalf.com]
> Sent: Friday, October 05, 2018 9:25 PM
> To: edk2-devel@lists.01.org
> Cc: Tian, Feng; Kinney, Michael D; Gao, Liming; leif.lindholm@linaro.org; Wu,
> Hao A; ard.biesheuvel@linaro.org; nadavh@marvell.com;
> mw@semihalf.com; jsd@semihalf.com; tm@semihalf.com
> Subject: [PATCH v2 4/4] MdeModulePkg/SdMmcPciHcDxe: Allow overriding
> base clock frequency
>
> Some SdMmc host controllers are run by clocks with different
> frequency than it is reflected in Capabilities Register 1.
> It is allowed by SDHCI specification ver. 4.2 - if BaseClkFreq
> field value of the Capability Register 1 is zero, the clock
> frequency must be obtained via another method.
>
> Because the bitfield is only 8 bits wide, a maximum value
> that could be obtained from hardware is 255MHz.
> In case the actual frequency exceeds 255MHz, the 8-bit BaseClkFreq
> member of SD_MMC_HC_SLOT_CAP structure occurs to be not sufficient
> to be used for setting the clock speed in SdMmcHcClockSupply
> function.
>
> This patch adds new UINT32 array ('BaseClkFreq[]') to
> SD_MMC_HC_PRIVATE_DATA structure for specifying
> the input clock speed for each slot of the host controller.
> All routines that are used for clock configuration are
> updated accordingly.
>
> This patch also adds new IN OUT BaseClockFreq field
> in the Capability callback of the SdMmcOverride,
> protocol which allows to update BaseClkFreq value.
>
> The patch reuses original commit from edk2-platforms:
> 20f6f144d3a8 ("Marvell/Drivers: XenonDxe: Allow overriding base clock
> frequency")
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 6 +++++
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 12 +++++----
> MdeModulePkg/Include/Protocol/SdMmcOverride.h | 5 +++-
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 4 +--
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 4 +--
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 18
> +++++++++++--
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 27
> +++++++++++---------
> 7 files changed, 52 insertions(+), 24 deletions(-)
>
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> index c683600..8c1a589 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> @@ -118,6 +118,12 @@ typedef struct {
> UINT64 MaxCurrent[SD_MMC_HC_MAX_SLOT];
>
> UINT32 ControllerVersion;
> +
> + //
> + // Some controllers may require to override base clock frequency
> + // value stored in Capabilities Register 1.
> + //
> + UINT32 BaseClkFreq[SD_MMC_HC_MAX_SLOT];
> } SD_MMC_HC_PRIVATE_DATA;
>
> #define SD_MMC_HC_TRB_SIG SIGNATURE_32 ('T', 'R', 'B', 'T')
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> index a03160d..f01ba21 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> @@ -173,12 +173,14 @@ typedef struct {
>
> @param[in] Slot The slot number of the SD card to send the
> command to.
> @param[in] Capability The buffer to store the capability data.
> + @param[in] BaseClkFreq The base clock frequency of host controller in
> MHz.
>
> **/
> VOID
> DumpCapabilityReg (
> IN UINT8 Slot,
> - IN SD_MMC_HC_SLOT_CAP *Capability
> + IN SD_MMC_HC_SLOT_CAP *Capability,
> + IN UINT32 BaseClkFreq
> );
>
> /**
> @@ -431,7 +433,7 @@ SdMmcHcStopClock (
> @param[in] PciIo The PCI IO protocol instance.
> @param[in] Slot The slot number of the SD card to send the
> command to.
> @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
> - @param[in] Capability The capability of the slot.
> + @param[in] BaseClkFreq The base clock frequency of host controller in
> MHz.
>
> @retval EFI_SUCCESS The clock is supplied successfully.
> @retval Others The clock isn't supplied successfully.
> @@ -442,7 +444,7 @@ SdMmcHcClockSupply (
> IN EFI_PCI_IO_PROTOCOL *PciIo,
> IN UINT8 Slot,
> IN UINT64 ClockFreq,
> - IN SD_MMC_HC_SLOT_CAP Capability
> + IN UINT32 BaseClkFreq
> );
>
> /**
> @@ -490,7 +492,7 @@ SdMmcHcSetBusWidth (
>
> @param[in] PciIo The PCI IO protocol instance.
> @param[in] Slot The slot number of the SD card to send the
> command to.
> - @param[in] Capability The capability of the slot.
> + @param[in] BaseClkFreq The base clock frequency of host controller in
> MHz.
>
> @retval EFI_SUCCESS The clock is supplied successfully.
> @retval Others The clock isn't supplied successfully.
> @@ -500,7 +502,7 @@ EFI_STATUS
> SdMmcHcInitClockFreq (
> IN EFI_PCI_IO_PROTOCOL *PciIo,
> IN UINT8 Slot,
> - IN SD_MMC_HC_SLOT_CAP Capability
> + IN UINT32 BaseClkFreq
> );
>
> /**
> diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> index d9daada..27023d3 100644
> --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> @@ -43,6 +43,8 @@ typedef enum {
> @param[in] ControllerHandle The EFI_HANDLE of the controller.
> @param[in] Slot The 0 based slot index.
> @param[in,out] SdMmcHcSlotCapability The SDHCI capability structure.
> + @param[in,out] BaseClkFreq The base clock frequency value that
> + optionally can be updated.
>
> @retval EFI_SUCCESS The override function completed successfully.
> @retval EFI_NOT_FOUND The specified controller or slot does not
> exist.
> @@ -54,7 +56,8 @@ EFI_STATUS
> (EFIAPI * EDKII_SD_MMC_CAPABILITY) (
> IN EFI_HANDLE ControllerHandle,
> IN UINT8 Slot,
> - IN OUT VOID *SdMmcHcSlotCapability
> + IN OUT VOID *SdMmcHcSlotCapability,
> + IN OUT UINT32 *BaseClkFreq
> );
>
> /**
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> index 7e75283..27ccd63 100755
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> @@ -705,7 +705,7 @@ EmmcSwitchClockFreq (
> //
> // Convert the clock freq unit from MHz to KHz.
> //
> - Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private-
> >Capability[Slot]);
> + Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private-
> >BaseClkFreq[Slot]);
>
> return Status;
> }
> @@ -1099,7 +1099,7 @@ EmmcSetBusMode (
> return Status;
> }
>
> - ASSERT (Private->Capability[Slot].BaseClkFreq != 0);
> + ASSERT (Private->BaseClkFreq[Slot] != 0);
> //
> // Check if the Host Controller support 8bits bus width.
> //
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> index 057a4e2..9ea13be 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> @@ -882,7 +882,7 @@ SdCardSetBusMode (
> }
> }
>
> - Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capability);
> + Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private-
> >BaseClkFreq[Slot]);
> if (EFI_ERROR (Status)) {
> return Status;
> }
> @@ -1081,7 +1081,7 @@ SdCardIdentification (
> goto Error;
> }
>
> - SdMmcHcInitClockFreq (PciIo, Slot, Private->Capability[Slot]);
> + SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot]);
>
> gBS->Stall (1000);
>
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
> b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
> index bf9869d..d7cc0ce 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
> @@ -625,18 +625,32 @@ SdMmcPciHcDriverBindingStart (
> if (EFI_ERROR (Status)) {
> continue;
> }
> +
> + Private->BaseClkFreq[Slot] = Private->Capability[Slot].BaseClkFreq;
> +
> if (mOverride != NULL && mOverride->Capability != NULL) {
> Status = mOverride->Capability (
> Controller,
> Slot,
> - &Private->Capability[Slot]);
> + &Private->Capability[Slot],
> + &Private->BaseClkFreq[Slot]
> + );
> if (EFI_ERROR (Status)) {
> DEBUG ((DEBUG_WARN, "%a: Failed to override capability - %r\n",
> __FUNCTION__, Status));
> continue;
> }
> }
> - DumpCapabilityReg (Slot, &Private->Capability[Slot]);
> +
> + //
> + // According to SDHCI specification ver. 4.2, BaseClkFreq field value of
> + // the Capability Register 1 can be zero, which means a need for
> obtaining
> + // the clock frequency via another method. Fail in case it is not updated
> + // by SW at this point.
> + //
> + ASSERT (Private->BaseClkFreq[Slot] != 0);
I think the ASSERT here can be dropped. This value will be handled within
function SdMmcHcInitClockFreq(). And the above newly added comments can be used
in SdMmcHcInitClockFreq() instead.
> +
> + DumpCapabilityReg (Slot, &Private->Capability[Slot], Private-
> >BaseClkFreq[Slot]);
My thought on this one is that you can leave DumpCapabilityReg() unchanged and
append a DEBUG() call with DEBUG_INFO level to output the value of
Private->BaseClkFreq for a slot.
Best Regards,
Hao Wu
>
> Support64BitDma &= Private->Capability[Slot].SysBus64;
>
> diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> index 38d6202..9f50754 100644
> --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> @@ -22,12 +22,14 @@
>
> @param[in] Slot The slot number of the SD card to send the
> command to.
> @param[in] Capability The buffer to store the capability data.
> + @param[in] BaseClkFreq The base clock frequency of host controller in
> MHz.
>
> **/
> VOID
> DumpCapabilityReg (
> IN UINT8 Slot,
> - IN SD_MMC_HC_SLOT_CAP *Capability
> + IN SD_MMC_HC_SLOT_CAP *Capability,
> + IN UINT32 BaseClkFreq
> )
> {
> //
> @@ -35,7 +37,10 @@ DumpCapabilityReg (
> //
> DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot,
> Capability));
> DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability-
> >TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));
> - DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability-
> >BaseClkFreq));
> + if (Capability->BaseClkFreq != BaseClkFreq) {
> + DEBUG ((DEBUG_INFO, " Controller register value overriden:\n"));
> + }
> + DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", BaseClkFreq));
> DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 <<
> Capability->MaxBlkLen)));
> DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ?
> "TRUE" : "FALSE"));
> DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ?
> "TRUE" : "FALSE"));
> @@ -721,7 +726,7 @@ SdMmcHcStopClock (
> @param[in] PciIo The PCI IO protocol instance.
> @param[in] Slot The slot number of the SD card to send the
> command to.
> @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
> - @param[in] Capability The capability of the slot.
> + @param[in] BaseClkFreq The base clock frequency of host controller in
> MHz.
>
> @retval EFI_SUCCESS The clock is supplied successfully.
> @retval Others The clock isn't supplied successfully.
> @@ -732,11 +737,10 @@ SdMmcHcClockSupply (
> IN EFI_PCI_IO_PROTOCOL *PciIo,
> IN UINT8 Slot,
> IN UINT64 ClockFreq,
> - IN SD_MMC_HC_SLOT_CAP Capability
> + IN UINT32 BaseClkFreq
> )
> {
> EFI_STATUS Status;
> - UINT32 BaseClkFreq;
> UINT32 SettingFreq;
> UINT32 Divisor;
> UINT32 Remainder;
> @@ -746,9 +750,8 @@ SdMmcHcClockSupply (
> //
> // Calculate a divisor for SD clock frequency
> //
> - ASSERT (Capability.BaseClkFreq != 0);
> + ASSERT (BaseClkFreq != 0);
>
> - BaseClkFreq = Capability.BaseClkFreq;
> if (ClockFreq == 0) {
> return EFI_INVALID_PARAMETER;
> }
> @@ -939,7 +942,7 @@ SdMmcHcSetBusWidth (
>
> @param[in] PciIo The PCI IO protocol instance.
> @param[in] Slot The slot number of the SD card to send the
> command to.
> - @param[in] Capability The capability of the slot.
> + @param[in] BaseClkFreq The base clock frequency of host controller in
> MHz.
>
> @retval EFI_SUCCESS The clock is supplied successfully.
> @retval Others The clock isn't supplied successfully.
> @@ -949,7 +952,7 @@ EFI_STATUS
> SdMmcHcInitClockFreq (
> IN EFI_PCI_IO_PROTOCOL *PciIo,
> IN UINT8 Slot,
> - IN SD_MMC_HC_SLOT_CAP Capability
> + IN UINT32 BaseClkFreq
> )
> {
> EFI_STATUS Status;
> @@ -958,7 +961,7 @@ SdMmcHcInitClockFreq (
> //
> // Calculate a divisor for SD clock frequency
> //
> - if (Capability.BaseClkFreq == 0) {
> + if (BaseClkFreq == 0) {
> //
> // Don't support get Base Clock Frequency information via another
> method
> //
> @@ -968,7 +971,7 @@ SdMmcHcInitClockFreq (
> // Supply 400KHz clock frequency at initialization phase.
> //
> InitFreq = 400;
> - Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, Capability);
> + Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, BaseClkFreq);
> return Status;
> }
>
> @@ -1102,7 +1105,7 @@ SdMmcHcInitHost (
> PciIo = Private->PciIo;
> Capability = Private->Capability[Slot];
>
> - Status = SdMmcHcInitClockFreq (PciIo, Slot, Capability);
> + Status = SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot]);
> if (EFI_ERROR (Status)) {
> return Status;
> }
> --
> 2.7.4
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 0/4] SdMmcOverride extension
2018-10-05 13:25 [PATCH v2 0/4] SdMmcOverride extension Marcin Wojtas
` (4 preceding siblings ...)
2018-10-12 5:24 ` [PATCH v2 0/4] SdMmcOverride extension Wu, Hao A
@ 2018-11-01 7:11 ` Wu, Hao A
2018-11-02 10:09 ` Marcin Wojtas
5 siblings, 1 reply; 47+ messages in thread
From: Wu, Hao A @ 2018-11-01 7:11 UTC (permalink / raw)
To: 'Marcin Wojtas', Ard Biesheuvel, edk2-devel@lists.01.org
Cc: Kinney, Michael D, Gao, Liming, leif.lindholm@linaro.org,
ard.biesheuvel@linaro.org, nadavh@marvell.com, jsd@semihalf.com,
tm@semihalf.com
Hi Marcin and Ard,
> -----Original Message-----
> From: Marcin Wojtas [mailto:mw@semihalf.com]
> Sent: Friday, October 05, 2018 9:25 PM
> To: edk2-devel@lists.01.org
> Cc: Tian, Feng; Kinney, Michael D; Gao, Liming; leif.lindholm@linaro.org; Wu,
> Hao A; ard.biesheuvel@linaro.org; nadavh@marvell.com;
> mw@semihalf.com; jsd@semihalf.com; tm@semihalf.com
> Subject: [PATCH v2 0/4] SdMmcOverride extension
>
> Hi,
>
> This is the second version of the patchset. Initial one was
> interleaved with the fixes, which after split got already merged.
> The biggest change is - resigning from the new callbacks
> and extending parameter lists of both NotifyPhase and Capability
> routines.
>
> Patches are available in the github:
> https://github.com/MarvellEmbeddedProcessors/edk2-open-
> platform/commits/sdmmc-override-upstream-r20181005
>
> Please note that extending SdMmcOverride protocol was impacting
> so far the only user of it (Synquacer controller). In paralel
> edk2-platforms patchset, a patch can be found:
> ("Silicon/SynQuacer/PlatformDxe: adjust to updated SdMmcOverride")
> which immunizes for above and future extensions of the protocol:
> https://github.com/MarvellEmbeddedProcessors/edk2-open-
> platform/commits/xenon-upstream-r20181005
>
> I'm looking forward to the comments and remarks.
Since there are protocol service interface changes, maybe a version change
(macro EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION) for the SdMmc Override Protocol
is needed.
Please share your thoughts on this one. Thanks.
Best Regards,
Hao Wu
>
> Best regards,
> Marcin
>
> Changelog:
> v1 -> v2
> * Rebase onto newest master
> * 1/4 [new patch] - preparation for extending NotifyPhase
> * 2/4 - UhsSignaling as a part of NotifyPhase
> * 3/4 - SwitchClockFreqPost as a part of NotifyPhase
> * 4/4 - Allow updating BaseClkFreq via Capability instead of the
> independent callback.
>
> Marcin Wojtas (2):
> MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in
> NotifyPhase
> MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequency
>
> Tomasz Michalec (2):
> MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride
> protocol
> MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to
> SdMmcOverride
>
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 6 +
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 62 +++++-
> MdeModulePkg/Include/Protocol/SdMmcOverride.h | 12 +-
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 215
> ++++++++++++++------
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 57 +++++-
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 18 +-
> MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 108 ++++++++-
> -
> 7 files changed, 383 insertions(+), 95 deletions(-)
>
> --
> 2.7.4
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-11-01 7:04 ` Wu, Hao A
@ 2018-11-02 8:21 ` Marcin Wojtas
2018-11-02 12:16 ` Marcin Wojtas
0 siblings, 1 reply; 47+ messages in thread
From: Marcin Wojtas @ 2018-11-02 8:21 UTC (permalink / raw)
To: hao.a.wu
Cc: edk2-devel-01, Kinney, Michael D, Gao, Liming, Leif Lindholm,
Ard Biesheuvel, nadavh, jsd@semihalf.com, Tomasz Michalec
Hi Hao,
czw., 1 lis 2018 o 08:06 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
>
> Hi Marcin,
>
> > -----Original Message-----
> > From: Marcin Wojtas [mailto:mw@semihalf.com]
> > Sent: Friday, October 05, 2018 9:25 PM
> > To: edk2-devel@lists.01.org
> > Cc: Tian, Feng; Kinney, Michael D; Gao, Liming; leif.lindholm@linaro.org; Wu,
> > Hao A; ard.biesheuvel@linaro.org; nadavh@marvell.com;
> > mw@semihalf.com; jsd@semihalf.com; tm@semihalf.com
> > Subject: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling
> > to SdMmcOverride protocol
> >
> > From: Tomasz Michalec <tm@semihalf.com>
> >
> > Some SD Host Controlers use different values in Host Control 2 Register
> > to select UHS Mode. This patch adds a new UhsSignaling type routine to
> > the NotifyPhase of the SdMmcOverride protocol.
> >
> > UHS signaling configuration is moved to a common, default routine
> > (SdMmcHcUhsSignaling), which is called when SdMmcOverride does not
> > cover this functionality.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> > ---
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 50 +++++++
> > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 2 +
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 153
> > ++++++++++++--------
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 37 +++--
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 69 +++++++++
> > 5 files changed, 243 insertions(+), 68 deletions(-)
> >
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > index e389d52..a03160d 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > @@ -63,6 +63,39 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF
> > ANY KIND, EITHER EXPRESS OR IMPLIED.
> > #define SD_MMC_HC_CTRL_VER 0xFE
> >
> > //
> > +// SD Host Controler bits to HOST_CTRL2 register
> > +//
> > +#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
> > +#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
> > +#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
> > +#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
> > +#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
> > +#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
> > +#define SD_MMC_HC_CTRL_MMC_DDR52 0x0004
> > +#define SD_MMC_HC_CTRL_MMC_SDR50 0x0002
>
> I think SD_MMC_HC_CTRL_MMC_SDR50 is not needed here.
>
> Since according to the SD Physical Layer Simplified Specification, max clock
> frequency for SD bus mode SDR50 is 100MHz. And there is no eMMC bus mode whose
> max clock frequency is at 100MHz in Embedded Multi-Media Card Electrical
> Standard (5.1).
Ok, will drop it.
>
> > +#define SD_MMC_HC_CTRL_MMC_SDR25 0x0001
> > +#define SD_MMC_HC_CTRL_MMC_SDR12 0x0000
> > +#define SD_MMC_HC_CTRL_HS200 0x0003
> > +#define SD_MMC_HC_CTRL_HS400 0x0005
>
> How about the below renames & reorder?
>
> SD_MMC_HC_CTRL_MMC_LEGACY 0x0000
> SD_MMC_HC_CTRL_MMC_HS_SDR 0x0001
> SD_MMC_HC_CTRL_MMC_HS_DDR 0x0004
> SD_MMC_HC_CTRL_MMC_HS200 0x0003
> SD_MMC_HC_CTRL_MMC_HS400 0x0005
Ok.
>
> > +
> > +//
> > +// Timing modes for uhs
> > +//
> > +typedef enum {
> > + SdMmcUhsSdr12,
> > + SdMmcUhsSdr25,
> > + SdMmcUhsSdr50,
> > + SdMmcUhsSdr104,
> > + SdMmcUhsDdr50,
> > + SdMmcMmcDdr52,
> > + SdMmcMmcSdr50,
> > + SdMmcMmcSdr25,
> > + SdMmcMmcSdr12,
> > + SdMmcMmcHs200,
> > + SdMmcMmcHs400,
> > +} SD_MMC_UHS_TIMING;
>
> Suggest a similar drop of 'SdMmcMmcSdr50' and rename according to the above
> comments upon HOST_CTRL2 register value definitions. Also, how about a rename
> for enum to SD_MMC_BUS_MODE?
Ok.
>
> > +
> > +//
> > // The transfer modes supported by SD Host Controller
> > // Simplified Spec 3.0 Table 1-2
> > //
> > @@ -508,4 +541,21 @@ SdMmcHcInitTimeoutCtrl (
> > IN UINT8 Slot
> > );
> >
> > +/**
> > + Set SD Host Controler control 2 registry according to selected speed.
> > +
> > + @param[in] PciIo The PCI IO protocol instance.
> > + @param[in] Slot The slot number of the SD card to send the
> > command to.
> > + @param[in] Timing The timing to select.
> > +
> > + @retval EFI_SUCCESS The timing is set successfully.
> > + @retval Others The timing isn't set successfully.
> > +**/
> > +EFI_STATUS
> > +SdMmcHcUhsSignaling (
> > + IN EFI_PCI_IO_PROTOCOL *PciIo,
> > + IN UINT8 Slot,
> > + IN SD_MMC_UHS_TIMING Timing
> > + );
> > +
> > #endif
> > diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > index 178945f..25db98a 100644
> > --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > @@ -17,6 +17,7 @@
> > #ifndef __SD_MMC_OVERRIDE_H__
> > #define __SD_MMC_OVERRIDE_H__
> >
> > +#include <Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h>
>
> Please do not expose a module private header file here.
>
> One approach comes to me is to keep the SD/MMC bus mode enumeration structure
> in this protocol header file. SdMmcPciHcDxe driver and producers of the
> Override protocol keep a version of the HOST_CTRL2 register value macros of
> their own.
Agree. I will move necessary defines to
Include/Protocol/SdMmcOverride.h instead of exposing SdMmcPciHci.h.
HOST_CTRL2 contents will be a local define in producer code.
>
> > #include <Protocol/SdMmcPassThru.h>
> >
> > #define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \
> > @@ -31,6 +32,7 @@ typedef enum {
> > EdkiiSdMmcResetPost,
> > EdkiiSdMmcInitHostPre,
> > EdkiiSdMmcInitHostPost,
> > + EdkiiSdMmcUhsSignaling,
> > } EDKII_SD_MMC_PHASE_TYPE;
> >
> > /**
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > index c5fd214..05bd4a0 100755
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > @@ -740,10 +740,13 @@ EmmcSwitchToHighSpeed (
> > IN UINT8 BusWidth
> > )
> > {
> > - EFI_STATUS Status;
> > - UINT8 HsTiming;
> > - UINT8 HostCtrl1;
> > - UINT8 HostCtrl2;
> > + EFI_STATUS Status;
> > + UINT8 HsTiming;
> > + UINT8 HostCtrl1;
> > + SD_MMC_UHS_TIMING Timing;
> > + SD_MMC_HC_PRIVATE_DATA *Private;
> > +
> > + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> >
> > Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusWidth);
> > if (EFI_ERROR (Status)) {
> > @@ -758,27 +761,37 @@ EmmcSwitchToHighSpeed (
> > return Status;
> > }
> >
> > - //
> > - // Clean UHS Mode Select field of Host Control 2 reigster before update
> > - //
> > - HostCtrl2 = (UINT8)~0x7;
> > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2,
> > sizeof (HostCtrl2), &HostCtrl2);
> > - if (EFI_ERROR (Status)) {
> > - return Status;
> > - }
> > - //
> > - // Set UHS Mode Select field of Host Control 2 reigster to SDR12/25/50
> > - //
> > if (IsDdr) {
> > - HostCtrl2 = BIT2;
> > + Timing = SdMmcMmcDdr52;
> > } else if (ClockFreq == 52) {
> > - HostCtrl2 = BIT0;
> > + Timing = SdMmcMmcSdr50;
> > + } else if (ClockFreq == 26) {
> > + Timing = SdMmcMmcSdr25;
> > } else {
> > - HostCtrl2 = 0;
> > + Timing = SdMmcMmcSdr12;
> > }
>
> As mentioned above, "SdMmcMmcSdr50" can be dropped here.
> And considering the rename above, how about:
>
> if (IsDdr) {
> Timing = SdMmcMmcHsDdr;
> } else if (ClockFreq == 52) {
> Timing = SdMmcMmcHsSdr;
> } else {
> Timing = SdMmcMmcLegacy;
> }
Ok.
>
> > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof
> > (HostCtrl2), &HostCtrl2);
> > - if (EFI_ERROR (Status)) {
> > - return Status;
> > +
> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> > + Status = mOverride->NotifyPhase (
> > + Private->ControllerHandle,
> > + Slot,
> > + EdkiiSdMmcUhsSignaling,
> > + &Timing
> > + );
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((
> > + DEBUG_ERROR,
> > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> > + __FUNCTION__,
> > + Status
> > + ));
> > + return Status;
> > + }
> > + } else {
> > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > }
>
> I have concern for this, current existing hook points for the NotifyPhase()
> service are performing additional operations during the controller
> initialization process.
>
> Producer of the override protocol can simply return EFI_SUCCESS, if there is
> nothing to do for a specific hook point.
>
> But this hook here is to override the behavior when setting the "UHS Mode
> Select" field of Host Control 2 Register. If the override protocol producer
> does not want to override the behavior at the 'EdkiiSdMmcUhsSignaling' hook,
> but has to do something in other hooks, one cannot directly return EFI_SUCCESS
> for the 'EdkiiSdMmcUhsSignaling' hook. For this case, one has to implement the
> 'EdkiiSdMmcUhsSignaling' hook even if the behavior will be exactly the same as
> the SdMmcPciHcDxe driver.
I see your point. It's not additional code, but replacing the default.
IMO the easiest way to handle it is to go back to a separate
UhsSignaling callback, so that it's either omitted or explicitly
defined by Override protocol producer driver. What do you think?
Best regards,
Marcin
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 3/4] MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to SdMmcOverride
2018-11-01 7:06 ` Wu, Hao A
@ 2018-11-02 9:39 ` Marcin Wojtas
2018-11-03 3:19 ` Wu, Hao A
0 siblings, 1 reply; 47+ messages in thread
From: Marcin Wojtas @ 2018-11-02 9:39 UTC (permalink / raw)
To: hao.a.wu
Cc: edk2-devel-01, Tomasz Michalec, nadavh, Gao, Liming,
Kinney, Michael D
Hi Hao,
czw., 1 lis 2018 o 08:06 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
>
> > -----Original Message-----
> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> > Marcin Wojtas
> > Sent: Friday, October 05, 2018 9:25 PM
> > To: edk2-devel@lists.01.org
> > Cc: Tian, Feng; tm@semihalf.com; Wu, Hao A; nadavh@marvell.com; Gao,
> > Liming; Kinney, Michael D
> > Subject: [edk2] [PATCH v2 3/4] MdeModulePkg/SdMmcPciHcDxe: Add
> > SwitchClockFreqPost to SdMmcOverride
> >
> > From: Tomasz Michalec <tm@semihalf.com>
> >
> > Some SD Host Controlers need to do additional opperations after clock
> > frequency switch.
> >
> > This patch add new callback type to NotifyPhase of the SdMmcOverride
> > protocol. It is called after EmmcSwitchClockFreq and SdMmcHcClockSupply.
>
> Hi Marcin,
>
> Just curious, I had a quick glance at the implementation of the
> XenonSwitchClockFreqPost() in your platform part changes. Are those operations
> within the function mandatory during the HC initialization? Are they mainly for
> performance or stability consideration?
As for Marvellt he Xenon controller is pretty complicated IP, which
consists of standard Sd/Mmc part and the dedicated PHY, that's
responsible for signal integrity for all bus modes. It requires
additional configuration, depending on the mode.
>
> I am wondering if this kind of customization is common among the SD & eMMC devices.
Well, in Linux this clock tuning after switching to certain bus mode.
This driver simply does it in 'set_ios' callback, whose custom
implementation (platform-specific code surrounding generic
sdhci_set_ios call) is _very_ common among all drivers/mmc/host
drivers.
Do you have any objections to the patch itself, given above explanation?
Best regards,
Marcin
>
> Best Regards,
> Hao Wu
>
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> > ---
> > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 1 +
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 60
> > ++++++++++++++++++++
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 18 ++++++
> > 3 files changed, 79 insertions(+)
> >
> > diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > index 25db98a..d9daada 100644
> > --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > @@ -33,6 +33,7 @@ typedef enum {
> > EdkiiSdMmcInitHostPre,
> > EdkiiSdMmcInitHostPost,
> > EdkiiSdMmcUhsSignaling,
> > + EdkiiSdMmcSwitchClockFreqPost,
> > } EDKII_SD_MMC_PHASE_TYPE;
> >
> > /**
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > index 05bd4a0..7e75283 100755
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > @@ -796,6 +796,27 @@ EmmcSwitchToHighSpeed (
> >
> > HsTiming = 1;
> > Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming,
> > ClockFreq);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > +
> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> > + Status = mOverride->NotifyPhase (
> > + Private->ControllerHandle,
> > + Slot,
> > + EdkiiSdMmcSwitchClockFreqPost,
> > + &Timing
> > + );
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((
> > + DEBUG_ERROR,
> > + "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
> > + __FUNCTION__,
> > + Status
> > + ));
> > + return Status;
> > + }
> > + }
> >
> > return Status;
> > }
> > @@ -905,6 +926,24 @@ EmmcSwitchToHS200 (
> > return Status;
> > }
> >
> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> > + Status = mOverride->NotifyPhase (
> > + Private->ControllerHandle,
> > + Slot,
> > + EdkiiSdMmcSwitchClockFreqPost,
> > + &Timing
> > + );
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((
> > + DEBUG_ERROR,
> > + "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
> > + __FUNCTION__,
> > + Status
> > + ));
> > + return Status;
> > + }
> > + }
> > +
> > Status = EmmcTuningClkForHs200 (PciIo, PassThru, Slot, BusWidth);
> >
> > return Status;
> > @@ -989,6 +1028,27 @@ EmmcSwitchToHS400 (
> >
> > HsTiming = 3;
> > Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming,
> > ClockFreq);
> > + if (EFI_ERROR (Status)) {
> > + return Status;
> > + }
> > +
> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> > + Status = mOverride->NotifyPhase (
> > + Private->ControllerHandle,
> > + Slot,
> > + EdkiiSdMmcSwitchClockFreqPost,
> > + &Timing
> > + );
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((
> > + DEBUG_ERROR,
> > + "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
> > + __FUNCTION__,
> > + Status
> > + ));
> > + return Status;
> > + }
> > + }
> >
> > return Status;
> > }
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > index 5645a71..057a4e2 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > @@ -887,6 +887,24 @@ SdCardSetBusMode (
> > return Status;
> > }
> >
> > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> > + Status = mOverride->NotifyPhase (
> > + Private->ControllerHandle,
> > + Slot,
> > + EdkiiSdMmcSwitchClockFreqPost,
> > + &Timing
> > + );
> > + if (EFI_ERROR (Status)) {
> > + DEBUG ((
> > + DEBUG_ERROR,
> > + "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
> > + __FUNCTION__,
> > + Status
> > + ));
> > + return Status;
> > + }
> > + }
> > +
> > if ((AccessMode == 3) || ((AccessMode == 2) && (Capability-
> > >TuningSDR50 != 0))) {
> > Status = SdCardTuningClock (PciIo, PassThru, Slot);
> > if (EFI_ERROR (Status)) {
> > --
> > 2.7.4
> >
> > _______________________________________________
> > edk2-devel mailing list
> > edk2-devel@lists.01.org
> > https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 4/4] MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequency
2018-11-01 7:11 ` Wu, Hao A
@ 2018-11-02 9:52 ` Marcin Wojtas
0 siblings, 0 replies; 47+ messages in thread
From: Marcin Wojtas @ 2018-11-02 9:52 UTC (permalink / raw)
To: hao.a.wu
Cc: edk2-devel-01, Kinney, Michael D, Gao, Liming, Leif Lindholm,
Ard Biesheuvel, nadavh, jsd@semihalf.com, Tomasz Michalec
Hi Hao,
czw., 1 lis 2018 o 08:11 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
>
> Hi Marcin,
>
> > -----Original Message-----
> > From: Marcin Wojtas [mailto:mw@semihalf.com]
> > Sent: Friday, October 05, 2018 9:25 PM
> > To: edk2-devel@lists.01.org
> > Cc: Tian, Feng; Kinney, Michael D; Gao, Liming; leif.lindholm@linaro.org; Wu,
> > Hao A; ard.biesheuvel@linaro.org; nadavh@marvell.com;
> > mw@semihalf.com; jsd@semihalf.com; tm@semihalf.com
> > Subject: [PATCH v2 4/4] MdeModulePkg/SdMmcPciHcDxe: Allow overriding
> > base clock frequency
> >
> > Some SdMmc host controllers are run by clocks with different
> > frequency than it is reflected in Capabilities Register 1.
> > It is allowed by SDHCI specification ver. 4.2 - if BaseClkFreq
> > field value of the Capability Register 1 is zero, the clock
> > frequency must be obtained via another method.
> >
> > Because the bitfield is only 8 bits wide, a maximum value
> > that could be obtained from hardware is 255MHz.
> > In case the actual frequency exceeds 255MHz, the 8-bit BaseClkFreq
> > member of SD_MMC_HC_SLOT_CAP structure occurs to be not sufficient
> > to be used for setting the clock speed in SdMmcHcClockSupply
> > function.
> >
> > This patch adds new UINT32 array ('BaseClkFreq[]') to
> > SD_MMC_HC_PRIVATE_DATA structure for specifying
> > the input clock speed for each slot of the host controller.
> > All routines that are used for clock configuration are
> > updated accordingly.
> >
> > This patch also adds new IN OUT BaseClockFreq field
> > in the Capability callback of the SdMmcOverride,
> > protocol which allows to update BaseClkFreq value.
> >
> > The patch reuses original commit from edk2-platforms:
> > 20f6f144d3a8 ("Marvell/Drivers: XenonDxe: Allow overriding base clock
> > frequency")
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> > ---
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 6 +++++
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 12 +++++----
> > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 5 +++-
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 4 +--
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 4 +--
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 18
> > +++++++++++--
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 27
> > +++++++++++---------
> > 7 files changed, 52 insertions(+), 24 deletions(-)
> >
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> > index c683600..8c1a589 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h
> > @@ -118,6 +118,12 @@ typedef struct {
> > UINT64 MaxCurrent[SD_MMC_HC_MAX_SLOT];
> >
> > UINT32 ControllerVersion;
> > +
> > + //
> > + // Some controllers may require to override base clock frequency
> > + // value stored in Capabilities Register 1.
> > + //
> > + UINT32 BaseClkFreq[SD_MMC_HC_MAX_SLOT];
> > } SD_MMC_HC_PRIVATE_DATA;
> >
> > #define SD_MMC_HC_TRB_SIG SIGNATURE_32 ('T', 'R', 'B', 'T')
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > index a03160d..f01ba21 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > @@ -173,12 +173,14 @@ typedef struct {
> >
> > @param[in] Slot The slot number of the SD card to send the
> > command to.
> > @param[in] Capability The buffer to store the capability data.
> > + @param[in] BaseClkFreq The base clock frequency of host controller in
> > MHz.
> >
> > **/
> > VOID
> > DumpCapabilityReg (
> > IN UINT8 Slot,
> > - IN SD_MMC_HC_SLOT_CAP *Capability
> > + IN SD_MMC_HC_SLOT_CAP *Capability,
> > + IN UINT32 BaseClkFreq
> > );
> >
> > /**
> > @@ -431,7 +433,7 @@ SdMmcHcStopClock (
> > @param[in] PciIo The PCI IO protocol instance.
> > @param[in] Slot The slot number of the SD card to send the
> > command to.
> > @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
> > - @param[in] Capability The capability of the slot.
> > + @param[in] BaseClkFreq The base clock frequency of host controller in
> > MHz.
> >
> > @retval EFI_SUCCESS The clock is supplied successfully.
> > @retval Others The clock isn't supplied successfully.
> > @@ -442,7 +444,7 @@ SdMmcHcClockSupply (
> > IN EFI_PCI_IO_PROTOCOL *PciIo,
> > IN UINT8 Slot,
> > IN UINT64 ClockFreq,
> > - IN SD_MMC_HC_SLOT_CAP Capability
> > + IN UINT32 BaseClkFreq
> > );
> >
> > /**
> > @@ -490,7 +492,7 @@ SdMmcHcSetBusWidth (
> >
> > @param[in] PciIo The PCI IO protocol instance.
> > @param[in] Slot The slot number of the SD card to send the
> > command to.
> > - @param[in] Capability The capability of the slot.
> > + @param[in] BaseClkFreq The base clock frequency of host controller in
> > MHz.
> >
> > @retval EFI_SUCCESS The clock is supplied successfully.
> > @retval Others The clock isn't supplied successfully.
> > @@ -500,7 +502,7 @@ EFI_STATUS
> > SdMmcHcInitClockFreq (
> > IN EFI_PCI_IO_PROTOCOL *PciIo,
> > IN UINT8 Slot,
> > - IN SD_MMC_HC_SLOT_CAP Capability
> > + IN UINT32 BaseClkFreq
> > );
> >
> > /**
> > diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > index d9daada..27023d3 100644
> > --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > @@ -43,6 +43,8 @@ typedef enum {
> > @param[in] ControllerHandle The EFI_HANDLE of the controller.
> > @param[in] Slot The 0 based slot index.
> > @param[in,out] SdMmcHcSlotCapability The SDHCI capability structure.
> > + @param[in,out] BaseClkFreq The base clock frequency value that
> > + optionally can be updated.
> >
> > @retval EFI_SUCCESS The override function completed successfully.
> > @retval EFI_NOT_FOUND The specified controller or slot does not
> > exist.
> > @@ -54,7 +56,8 @@ EFI_STATUS
> > (EFIAPI * EDKII_SD_MMC_CAPABILITY) (
> > IN EFI_HANDLE ControllerHandle,
> > IN UINT8 Slot,
> > - IN OUT VOID *SdMmcHcSlotCapability
> > + IN OUT VOID *SdMmcHcSlotCapability,
> > + IN OUT UINT32 *BaseClkFreq
> > );
> >
> > /**
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > index 7e75283..27ccd63 100755
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > @@ -705,7 +705,7 @@ EmmcSwitchClockFreq (
> > //
> > // Convert the clock freq unit from MHz to KHz.
> > //
> > - Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private-
> > >Capability[Slot]);
> > + Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private-
> > >BaseClkFreq[Slot]);
> >
> > return Status;
> > }
> > @@ -1099,7 +1099,7 @@ EmmcSetBusMode (
> > return Status;
> > }
> >
> > - ASSERT (Private->Capability[Slot].BaseClkFreq != 0);
> > + ASSERT (Private->BaseClkFreq[Slot] != 0);
> > //
> > // Check if the Host Controller support 8bits bus width.
> > //
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > index 057a4e2..9ea13be 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > @@ -882,7 +882,7 @@ SdCardSetBusMode (
> > }
> > }
> >
> > - Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capability);
> > + Status = SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private-
> > >BaseClkFreq[Slot]);
> > if (EFI_ERROR (Status)) {
> > return Status;
> > }
> > @@ -1081,7 +1081,7 @@ SdCardIdentification (
> > goto Error;
> > }
> >
> > - SdMmcHcInitClockFreq (PciIo, Slot, Private->Capability[Slot]);
> > + SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot]);
> >
> > gBS->Stall (1000);
> >
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
> > index bf9869d..d7cc0ce 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c
> > @@ -625,18 +625,32 @@ SdMmcPciHcDriverBindingStart (
> > if (EFI_ERROR (Status)) {
> > continue;
> > }
> > +
> > + Private->BaseClkFreq[Slot] = Private->Capability[Slot].BaseClkFreq;
> > +
> > if (mOverride != NULL && mOverride->Capability != NULL) {
> > Status = mOverride->Capability (
> > Controller,
> > Slot,
> > - &Private->Capability[Slot]);
> > + &Private->Capability[Slot],
> > + &Private->BaseClkFreq[Slot]
> > + );
> > if (EFI_ERROR (Status)) {
> > DEBUG ((DEBUG_WARN, "%a: Failed to override capability - %r\n",
> > __FUNCTION__, Status));
> > continue;
> > }
> > }
> > - DumpCapabilityReg (Slot, &Private->Capability[Slot]);
> > +
> > + //
> > + // According to SDHCI specification ver. 4.2, BaseClkFreq field value of
> > + // the Capability Register 1 can be zero, which means a need for
> > obtaining
> > + // the clock frequency via another method. Fail in case it is not updated
> > + // by SW at this point.
> > + //
> > + ASSERT (Private->BaseClkFreq[Slot] != 0);
>
> I think the ASSERT here can be dropped. This value will be handled within
> function SdMmcHcInitClockFreq(). And the above newly added comments can be used
> in SdMmcHcInitClockFreq() instead.
Right, I missed it - I will remove the ASSERT here, as the protection
against 0 value is already there.
>
> > +
> > + DumpCapabilityReg (Slot, &Private->Capability[Slot], Private-
> > >BaseClkFreq[Slot]);
>
> My thought on this one is that you can leave DumpCapabilityReg() unchanged and
> append a DEBUG() call with DEBUG_INFO level to output the value of
> Private->BaseClkFreq for a slot.
Ok, I will append the print separately.
Thanks,
Marcin
> >
> > Support64BitDma &= Private->Capability[Slot].SysBus64;
> >
> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > index 38d6202..9f50754 100644
> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c
> > @@ -22,12 +22,14 @@
> >
> > @param[in] Slot The slot number of the SD card to send the
> > command to.
> > @param[in] Capability The buffer to store the capability data.
> > + @param[in] BaseClkFreq The base clock frequency of host controller in
> > MHz.
> >
> > **/
> > VOID
> > DumpCapabilityReg (
> > IN UINT8 Slot,
> > - IN SD_MMC_HC_SLOT_CAP *Capability
> > + IN SD_MMC_HC_SLOT_CAP *Capability,
> > + IN UINT32 BaseClkFreq
> > )
> > {
> > //
> > @@ -35,7 +37,10 @@ DumpCapabilityReg (
> > //
> > DEBUG ((DEBUG_INFO, " == Slot [%d] Capability is 0x%x ==\n", Slot,
> > Capability));
> > DEBUG ((DEBUG_INFO, " Timeout Clk Freq %d%a\n", Capability-
> > >TimeoutFreq, (Capability->TimeoutUnit) ? "MHz" : "KHz"));
> > - DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", Capability-
> > >BaseClkFreq));
> > + if (Capability->BaseClkFreq != BaseClkFreq) {
> > + DEBUG ((DEBUG_INFO, " Controller register value overriden:\n"));
> > + }
> > + DEBUG ((DEBUG_INFO, " Base Clk Freq %dMHz\n", BaseClkFreq));
> > DEBUG ((DEBUG_INFO, " Max Blk Len %dbytes\n", 512 * (1 <<
> > Capability->MaxBlkLen)));
> > DEBUG ((DEBUG_INFO, " 8-bit Support %a\n", Capability->BusWidth8 ?
> > "TRUE" : "FALSE"));
> > DEBUG ((DEBUG_INFO, " ADMA2 Support %a\n", Capability->Adma2 ?
> > "TRUE" : "FALSE"));
> > @@ -721,7 +726,7 @@ SdMmcHcStopClock (
> > @param[in] PciIo The PCI IO protocol instance.
> > @param[in] Slot The slot number of the SD card to send the
> > command to.
> > @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.
> > - @param[in] Capability The capability of the slot.
> > + @param[in] BaseClkFreq The base clock frequency of host controller in
> > MHz.
> >
> > @retval EFI_SUCCESS The clock is supplied successfully.
> > @retval Others The clock isn't supplied successfully.
> > @@ -732,11 +737,10 @@ SdMmcHcClockSupply (
> > IN EFI_PCI_IO_PROTOCOL *PciIo,
> > IN UINT8 Slot,
> > IN UINT64 ClockFreq,
> > - IN SD_MMC_HC_SLOT_CAP Capability
> > + IN UINT32 BaseClkFreq
> > )
> > {
> > EFI_STATUS Status;
> > - UINT32 BaseClkFreq;
> > UINT32 SettingFreq;
> > UINT32 Divisor;
> > UINT32 Remainder;
> > @@ -746,9 +750,8 @@ SdMmcHcClockSupply (
> > //
> > // Calculate a divisor for SD clock frequency
> > //
> > - ASSERT (Capability.BaseClkFreq != 0);
> > + ASSERT (BaseClkFreq != 0);
> >
> > - BaseClkFreq = Capability.BaseClkFreq;
> > if (ClockFreq == 0) {
> > return EFI_INVALID_PARAMETER;
> > }
> > @@ -939,7 +942,7 @@ SdMmcHcSetBusWidth (
> >
> > @param[in] PciIo The PCI IO protocol instance.
> > @param[in] Slot The slot number of the SD card to send the
> > command to.
> > - @param[in] Capability The capability of the slot.
> > + @param[in] BaseClkFreq The base clock frequency of host controller in
> > MHz.
> >
> > @retval EFI_SUCCESS The clock is supplied successfully.
> > @retval Others The clock isn't supplied successfully.
> > @@ -949,7 +952,7 @@ EFI_STATUS
> > SdMmcHcInitClockFreq (
> > IN EFI_PCI_IO_PROTOCOL *PciIo,
> > IN UINT8 Slot,
> > - IN SD_MMC_HC_SLOT_CAP Capability
> > + IN UINT32 BaseClkFreq
> > )
> > {
> > EFI_STATUS Status;
> > @@ -958,7 +961,7 @@ SdMmcHcInitClockFreq (
> > //
> > // Calculate a divisor for SD clock frequency
> > //
> > - if (Capability.BaseClkFreq == 0) {
> > + if (BaseClkFreq == 0) {
> > //
> > // Don't support get Base Clock Frequency information via another
> > method
> > //
> > @@ -968,7 +971,7 @@ SdMmcHcInitClockFreq (
> > // Supply 400KHz clock frequency at initialization phase.
> > //
> > InitFreq = 400;
> > - Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, Capability);
> > + Status = SdMmcHcClockSupply (PciIo, Slot, InitFreq, BaseClkFreq);
> > return Status;
> > }
> >
> > @@ -1102,7 +1105,7 @@ SdMmcHcInitHost (
> > PciIo = Private->PciIo;
> > Capability = Private->Capability[Slot];
> >
> > - Status = SdMmcHcInitClockFreq (PciIo, Slot, Capability);
> > + Status = SdMmcHcInitClockFreq (PciIo, Slot, Private->BaseClkFreq[Slot]);
> > if (EFI_ERROR (Status)) {
> > return Status;
> > }
> > --
> > 2.7.4
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 0/4] SdMmcOverride extension
2018-11-01 7:11 ` Wu, Hao A
@ 2018-11-02 10:09 ` Marcin Wojtas
0 siblings, 0 replies; 47+ messages in thread
From: Marcin Wojtas @ 2018-11-02 10:09 UTC (permalink / raw)
To: hao.a.wu
Cc: Ard Biesheuvel, edk2-devel-01, Kinney, Michael D, Gao, Liming,
Leif Lindholm, nadavh, jsd@semihalf.com, Tomasz Michalec
Hao,
czw., 1 lis 2018 o 08:11 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
>
> Hi Marcin and Ard,
>
> > -----Original Message-----
> > From: Marcin Wojtas [mailto:mw@semihalf.com]
> > Sent: Friday, October 05, 2018 9:25 PM
> > To: edk2-devel@lists.01.org
> > Cc: Tian, Feng; Kinney, Michael D; Gao, Liming; leif.lindholm@linaro.org; Wu,
> > Hao A; ard.biesheuvel@linaro.org; nadavh@marvell.com;
> > mw@semihalf.com; jsd@semihalf.com; tm@semihalf.com
> > Subject: [PATCH v2 0/4] SdMmcOverride extension
> >
> > Hi,
> >
> > This is the second version of the patchset. Initial one was
> > interleaved with the fixes, which after split got already merged.
> > The biggest change is - resigning from the new callbacks
> > and extending parameter lists of both NotifyPhase and Capability
> > routines.
> >
> > Patches are available in the github:
> > https://github.com/MarvellEmbeddedProcessors/edk2-open-
> > platform/commits/sdmmc-override-upstream-r20181005
> >
> > Please note that extending SdMmcOverride protocol was impacting
> > so far the only user of it (Synquacer controller). In paralel
> > edk2-platforms patchset, a patch can be found:
> > ("Silicon/SynQuacer/PlatformDxe: adjust to updated SdMmcOverride")
> > which immunizes for above and future extensions of the protocol:
> > https://github.com/MarvellEmbeddedProcessors/edk2-open-
> > platform/commits/xenon-upstream-r20181005
> >
> > I'm looking forward to the comments and remarks.
>
> Since there are protocol service interface changes, maybe a version change
> (macro EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION) for the SdMmc Override Protocol
> is needed.
>
> Please share your thoughts on this one. Thanks.
IMO such change is justified. I can add it in a separate on top, you
can decide later with Ard, if it's good to merge it.
Best regards,
Marcin
>
> Best Regards,
> Hao Wu
>
> >
> > Best regards,
> > Marcin
> >
> > Changelog:
> > v1 -> v2
> > * Rebase onto newest master
> > * 1/4 [new patch] - preparation for extending NotifyPhase
> > * 2/4 - UhsSignaling as a part of NotifyPhase
> > * 3/4 - SwitchClockFreqPost as a part of NotifyPhase
> > * 4/4 - Allow updating BaseClkFreq via Capability instead of the
> > independent callback.
> >
> > Marcin Wojtas (2):
> > MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in
> > NotifyPhase
> > MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequency
> >
> > Tomasz Michalec (2):
> > MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride
> > protocol
> > MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to
> > SdMmcOverride
> >
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 6 +
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 62 +++++-
> > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 12 +-
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 215
> > ++++++++++++++------
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 57 +++++-
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 18 +-
> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 108 ++++++++-
> > -
> > 7 files changed, 383 insertions(+), 95 deletions(-)
> >
> > --
> > 2.7.4
>
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-11-02 8:21 ` Marcin Wojtas
@ 2018-11-02 12:16 ` Marcin Wojtas
2018-11-03 2:57 ` Wu, Hao A
0 siblings, 1 reply; 47+ messages in thread
From: Marcin Wojtas @ 2018-11-02 12:16 UTC (permalink / raw)
To: hao.a.wu
Cc: edk2-devel-01, Kinney, Michael D, Gao, Liming, Leif Lindholm,
Ard Biesheuvel, nadavh, jsd@semihalf.com, Tomasz Michalec
pt., 2 lis 2018 o 09:21 Marcin Wojtas <mw@semihalf.com> napisał(a):
>
> Hi Hao,
>
> czw., 1 lis 2018 o 08:06 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
> >
> > Hi Marcin,
> >
> > > -----Original Message-----
> > > From: Marcin Wojtas [mailto:mw@semihalf.com]
> > > Sent: Friday, October 05, 2018 9:25 PM
> > > To: edk2-devel@lists.01.org
> > > Cc: Tian, Feng; Kinney, Michael D; Gao, Liming; leif.lindholm@linaro.org; Wu,
> > > Hao A; ard.biesheuvel@linaro.org; nadavh@marvell.com;
> > > mw@semihalf.com; jsd@semihalf.com; tm@semihalf.com
> > > Subject: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling
> > > to SdMmcOverride protocol
> > >
> > > From: Tomasz Michalec <tm@semihalf.com>
> > >
> > > Some SD Host Controlers use different values in Host Control 2 Register
> > > to select UHS Mode. This patch adds a new UhsSignaling type routine to
> > > the NotifyPhase of the SdMmcOverride protocol.
> > >
> > > UHS signaling configuration is moved to a common, default routine
> > > (SdMmcHcUhsSignaling), which is called when SdMmcOverride does not
> > > cover this functionality.
> > >
> > > Contributed-under: TianoCore Contribution Agreement 1.1
> > > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> > > ---
> > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 50 +++++++
> > > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 2 +
> > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 153
> > > ++++++++++++--------
> > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 37 +++--
> > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 69 +++++++++
> > > 5 files changed, 243 insertions(+), 68 deletions(-)
> > >
> > > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > > index e389d52..a03160d 100644
> > > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > > @@ -63,6 +63,39 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF
> > > ANY KIND, EITHER EXPRESS OR IMPLIED.
> > > #define SD_MMC_HC_CTRL_VER 0xFE
> > >
> > > //
> > > +// SD Host Controler bits to HOST_CTRL2 register
> > > +//
> > > +#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
> > > +#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
> > > +#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
> > > +#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
> > > +#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
> > > +#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
> > > +#define SD_MMC_HC_CTRL_MMC_DDR52 0x0004
> > > +#define SD_MMC_HC_CTRL_MMC_SDR50 0x0002
> >
> > I think SD_MMC_HC_CTRL_MMC_SDR50 is not needed here.
> >
> > Since according to the SD Physical Layer Simplified Specification, max clock
> > frequency for SD bus mode SDR50 is 100MHz. And there is no eMMC bus mode whose
> > max clock frequency is at 100MHz in Embedded Multi-Media Card Electrical
> > Standard (5.1).
>
> Ok, will drop it.
>
> >
> > > +#define SD_MMC_HC_CTRL_MMC_SDR25 0x0001
> > > +#define SD_MMC_HC_CTRL_MMC_SDR12 0x0000
> > > +#define SD_MMC_HC_CTRL_HS200 0x0003
> > > +#define SD_MMC_HC_CTRL_HS400 0x0005
> >
> > How about the below renames & reorder?
> >
> > SD_MMC_HC_CTRL_MMC_LEGACY 0x0000
> > SD_MMC_HC_CTRL_MMC_HS_SDR 0x0001
> > SD_MMC_HC_CTRL_MMC_HS_DDR 0x0004
> > SD_MMC_HC_CTRL_MMC_HS200 0x0003
> > SD_MMC_HC_CTRL_MMC_HS400 0x0005
>
> Ok.
>
> >
> > > +
> > > +//
> > > +// Timing modes for uhs
> > > +//
> > > +typedef enum {
> > > + SdMmcUhsSdr12,
> > > + SdMmcUhsSdr25,
> > > + SdMmcUhsSdr50,
> > > + SdMmcUhsSdr104,
> > > + SdMmcUhsDdr50,
> > > + SdMmcMmcDdr52,
> > > + SdMmcMmcSdr50,
> > > + SdMmcMmcSdr25,
> > > + SdMmcMmcSdr12,
> > > + SdMmcMmcHs200,
> > > + SdMmcMmcHs400,
> > > +} SD_MMC_UHS_TIMING;
> >
> > Suggest a similar drop of 'SdMmcMmcSdr50' and rename according to the above
> > comments upon HOST_CTRL2 register value definitions. Also, how about a rename
> > for enum to SD_MMC_BUS_MODE?
>
> Ok.
>
> >
> > > +
> > > +//
> > > // The transfer modes supported by SD Host Controller
> > > // Simplified Spec 3.0 Table 1-2
> > > //
> > > @@ -508,4 +541,21 @@ SdMmcHcInitTimeoutCtrl (
> > > IN UINT8 Slot
> > > );
> > >
> > > +/**
> > > + Set SD Host Controler control 2 registry according to selected speed.
> > > +
> > > + @param[in] PciIo The PCI IO protocol instance.
> > > + @param[in] Slot The slot number of the SD card to send the
> > > command to.
> > > + @param[in] Timing The timing to select.
> > > +
> > > + @retval EFI_SUCCESS The timing is set successfully.
> > > + @retval Others The timing isn't set successfully.
> > > +**/
> > > +EFI_STATUS
> > > +SdMmcHcUhsSignaling (
> > > + IN EFI_PCI_IO_PROTOCOL *PciIo,
> > > + IN UINT8 Slot,
> > > + IN SD_MMC_UHS_TIMING Timing
> > > + );
> > > +
> > > #endif
> > > diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > > b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > > index 178945f..25db98a 100644
> > > --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > > +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > > @@ -17,6 +17,7 @@
> > > #ifndef __SD_MMC_OVERRIDE_H__
> > > #define __SD_MMC_OVERRIDE_H__
> > >
> > > +#include <Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h>
> >
> > Please do not expose a module private header file here.
> >
> > One approach comes to me is to keep the SD/MMC bus mode enumeration structure
> > in this protocol header file. SdMmcPciHcDxe driver and producers of the
> > Override protocol keep a version of the HOST_CTRL2 register value macros of
> > their own.
>
> Agree. I will move necessary defines to
> Include/Protocol/SdMmcOverride.h instead of exposing SdMmcPciHci.h.
> HOST_CTRL2 contents will be a local define in producer code.
>
> >
> > > #include <Protocol/SdMmcPassThru.h>
> > >
> > > #define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \
> > > @@ -31,6 +32,7 @@ typedef enum {
> > > EdkiiSdMmcResetPost,
> > > EdkiiSdMmcInitHostPre,
> > > EdkiiSdMmcInitHostPost,
> > > + EdkiiSdMmcUhsSignaling,
> > > } EDKII_SD_MMC_PHASE_TYPE;
> > >
> > > /**
> > > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > > index c5fd214..05bd4a0 100755
> > > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > > @@ -740,10 +740,13 @@ EmmcSwitchToHighSpeed (
> > > IN UINT8 BusWidth
> > > )
> > > {
> > > - EFI_STATUS Status;
> > > - UINT8 HsTiming;
> > > - UINT8 HostCtrl1;
> > > - UINT8 HostCtrl2;
> > > + EFI_STATUS Status;
> > > + UINT8 HsTiming;
> > > + UINT8 HostCtrl1;
> > > + SD_MMC_UHS_TIMING Timing;
> > > + SD_MMC_HC_PRIVATE_DATA *Private;
> > > +
> > > + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> > >
> > > Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusWidth);
> > > if (EFI_ERROR (Status)) {
> > > @@ -758,27 +761,37 @@ EmmcSwitchToHighSpeed (
> > > return Status;
> > > }
> > >
> > > - //
> > > - // Clean UHS Mode Select field of Host Control 2 reigster before update
> > > - //
> > > - HostCtrl2 = (UINT8)~0x7;
> > > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2,
> > > sizeof (HostCtrl2), &HostCtrl2);
> > > - if (EFI_ERROR (Status)) {
> > > - return Status;
> > > - }
> > > - //
> > > - // Set UHS Mode Select field of Host Control 2 reigster to SDR12/25/50
> > > - //
> > > if (IsDdr) {
> > > - HostCtrl2 = BIT2;
> > > + Timing = SdMmcMmcDdr52;
> > > } else if (ClockFreq == 52) {
> > > - HostCtrl2 = BIT0;
> > > + Timing = SdMmcMmcSdr50;
> > > + } else if (ClockFreq == 26) {
> > > + Timing = SdMmcMmcSdr25;
> > > } else {
> > > - HostCtrl2 = 0;
> > > + Timing = SdMmcMmcSdr12;
> > > }
> >
> > As mentioned above, "SdMmcMmcSdr50" can be dropped here.
> > And considering the rename above, how about:
> >
> > if (IsDdr) {
> > Timing = SdMmcMmcHsDdr;
> > } else if (ClockFreq == 52) {
> > Timing = SdMmcMmcHsSdr;
> > } else {
> > Timing = SdMmcMmcLegacy;
> > }
>
> Ok.
>
> >
> > > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof
> > > (HostCtrl2), &HostCtrl2);
> > > - if (EFI_ERROR (Status)) {
> > > - return Status;
> > > +
> > > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> > > + Status = mOverride->NotifyPhase (
> > > + Private->ControllerHandle,
> > > + Slot,
> > > + EdkiiSdMmcUhsSignaling,
> > > + &Timing
> > > + );
> > > + if (EFI_ERROR (Status)) {
> > > + DEBUG ((
> > > + DEBUG_ERROR,
> > > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> > > + __FUNCTION__,
> > > + Status
> > > + ));
> > > + return Status;
> > > + }
> > > + } else {
> > > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> > > + if (EFI_ERROR (Status)) {
> > > + return Status;
> > > + }
> > > }
> >
> > I have concern for this, current existing hook points for the NotifyPhase()
> > service are performing additional operations during the controller
> > initialization process.
> >
> > Producer of the override protocol can simply return EFI_SUCCESS, if there is
> > nothing to do for a specific hook point.
> >
> > But this hook here is to override the behavior when setting the "UHS Mode
> > Select" field of Host Control 2 Register. If the override protocol producer
> > does not want to override the behavior at the 'EdkiiSdMmcUhsSignaling' hook,
> > but has to do something in other hooks, one cannot directly return EFI_SUCCESS
> > for the 'EdkiiSdMmcUhsSignaling' hook. For this case, one has to implement the
> > 'EdkiiSdMmcUhsSignaling' hook even if the behavior will be exactly the same as
> > the SdMmcPciHcDxe driver.
>
> I see your point. It's not additional code, but replacing the default.
> IMO the easiest way to handle it is to go back to a separate
> UhsSignaling callback, so that it's either omitted or explicitly
> defined by Override protocol producer driver. What do you think?
>
Second thought here, as previously I discussed a lot with Ard, how to
keep only Notify and Capability callbacks. I think the best compromise
would be to call SdMmcHcUhsSignaling unconditionally before
SdMmcOverride callback. In case the producer does nothing, the
defaults would be used. This way, in case of deviations from standard,
the the producer driver would have to handle updating only affected
timing values.
Best regards,
Marcin
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol
2018-11-02 12:16 ` Marcin Wojtas
@ 2018-11-03 2:57 ` Wu, Hao A
0 siblings, 0 replies; 47+ messages in thread
From: Wu, Hao A @ 2018-11-03 2:57 UTC (permalink / raw)
To: Marcin Wojtas
Cc: edk2-devel-01, Kinney, Michael D, Gao, Liming, Leif Lindholm,
Ard Biesheuvel, nadavh@marvell.com, jsd@semihalf.com,
Tomasz Michalec
> -----Original Message-----
> From: Marcin Wojtas [mailto:mw@semihalf.com]
> Sent: Friday, November 02, 2018 8:17 PM
> To: Wu, Hao A
> Cc: edk2-devel-01; Kinney, Michael D; Gao, Liming; Leif Lindholm; Ard
> Biesheuvel; nadavh@marvell.com; jsd@semihalf.com; Tomasz Michalec
> Subject: Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling
> to SdMmcOverride protocol
>
> pt., 2 lis 2018 o 09:21 Marcin Wojtas <mw@semihalf.com> napisał(a):
> >
> > Hi Hao,
> >
> > czw., 1 lis 2018 o 08:06 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
> > >
> > > Hi Marcin,
> > >
> > > > -----Original Message-----
> > > > From: Marcin Wojtas [mailto:mw@semihalf.com]
> > > > Sent: Friday, October 05, 2018 9:25 PM
> > > > To: edk2-devel@lists.01.org
> > > > Cc: Tian, Feng; Kinney, Michael D; Gao, Liming; leif.lindholm@linaro.org;
> Wu,
> > > > Hao A; ard.biesheuvel@linaro.org; nadavh@marvell.com;
> > > > mw@semihalf.com; jsd@semihalf.com; tm@semihalf.com
> > > > Subject: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add
> UhsSignaling
> > > > to SdMmcOverride protocol
> > > >
> > > > From: Tomasz Michalec <tm@semihalf.com>
> > > >
> > > > Some SD Host Controlers use different values in Host Control 2 Register
> > > > to select UHS Mode. This patch adds a new UhsSignaling type routine to
> > > > the NotifyPhase of the SdMmcOverride protocol.
> > > >
> > > > UHS signaling configuration is moved to a common, default routine
> > > > (SdMmcHcUhsSignaling), which is called when SdMmcOverride does not
> > > > cover this functionality.
> > > >
> > > > Contributed-under: TianoCore Contribution Agreement 1.1
> > > > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> > > > ---
> > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 50 +++++++
> > > > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 2 +
> > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 153
> > > > ++++++++++++--------
> > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 37 +++--
> > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 69
> +++++++++
> > > > 5 files changed, 243 insertions(+), 68 deletions(-)
> > > >
> > > > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > > > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > > > index e389d52..a03160d 100644
> > > > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > > > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h
> > > > @@ -63,6 +63,39 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF
> > > > ANY KIND, EITHER EXPRESS OR IMPLIED.
> > > > #define SD_MMC_HC_CTRL_VER 0xFE
> > > >
> > > > //
> > > > +// SD Host Controler bits to HOST_CTRL2 register
> > > > +//
> > > > +#define SD_MMC_HC_CTRL_UHS_MASK 0x0007
> > > > +#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000
> > > > +#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001
> > > > +#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002
> > > > +#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003
> > > > +#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004
> > > > +#define SD_MMC_HC_CTRL_MMC_DDR52 0x0004
> > > > +#define SD_MMC_HC_CTRL_MMC_SDR50 0x0002
> > >
> > > I think SD_MMC_HC_CTRL_MMC_SDR50 is not needed here.
> > >
> > > Since according to the SD Physical Layer Simplified Specification, max clock
> > > frequency for SD bus mode SDR50 is 100MHz. And there is no eMMC bus
> mode whose
> > > max clock frequency is at 100MHz in Embedded Multi-Media Card Electrical
> > > Standard (5.1).
> >
> > Ok, will drop it.
> >
> > >
> > > > +#define SD_MMC_HC_CTRL_MMC_SDR25 0x0001
> > > > +#define SD_MMC_HC_CTRL_MMC_SDR12 0x0000
> > > > +#define SD_MMC_HC_CTRL_HS200 0x0003
> > > > +#define SD_MMC_HC_CTRL_HS400 0x0005
> > >
> > > How about the below renames & reorder?
> > >
> > > SD_MMC_HC_CTRL_MMC_LEGACY 0x0000
> > > SD_MMC_HC_CTRL_MMC_HS_SDR 0x0001
> > > SD_MMC_HC_CTRL_MMC_HS_DDR 0x0004
> > > SD_MMC_HC_CTRL_MMC_HS200 0x0003
> > > SD_MMC_HC_CTRL_MMC_HS400 0x0005
> >
> > Ok.
> >
> > >
> > > > +
> > > > +//
> > > > +// Timing modes for uhs
> > > > +//
> > > > +typedef enum {
> > > > + SdMmcUhsSdr12,
> > > > + SdMmcUhsSdr25,
> > > > + SdMmcUhsSdr50,
> > > > + SdMmcUhsSdr104,
> > > > + SdMmcUhsDdr50,
> > > > + SdMmcMmcDdr52,
> > > > + SdMmcMmcSdr50,
> > > > + SdMmcMmcSdr25,
> > > > + SdMmcMmcSdr12,
> > > > + SdMmcMmcHs200,
> > > > + SdMmcMmcHs400,
> > > > +} SD_MMC_UHS_TIMING;
> > >
> > > Suggest a similar drop of 'SdMmcMmcSdr50' and rename according to the
> above
> > > comments upon HOST_CTRL2 register value definitions. Also, how about a
> rename
> > > for enum to SD_MMC_BUS_MODE?
> >
> > Ok.
> >
> > >
> > > > +
> > > > +//
> > > > // The transfer modes supported by SD Host Controller
> > > > // Simplified Spec 3.0 Table 1-2
> > > > //
> > > > @@ -508,4 +541,21 @@ SdMmcHcInitTimeoutCtrl (
> > > > IN UINT8 Slot
> > > > );
> > > >
> > > > +/**
> > > > + Set SD Host Controler control 2 registry according to selected speed.
> > > > +
> > > > + @param[in] PciIo The PCI IO protocol instance.
> > > > + @param[in] Slot The slot number of the SD card to send the
> > > > command to.
> > > > + @param[in] Timing The timing to select.
> > > > +
> > > > + @retval EFI_SUCCESS The timing is set successfully.
> > > > + @retval Others The timing isn't set successfully.
> > > > +**/
> > > > +EFI_STATUS
> > > > +SdMmcHcUhsSignaling (
> > > > + IN EFI_PCI_IO_PROTOCOL *PciIo,
> > > > + IN UINT8 Slot,
> > > > + IN SD_MMC_UHS_TIMING Timing
> > > > + );
> > > > +
> > > > #endif
> > > > diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > > > b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > > > index 178945f..25db98a 100644
> > > > --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > > > +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > > > @@ -17,6 +17,7 @@
> > > > #ifndef __SD_MMC_OVERRIDE_H__
> > > > #define __SD_MMC_OVERRIDE_H__
> > > >
> > > > +#include <Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h>
> > >
> > > Please do not expose a module private header file here.
> > >
> > > One approach comes to me is to keep the SD/MMC bus mode enumeration
> structure
> > > in this protocol header file. SdMmcPciHcDxe driver and producers of the
> > > Override protocol keep a version of the HOST_CTRL2 register value macros
> of
> > > their own.
> >
> > Agree. I will move necessary defines to
> > Include/Protocol/SdMmcOverride.h instead of exposing SdMmcPciHci.h.
> > HOST_CTRL2 contents will be a local define in producer code.
> >
> > >
> > > > #include <Protocol/SdMmcPassThru.h>
> > > >
> > > > #define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \
> > > > @@ -31,6 +32,7 @@ typedef enum {
> > > > EdkiiSdMmcResetPost,
> > > > EdkiiSdMmcInitHostPre,
> > > > EdkiiSdMmcInitHostPost,
> > > > + EdkiiSdMmcUhsSignaling,
> > > > } EDKII_SD_MMC_PHASE_TYPE;
> > > >
> > > > /**
> > > > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > > > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > > > index c5fd214..05bd4a0 100755
> > > > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > > > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > > > @@ -740,10 +740,13 @@ EmmcSwitchToHighSpeed (
> > > > IN UINT8 BusWidth
> > > > )
> > > > {
> > > > - EFI_STATUS Status;
> > > > - UINT8 HsTiming;
> > > > - UINT8 HostCtrl1;
> > > > - UINT8 HostCtrl2;
> > > > + EFI_STATUS Status;
> > > > + UINT8 HsTiming;
> > > > + UINT8 HostCtrl1;
> > > > + SD_MMC_UHS_TIMING Timing;
> > > > + SD_MMC_HC_PRIVATE_DATA *Private;
> > > > +
> > > > + Private = SD_MMC_HC_PRIVATE_FROM_THIS (PassThru);
> > > >
> > > > Status = EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr,
> BusWidth);
> > > > if (EFI_ERROR (Status)) {
> > > > @@ -758,27 +761,37 @@ EmmcSwitchToHighSpeed (
> > > > return Status;
> > > > }
> > > >
> > > > - //
> > > > - // Clean UHS Mode Select field of Host Control 2 reigster before update
> > > > - //
> > > > - HostCtrl2 = (UINT8)~0x7;
> > > > - Status = SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2,
> > > > sizeof (HostCtrl2), &HostCtrl2);
> > > > - if (EFI_ERROR (Status)) {
> > > > - return Status;
> > > > - }
> > > > - //
> > > > - // Set UHS Mode Select field of Host Control 2 reigster to SDR12/25/50
> > > > - //
> > > > if (IsDdr) {
> > > > - HostCtrl2 = BIT2;
> > > > + Timing = SdMmcMmcDdr52;
> > > > } else if (ClockFreq == 52) {
> > > > - HostCtrl2 = BIT0;
> > > > + Timing = SdMmcMmcSdr50;
> > > > + } else if (ClockFreq == 26) {
> > > > + Timing = SdMmcMmcSdr25;
> > > > } else {
> > > > - HostCtrl2 = 0;
> > > > + Timing = SdMmcMmcSdr12;
> > > > }
> > >
> > > As mentioned above, "SdMmcMmcSdr50" can be dropped here.
> > > And considering the rename above, how about:
> > >
> > > if (IsDdr) {
> > > Timing = SdMmcMmcHsDdr;
> > > } else if (ClockFreq == 52) {
> > > Timing = SdMmcMmcHsSdr;
> > > } else {
> > > Timing = SdMmcMmcLegacy;
> > > }
> >
> > Ok.
> >
> > >
> > > > - Status = SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2,
> sizeof
> > > > (HostCtrl2), &HostCtrl2);
> > > > - if (EFI_ERROR (Status)) {
> > > > - return Status;
> > > > +
> > > > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> > > > + Status = mOverride->NotifyPhase (
> > > > + Private->ControllerHandle,
> > > > + Slot,
> > > > + EdkiiSdMmcUhsSignaling,
> > > > + &Timing
> > > > + );
> > > > + if (EFI_ERROR (Status)) {
> > > > + DEBUG ((
> > > > + DEBUG_ERROR,
> > > > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n",
> > > > + __FUNCTION__,
> > > > + Status
> > > > + ));
> > > > + return Status;
> > > > + }
> > > > + } else {
> > > > + Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
> > > > + if (EFI_ERROR (Status)) {
> > > > + return Status;
> > > > + }
> > > > }
> > >
> > > I have concern for this, current existing hook points for the NotifyPhase()
> > > service are performing additional operations during the controller
> > > initialization process.
> > >
> > > Producer of the override protocol can simply return EFI_SUCCESS, if there is
> > > nothing to do for a specific hook point.
> > >
> > > But this hook here is to override the behavior when setting the "UHS Mode
> > > Select" field of Host Control 2 Register. If the override protocol producer
> > > does not want to override the behavior at the 'EdkiiSdMmcUhsSignaling'
> hook,
> > > but has to do something in other hooks, one cannot directly return
> EFI_SUCCESS
> > > for the 'EdkiiSdMmcUhsSignaling' hook. For this case, one has to implement
> the
> > > 'EdkiiSdMmcUhsSignaling' hook even if the behavior will be exactly the
> same as
> > > the SdMmcPciHcDxe driver.
> >
> > I see your point. It's not additional code, but replacing the default.
> > IMO the easiest way to handle it is to go back to a separate
> > UhsSignaling callback, so that it's either omitted or explicitly
> > defined by Override protocol producer driver. What do you think?
> >
>
> Second thought here, as previously I discussed a lot with Ard, how to
> keep only Notify and Capability callbacks. I think the best compromise
> would be to call SdMmcHcUhsSignaling unconditionally before
> SdMmcOverride callback. In case the producer does nothing, the
> defaults would be used. This way, in case of deviations from standard,
> the the producer driver would have to handle updating only affected
> timing values.
Yes, I was thinking quite the same:
A. Set the "UHS Mode Select" field more than 1 time
Abstracted code:
Status = SdMmcHcUhsSignaling (PciIo, Slot, Timing);
if (EFI_ERROR (Status)) {
return Status;
}
if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
Status = mOverride->NotifyPhase (EdkiiSdMmcUhsSignaling);
...
}
For this approach, I am not very sure if setting the "UHS Mode Select" field
multiple times will bring any side effect.
Another possible approach comes to my mind is that:
B. Introduce a new return status to the NotifyPhase() service to indicate
nothing has been done (in other words, the hook type is just ignored by the
implementation)
The current implementation of the NotifyPhase() service will return EFI_SUCCESS
when:
1) the additional operations finished successfully;
2) nothing has been done for a specific hook type.
I am thinking whether a new return status (like EFI_UNSUPPORTED) can be
introduced to distinguish the above 2 cases.
For this approach, the caller of the NotifyPhase() will then not treat this new
return status as a fatal error, and the initialization process should continue.
Best Regards,
Hao Wu
>
> Best regards,
> Marcin
^ permalink raw reply [flat|nested] 47+ messages in thread
* Re: [PATCH v2 3/4] MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to SdMmcOverride
2018-11-02 9:39 ` Marcin Wojtas
@ 2018-11-03 3:19 ` Wu, Hao A
0 siblings, 0 replies; 47+ messages in thread
From: Wu, Hao A @ 2018-11-03 3:19 UTC (permalink / raw)
To: Marcin Wojtas
Cc: edk2-devel-01, Tomasz Michalec, nadavh@marvell.com, Gao, Liming,
Kinney, Michael D
> -----Original Message-----
> From: Marcin Wojtas [mailto:mw@semihalf.com]
> Sent: Friday, November 02, 2018 5:39 PM
> To: Wu, Hao A
> Cc: edk2-devel-01; Tomasz Michalec; nadavh@marvell.com; Gao, Liming;
> Kinney, Michael D
> Subject: Re: [edk2] [PATCH v2 3/4] MdeModulePkg/SdMmcPciHcDxe: Add
> SwitchClockFreqPost to SdMmcOverride
>
> Hi Hao,
>
> czw., 1 lis 2018 o 08:06 Wu, Hao A <hao.a.wu@intel.com> napisał(a):
> >
> > > -----Original Message-----
> > > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> > > Marcin Wojtas
> > > Sent: Friday, October 05, 2018 9:25 PM
> > > To: edk2-devel@lists.01.org
> > > Cc: Tian, Feng; tm@semihalf.com; Wu, Hao A; nadavh@marvell.com; Gao,
> > > Liming; Kinney, Michael D
> > > Subject: [edk2] [PATCH v2 3/4] MdeModulePkg/SdMmcPciHcDxe: Add
> > > SwitchClockFreqPost to SdMmcOverride
> > >
> > > From: Tomasz Michalec <tm@semihalf.com>
> > >
> > > Some SD Host Controlers need to do additional opperations after clock
> > > frequency switch.
> > >
> > > This patch add new callback type to NotifyPhase of the SdMmcOverride
> > > protocol. It is called after EmmcSwitchClockFreq and SdMmcHcClockSupply.
> >
> > Hi Marcin,
> >
> > Just curious, I had a quick glance at the implementation of the
> > XenonSwitchClockFreqPost() in your platform part changes. Are those
> operations
> > within the function mandatory during the HC initialization? Are they mainly for
> > performance or stability consideration?
>
> As for Marvellt he Xenon controller is pretty complicated IP, which
> consists of standard Sd/Mmc part and the dedicated PHY, that's
> responsible for signal integrity for all bus modes. It requires
> additional configuration, depending on the mode.
Got it.
>
> >
> > I am wondering if this kind of customization is common among the SD &
> eMMC devices.
>
> Well, in Linux this clock tuning after switching to certain bus mode.
> This driver simply does it in 'set_ios' callback, whose custom
> implementation (platform-specific code surrounding generic
> sdhci_set_ios call) is _very_ common among all drivers/mmc/host
> drivers.
>
> Do you have any objections to the patch itself, given above explanation?
No, thanks for the detailed explanation.
Best Regards,
Hao Wu
>
> Best regards,
> Marcin
>
> >
> > Best Regards,
> > Hao Wu
> >
> > >
> > > Contributed-under: TianoCore Contribution Agreement 1.1
> > > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> > > ---
> > > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 1 +
> > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 60
> > > ++++++++++++++++++++
> > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 18 ++++++
> > > 3 files changed, 79 insertions(+)
> > >
> > > diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > > b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > > index 25db98a..d9daada 100644
> > > --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > > +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h
> > > @@ -33,6 +33,7 @@ typedef enum {
> > > EdkiiSdMmcInitHostPre,
> > > EdkiiSdMmcInitHostPost,
> > > EdkiiSdMmcUhsSignaling,
> > > + EdkiiSdMmcSwitchClockFreqPost,
> > > } EDKII_SD_MMC_PHASE_TYPE;
> > >
> > > /**
> > > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > > index 05bd4a0..7e75283 100755
> > > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c
> > > @@ -796,6 +796,27 @@ EmmcSwitchToHighSpeed (
> > >
> > > HsTiming = 1;
> > > Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming,
> > > ClockFreq);
> > > + if (EFI_ERROR (Status)) {
> > > + return Status;
> > > + }
> > > +
> > > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> > > + Status = mOverride->NotifyPhase (
> > > + Private->ControllerHandle,
> > > + Slot,
> > > + EdkiiSdMmcSwitchClockFreqPost,
> > > + &Timing
> > > + );
> > > + if (EFI_ERROR (Status)) {
> > > + DEBUG ((
> > > + DEBUG_ERROR,
> > > + "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
> > > + __FUNCTION__,
> > > + Status
> > > + ));
> > > + return Status;
> > > + }
> > > + }
> > >
> > > return Status;
> > > }
> > > @@ -905,6 +926,24 @@ EmmcSwitchToHS200 (
> > > return Status;
> > > }
> > >
> > > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> > > + Status = mOverride->NotifyPhase (
> > > + Private->ControllerHandle,
> > > + Slot,
> > > + EdkiiSdMmcSwitchClockFreqPost,
> > > + &Timing
> > > + );
> > > + if (EFI_ERROR (Status)) {
> > > + DEBUG ((
> > > + DEBUG_ERROR,
> > > + "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
> > > + __FUNCTION__,
> > > + Status
> > > + ));
> > > + return Status;
> > > + }
> > > + }
> > > +
> > > Status = EmmcTuningClkForHs200 (PciIo, PassThru, Slot, BusWidth);
> > >
> > > return Status;
> > > @@ -989,6 +1028,27 @@ EmmcSwitchToHS400 (
> > >
> > > HsTiming = 3;
> > > Status = EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming,
> > > ClockFreq);
> > > + if (EFI_ERROR (Status)) {
> > > + return Status;
> > > + }
> > > +
> > > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> > > + Status = mOverride->NotifyPhase (
> > > + Private->ControllerHandle,
> > > + Slot,
> > > + EdkiiSdMmcSwitchClockFreqPost,
> > > + &Timing
> > > + );
> > > + if (EFI_ERROR (Status)) {
> > > + DEBUG ((
> > > + DEBUG_ERROR,
> > > + "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
> > > + __FUNCTION__,
> > > + Status
> > > + ));
> > > + return Status;
> > > + }
> > > + }
> > >
> > > return Status;
> > > }
> > > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > > index 5645a71..057a4e2 100644
> > > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c
> > > @@ -887,6 +887,24 @@ SdCardSetBusMode (
> > > return Status;
> > > }
> > >
> > > + if (mOverride != NULL && mOverride->NotifyPhase != NULL) {
> > > + Status = mOverride->NotifyPhase (
> > > + Private->ControllerHandle,
> > > + Slot,
> > > + EdkiiSdMmcSwitchClockFreqPost,
> > > + &Timing
> > > + );
> > > + if (EFI_ERROR (Status)) {
> > > + DEBUG ((
> > > + DEBUG_ERROR,
> > > + "%a: SD/MMC switch clock freq post notifier callback failed - %r\n",
> > > + __FUNCTION__,
> > > + Status
> > > + ));
> > > + return Status;
> > > + }
> > > + }
> > > +
> > > if ((AccessMode == 3) || ((AccessMode == 2) && (Capability-
> > > >TuningSDR50 != 0))) {
> > > Status = SdCardTuningClock (PciIo, PassThru, Slot);
> > > if (EFI_ERROR (Status)) {
> > > --
> > > 2.7.4
> > >
> > > _______________________________________________
> > > edk2-devel mailing list
> > > edk2-devel@lists.01.org
> > > https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 47+ messages in thread
end of thread, other threads:[~2018-11-03 3:19 UTC | newest]
Thread overview: 47+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-10-05 13:25 [PATCH v2 0/4] SdMmcOverride extension Marcin Wojtas
2018-10-05 13:25 ` [PATCH v2 1/4] MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in NotifyPhase Marcin Wojtas
2018-10-08 12:21 ` Ard Biesheuvel
2018-10-05 13:25 ` [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol Marcin Wojtas
2018-10-05 15:12 ` Philippe Mathieu-Daudé
2018-10-05 15:17 ` Marcin Wojtas
2018-10-08 12:41 ` Ard Biesheuvel
2018-10-08 12:59 ` Marcin Wojtas
2018-10-08 13:07 ` Ard Biesheuvel
2018-10-08 13:17 ` Marcin Wojtas
2018-10-08 13:27 ` Ard Biesheuvel
2018-10-08 13:37 ` Marcin Wojtas
2018-10-08 13:43 ` Ard Biesheuvel
2018-10-08 14:52 ` Marcin Wojtas
2018-10-08 15:10 ` Ard Biesheuvel
2018-10-09 11:22 ` Wu, Hao A
2018-10-09 11:32 ` Marcin Wojtas
2018-10-09 11:45 ` Ard Biesheuvel
2018-10-09 11:51 ` Marcin Wojtas
2018-10-11 15:43 ` Marcin Wojtas
2018-10-12 1:39 ` Wu, Hao A
2018-10-12 5:06 ` Marcin Wojtas
2018-10-12 15:55 ` Ard Biesheuvel
2018-10-12 16:04 ` Marcin Wojtas
2018-10-12 16:24 ` Ard Biesheuvel
2018-10-12 16:49 ` Marcin Wojtas
2018-11-01 7:04 ` Wu, Hao A
2018-11-02 8:21 ` Marcin Wojtas
2018-11-02 12:16 ` Marcin Wojtas
2018-11-03 2:57 ` Wu, Hao A
2018-10-05 13:25 ` [PATCH v2 3/4] MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to SdMmcOverride Marcin Wojtas
2018-10-08 12:44 ` Ard Biesheuvel
2018-11-01 7:06 ` Wu, Hao A
2018-11-02 9:39 ` Marcin Wojtas
2018-11-03 3:19 ` Wu, Hao A
2018-10-05 13:25 ` [PATCH v2 4/4] MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequency Marcin Wojtas
2018-10-08 12:49 ` Ard Biesheuvel
2018-11-01 7:11 ` Wu, Hao A
2018-11-02 9:52 ` Marcin Wojtas
2018-10-12 5:24 ` [PATCH v2 0/4] SdMmcOverride extension Wu, Hao A
2018-10-12 5:33 ` Marcin Wojtas
2018-10-12 12:48 ` Wu, Hao A
2018-10-12 12:50 ` Marcin Wojtas
2018-10-25 12:43 ` Marcin Wojtas
2018-10-26 7:22 ` Wu, Hao A
2018-11-01 7:11 ` Wu, Hao A
2018-11-02 10:09 ` Marcin Wojtas
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