From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::143; helo=mail-it1-x143.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it1-x143.google.com (mail-it1-x143.google.com [IPv6:2607:f8b0:4864:20::143]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9B49E21A07A92 for ; Tue, 9 Oct 2018 04:45:29 -0700 (PDT) Received: by mail-it1-x143.google.com with SMTP id c85-v6so2135512itd.1 for ; Tue, 09 Oct 2018 04:45:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=4xFkz4GYEU0Q/1aJ9gWNyneTQvun6Wphd3F+hAl6PgI=; b=QFyg8WSsqbLTrM+JEzfI5RsGLGudyJqNGWSv/omyLP5qHhZRgWNDX50wrXXHLvBV97 FsmV4MWPwQLHgg+kFLoT39cXr7jGdWiaQiCyJ0D7nIHhkyOXBwxxEdQaWxO/5w4i/FCn 4Ai6q/6oCtOkBtezCwXlhiAFAMfwzD5l+KXQQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=4xFkz4GYEU0Q/1aJ9gWNyneTQvun6Wphd3F+hAl6PgI=; b=h91/qltZlLdRfGoklGtMUugLQ/GcYB559hD584RiBpM8+hhZVSxqmya/OQPF8AnX+G vikrhNG6pYNPgosgscHUWZFM+Fgyi2V6VfU8X3Tgspw6GC4rBKPyqWZaCDJxO7F4hAvY yQnzr2xFdBVzLGYgnA+i7jUZl9+qvzBKNHQk/9zLRgCAsbhqrTBzIqtfxM3G1hYMcmRC 9OFoAkZvsDcSKmvldTNPguPBwxrzGbj9t6S5Uq5bYozkc1ACN6Ngeh6Csnfg2quiOorM GPa3TDx/q5yzK0FduwW4MWuOGRcgU45cb0RA4LDVX5Op4w3WAz5bD2q6xF8JhjicVzSp ap9A== X-Gm-Message-State: ABuFfojROrCiS9xWO/AiQKi0lYbhlaVK0SrRf5XHXeJ2fxzLizY+aJf+ jMqKKHsgytkdTsTt5xtZwgh8FO8AEb5UB9MjWFoHIzJ4q0M= X-Google-Smtp-Source: ACcGV61Z9kiYFzy0eZ4a6AXC7pGrk4R0RLvXrBr+NHXbxJGEH10gSd/D2BT6jMzQOJjaoIVe/VuXHnGb1TKlecoaEds= X-Received: by 2002:a24:4ac5:: with SMTP id k188-v6mr1563602itb.158.1539085528581; Tue, 09 Oct 2018 04:45:28 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a6b:5910:0:0:0:0:0 with HTTP; Tue, 9 Oct 2018 04:45:27 -0700 (PDT) In-Reply-To: References: <1538745911-22484-1-git-send-email-mw@semihalf.com> <1538745911-22484-3-git-send-email-mw@semihalf.com> From: Ard Biesheuvel Date: Tue, 9 Oct 2018 13:45:27 +0200 Message-ID: To: Marcin Wojtas Cc: "Wu, Hao A" , "Ni, Ruiyu" , "Tian, Feng" , Tomasz Michalec , Eric Dong , edk2-devel-01 , "Gao, Liming" , Nadav Haklai , "Kinney, Michael D" , "Zeng, Star" Subject: Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 09 Oct 2018 11:45:29 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On 9 October 2018 at 13:32, Marcin Wojtas wrote: > wt., 9 pa=C5=BA 2018 o 13:28 Wu, Hao A napisa=C5=82(= a): >> >> > -----Original Message----- >> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of= Ard >> > Biesheuvel >> > Sent: Monday, October 08, 2018 11:10 PM >> > To: Marcin Wojtas; Ni, Ruiyu; Wu, Hao A >> > Cc: Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-devel-01; Gao, Limin= g; >> > Nadav Haklai; Kinney, Michael D; Zeng, Star >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add >> > UhsSignaling to SdMmcOverride protocol >> > ... >> > >> > I suppose this is defined by the eMMC spec. >> > >> > Ruiyu, Hao, could you clarify? Are the host control 2 register values >> > for HS200/HS400 defined by the eMMC spec? >> >> Hi Ard and Marcin, >> >> As far as I know, the EMMC Electrical Standard Spec 5.1 (latest) does no= t >> mention on how to set the "UHS Mode Select" field of the Host Control 2 >> Register when switching to HS200/HS400. (Actually, the EMMC spec does no= t >> mention Host Control 2 Register at all) >> >> When it comes to setting the bus mode for EMMC devices, the current >> implementation of the SdMmcPciHcDxe driver does a mapping when setting t= he >> Host Control 2 Register: >> >> EMMC High Speed SDR - Freq: 0-52 MHz, Data Rate: Single >> matches >> SD SDR25 - Freq: 0-50 MHz, Data Rate: Single >> >> EMMC High Speed DDR - Freq: 0-52 MHz, Data Rate: Dual >> matches >> SD DDR50 - Freq: 0-50 MHz, Data Rate: Dual >> >> EMMC HS200 - Freq: 0-200 MHz, Data Rate: Single >> matches >> SD SDR104 - Freq: 0-208 MHz, Data Rate: Single >> >> EMMC HS400 - Freq: 0-200 MHz, Data Rate: Dual >> matches >> SD None >> >> And there is no obvious counterpart for the EMMC HS400 mode in the SD >> spec. The driver currently sets the "UHS Mode Select" field to a reserve= d >> value 0x5. >> > > Thank you Hao, above is on par with what the default UhsSignaling > routine does in this patch. IMO especially in case the EMMC standard > is not unequivocal regarding UHS_MODE_SEL, I'd encourage to accept > some way of updating HostControl2 register, depending on the > implementation. What is your opinion Ard? > I would like to know where the current values in SdMmcPciHcDxe come from if they are not defined in any spec. How do we know which ones are the correct ones?