From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=yHGQLMpe; spf=pass (domain: linaro.org, ip: 209.85.166.65, mailfrom: ard.biesheuvel@linaro.org) Received: from mail-io1-f65.google.com (mail-io1-f65.google.com [209.85.166.65]) by groups.io with SMTP; Thu, 16 May 2019 07:25:27 -0700 Received: by mail-io1-f65.google.com with SMTP id u2so2740213ioc.4 for ; Thu, 16 May 2019 07:25:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=LIImJ2vvbkch3PrFsAwh2TUXkn4OyVL1Sb30RHgE9BA=; b=yHGQLMpeKJQQaoQG65qv1658nN88YT1O6B6m14B6ooJIwgvJ4rvXklTc2T+jKcxJ5g PB0thFCPXcmad/5CFe05jGlSa+lb7gt5qOZK37e6RjfUqS3EERHHxjaGZyByH+3kx/Ei DawcPzfFPUclDbTlIAB4kB8YzlYeOy+GdvVTJoA7S3Tjrly49DCCPN3HTAusGxaWZqYf 6QAiJntI1vqrh3v53pGkmESIEHz6IJmAxEr7gAYtZpIRWZ+gP4iexlUEkmSAmL8NGUZZ i9P9OWLmbnmdtEKa2dZdX2H1d3XT8e0tfywDaeZYGmhYNanQH48yi9puGcK+1qEKc21c LaGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=LIImJ2vvbkch3PrFsAwh2TUXkn4OyVL1Sb30RHgE9BA=; b=JDrwDkr1VqmOecOiQf3J1ChXTATApE8AqFRUyySvauna9B6dkh8TWsSvampCiEHnn8 BRkp2WcgcxDEIZSlgwFH1Io40qu1wSEN/y4rnbue1q65go/vWuRZI1qmGoPA6hDDIR7O 5idbOCcTbiSHwRBK+MhljUMqFLmbAeRu/9b5/FEaM2lsoADvab6JLX7qoRtSGteMCzAD svK84Htli4rjQ5FczthuKDAPom9rompSDcNOL+YUzqaiwVg2Wf1oi4e3C1FhL4IiedXc 6FlYIkXj+GofP3kMnWo8XhdGVM1U4koguWJmgWZS/hbCFJYScXiyWViIIzr0cMLsvZXL lyjA== X-Gm-Message-State: APjAAAWeLeoPre27iw/r1e4ny7UbDcUxZFgiV2/foQoNlb1yD0Hy8OhW ddp97o5zk3fTOJk5ll+Z6uMHNqKEg9aRVStLPIgU1g== X-Google-Smtp-Source: APXvYqwIuKAzxnjJRNfzC1CdSWp0bdz+N38DidwdiXwvipUSWDj51FNS74qLeRE+ibZFOd8076bll/SvrTn0gjjCEV8= X-Received: by 2002:a6b:c842:: with SMTP id y63mr13127937iof.60.1558016726337; Thu, 16 May 2019 07:25:26 -0700 (PDT) MIME-Version: 1.0 References: <1557395622-32425-1-git-send-email-mw@semihalf.com> <1557395622-32425-9-git-send-email-mw@semihalf.com> In-Reply-To: From: "Ard Biesheuvel" Date: Thu, 16 May 2019 16:25:14 +0200 Message-ID: Subject: Re: [edk2-platforms: PATCH 08/14] Marvell/Armada7k8k: Enable PCIE support To: Marcin Wojtas Cc: edk2-devel-groups-io , Leif Lindholm , =?UTF-8?B?SmFuIETEhWJyb8Wb?= , Grzegorz Jaszczyk , Kostya Porotchkin , Jici Gao , Rebecca Cran , Mark Kettenis Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Thu, 16 May 2019 at 16:22, Marcin Wojtas wrote: > > Hi Ard, > > czw., 16 maj 2019 o 16:16 Ard Biesheuvel napi= sa=C5=82(a): > > > > On Thu, 9 May 2019 at 11:54, Marcin Wojtas wrote: > > > > > > Wire up the platform libraries to the generic drivers so that we can = use > > > PCI devices and UEFI, and leave the controller initialized so that th= e > > > OS can boot it using a generic driver of its own. > > > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > > Signed-off-by: Marcin Wojtas > > > --- > > > Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 17 +++++++++++++++-- > > > Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 5 +++++ > > > 2 files changed, 20 insertions(+), 2 deletions(-) > > > > > > diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/= Marvell/Armada7k8k/Armada7k8k.dsc.inc > > > index 545b369..f78a76b 100644 > > > --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc > > > +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc > > > @@ -70,8 +70,10 @@ > > > IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf > > > UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDec= ompressLib.inf > > > CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf > > > - PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf > > > - PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf > > > + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.in= f > > > + PciHostBridgeLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciH= ostBridgeLib/PciHostBridgeLib.inf > > > + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLi= bPci.inf > > > + PciExpressLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciExpr= essLib/PciExpressLib.inf > > > > > > # Basic UEFI services libraries > > > UefiLib|MdePkg/Library/UefiLib/UefiLib.inf > > > @@ -407,6 +409,12 @@ > > > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x0= 0010000 > > > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x000= 10000 > > > > > > + # PCIE > > > + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 > > > + > > > + # SoC Configuration Space > > > + gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xE0000000 > > > + > > > !if $(CAPSULE_ENABLE) > > > [PcdsDynamicExDefault.common.DEFAULT] > > > gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDesc= riptor|{0x0}|VOID*|0x100 > > > @@ -520,6 +528,11 @@ > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf > > > Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonDxe.inf > > > > > > + # PCI > > > + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf > > > > This driver requires gArmTokenSpaceGuid.PcdPciIoTranslation to be set > > to a sane value. Are you sure this is the case for your platforms? > > > > Do you mean the IO space for the controller? If yes, I'll set the PCD > to according value I use in board description. I don't have an old > enough endpoint that requires IO space to test :) > Yes, it is basically the MMIO address of the I/O space. Leif kindly gave me a PCIe serial port controller that I use especially for testing these things at plugfests.