From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::d42; helo=mail-io1-xd42.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io1-xd42.google.com (mail-io1-xd42.google.com [IPv6:2607:f8b0:4864:20::d42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D2A2C21168233 for ; Fri, 12 Oct 2018 03:03:25 -0700 (PDT) Received: by mail-io1-xd42.google.com with SMTP id q4-v6so8815218iob.8 for ; Fri, 12 Oct 2018 03:03:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=EbyY5V4Nv/GOKJ6xlENsNWLlEohRGRawdeDEDPrmI3s=; b=c6BMak2gJwiUHyKp9W23XF7PP0EY6wghQIYVyE+u+hF5L3MOwg7nPHs21EOSvp6Xh6 /CWr4MZ5f4fnSwmwMlVPjpRlEgetjxSw6Yy5ajdfAhJf6qNjj1b63c1Xjy2EkHzfgkmZ Z+1CxJSvkGkIgMi/gectTb7PSau6sPG9mtbi8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=EbyY5V4Nv/GOKJ6xlENsNWLlEohRGRawdeDEDPrmI3s=; b=jpWYBt+d/ERh6bbmAWQpPqOAoXcrpbWMQUA53K1hpLYtkVJMrzdm+46w04onXro0BM zOLs/oDkM7PnUI19k+K8vChsuvxExkpeHqLMpCPu8U64w1diUbCeECs6v2uOxIaKh6aU ShPrIHBezea8iTXancgoJ3V1HM+m2jFGSU/naEz3U1j2l21fQbhHLQi1IVW4uF/473Ym YQjYa5pMF1qVwK/aAPgWLiAXUovDrH60Fj0kHZZiUsrLtzGHaX+Z/gQL2fpmKPYvycNf eJXYKdmVizeJN6HUCFzOt5q/LYijkgChwgWMpwOAEGQjwOELG+U/QEPuRpNI60Uxl4B8 QJow== X-Gm-Message-State: ABuFfoj4E6ZNN7mwIcv/ZWxkVUFksJDyWQfjmlmzLgqZIFINTXNTm4zY uXDaqkIPJ3+dbUHDtxciZPlnoYKLYZ6DUE53vQNLLw== X-Google-Smtp-Source: ACcGV62w8YqRhVuj8b5tWUwKCbHzIX297BJJOtSj5r4AhYDMk1NundYkSV2u5KCUy+RZXi/apSeU1JdMU9E1ru4BsD8= X-Received: by 2002:a6b:5d12:: with SMTP id r18-v6mr3529298iob.170.1539338604828; Fri, 12 Oct 2018 03:03:24 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a6b:5910:0:0:0:0:0 with HTTP; Fri, 12 Oct 2018 03:03:24 -0700 (PDT) In-Reply-To: <20180531091622.3u7dd2kjnu6fhb5w@bivouac.eciton.net> References: <20180530181929.5066-1-ard.biesheuvel@linaro.org> <20180530181929.5066-4-ard.biesheuvel@linaro.org> <20180531091622.3u7dd2kjnu6fhb5w@bivouac.eciton.net> From: Ard Biesheuvel Date: Fri, 12 Oct 2018 12:03:24 +0200 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" , Masahisa Kojima Subject: Re: [PATCH edk2-platforms 3/3] Silicon/SynQuacer/AcpiTables: add NETSEC/eMMC SMMU to the IORT X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Oct 2018 10:03:26 -0000 Content-Type: text/plain; charset="UTF-8" On 31 May 2018 at 11:16, Leif Lindholm wrote: > On Wed, May 30, 2018 at 08:19:29PM +0200, Ard Biesheuvel wrote: >> Add a description of the SMMU that sits in front of the NETSEC and >> eMMC controllers to the IORT table so that ACPI based OSes can >> utilize it. >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ard Biesheuvel > > Looks reasonable to me. > Reviewed-by: Leif Lindholm > As it turns out, we don't actually need a SCP firmware update for this, and the other remaining issue (only 40 address bits wired up while the IP can driver 48) was fixed both in the Linux driver (and backported) and in the DMA layer, so let's enable this piece of functionality now. Note that DT boot will not enable the SMMU. Pushed as 8c3914c90ecd..a82113852ae1 >> --- >> Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc | 109 +++++++++++++++++++- >> 1 file changed, 107 insertions(+), 2 deletions(-) >> >> diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc b/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc >> index 92c485f8006f..3f2aaa3d8858 100644 >> --- a/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc >> +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Iort.aslc >> @@ -13,6 +13,7 @@ >> **/ >> >> #include >> +#include >> >> #include "AcpiTables.h" >> >> @@ -29,10 +30,23 @@ typedef struct { >> EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping; >> } SYNQUACER_RC_NODE; >> >> +typedef struct { >> + EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE Node; >> + EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT Context[8]; >> +} SYNQUACER_SMMU_NODE; >> + >> +typedef struct { >> + EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE Node; >> + CONST CHAR8 Name[11]; >> + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMapping; >> +} SYNQUACER_NC_NODE; >> + >> typedef struct { >> EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort; >> SYNQUACER_ITS_NODE ItsNode; >> SYNQUACER_RC_NODE RcNode[2]; >> + SYNQUACER_SMMU_NODE SmmuNode; >> + SYNQUACER_NC_NODE NamedCompNode[2]; >> } SYNQUACER_IO_REMAPPING_STRUCTURE; >> >> #define __SYNQUACER_ID_MAPPING(In, Num, Out, Ref, Flags) \ >> @@ -49,7 +63,7 @@ STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = { >> __ACPI_HEADER(EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE, >> SYNQUACER_IO_REMAPPING_STRUCTURE, >> EFI_ACPI_IO_REMAPPING_TABLE_REVISION), >> - 3, // NumNodes >> + 6, // NumNodes >> sizeof(EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset >> 0 // Reserved >> }, { >> @@ -94,7 +108,7 @@ STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = { >> // >> __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode, >> EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE), >> - }, { >> + }, { >> // PciRcNode >> { >> { >> @@ -121,6 +135,97 @@ STATIC SYNQUACER_IO_REMAPPING_STRUCTURE Iort = { >> __SYNQUACER_ID_MAPPING(0x0, 0x0, 0x0, ItsNode, >> EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE), >> } >> + }, { >> + // NETSEC/eMMC SMMU node >> + { >> + { >> + EFI_ACPI_IORT_TYPE_SMMUv1v2, >> + sizeof(SYNQUACER_SMMU_NODE), >> + 0x0, >> + 0x0, >> + 0x0, >> + 0x0, >> + }, >> + SYNQUACER_SCB_SMMU_BASE, >> + SYNQUACER_SCB_SMMU_SIZE, >> + EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500, >> + EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK, >> + FIELD_OFFSET(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE, >> + SMMU_NSgIrpt), >> + 0x8, >> + sizeof(EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE), >> + 0x0, >> + 0x0, >> + 228, >> + EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, >> + 0x0, >> + 0x0, >> + }, { >> + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, >> + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, >> + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, >> + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, >> + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, >> + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, >> + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, >> + { 228, EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL, }, >> + }, >> + }, { >> + { >> + // NETSEC named component node >> + { >> + { >> + EFI_ACPI_IORT_TYPE_NAMED_COMP, >> + sizeof(SYNQUACER_NC_NODE), >> + 0x0, >> + 0x0, >> + 0x1, >> + FIELD_OFFSET(SYNQUACER_NC_NODE, RcIdMapping), >> + }, >> + 0x0, >> + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, >> + 0x0, >> + 0x0, >> + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | >> + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, >> + 40, >> + }, { >> + "\\_SB_.NET0" >> + }, { >> + 0x0, >> + 0x0, >> + 0x0, >> + FIELD_OFFSET(SYNQUACER_IO_REMAPPING_STRUCTURE, SmmuNode), >> + EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE >> + } >> + }, { >> + // eMMC named component node >> + { >> + { >> + EFI_ACPI_IORT_TYPE_NAMED_COMP, >> + sizeof(SYNQUACER_NC_NODE), >> + 0x0, >> + 0x0, >> + 0x1, >> + FIELD_OFFSET(SYNQUACER_NC_NODE, RcIdMapping), >> + }, >> + 0x0, >> + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, >> + 0x0, >> + 0x0, >> + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM | >> + EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS, >> + 40, >> + }, { >> + "\\_SB_.MMC0" >> + }, { >> + 0x0, >> + 0x0, >> + 0x0, >> + FIELD_OFFSET(SYNQUACER_IO_REMAPPING_STRUCTURE, SmmuNode), >> + EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE >> + } >> + } >> } >> }; >> >> -- >> 2.17.0 >>