From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-io0-x231.google.com (mail-io0-x231.google.com [IPv6:2607:f8b0:4001:c06::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2C5571A1EBD for ; Thu, 22 Sep 2016 08:22:41 -0700 (PDT) Received: by mail-io0-x231.google.com with SMTP id r145so89226664ior.0 for ; Thu, 22 Sep 2016 08:22:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=i1FkXCfI77r588stjVC1S/WTPXNDZhZW/7YY19q8H1Y=; b=DiWxkvDiTd86cVmoUgVjdcH/WRmShWgu4hWdy08aTPikd+C51RSpWKZcjHHo2SZxHu oziLGyCBuwGrPybnG/AcqjfrZoPJovv9HiHlAOgCfamENIvo0I628yauyOqS9h3UPAGN 9a7Hf5OZvf4GjPTboQn0l9PY7K9b/cd7tSlPA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=i1FkXCfI77r588stjVC1S/WTPXNDZhZW/7YY19q8H1Y=; b=O3rIHlzuW2YGSewQlz8mCIXIGrkoUOBfZc7bCVFan7R8xZeSaLaXeLrQrQkGmI/qcn +n/YvcfYWVU/HwW4Y3MZS+8w3P4EjF+yZYPRx4ODLwdwgPESxs0dsdBV2e10A15hdrO5 XoR50b6XRCE9Bz882YcmbZ57iD8zLVGDQv1frNnbGxtnNDM/sAbgg78qIb80oUxOAop4 2qErO1vwESl9M8ZrJkjNniifFPBjbomnMTRWop3kXfd9iP1/HikgFbH8RJz98IHjJK6s CwYrqrXxV/s7/DwCXDoUwbRx7Nx3XQ9xlOK1YrdOBPPmGM+6CgVsoYVhCj+vmp/SVzg3 4pog== X-Gm-Message-State: AE9vXwOU2q0ukOFbdKtZgSMeneOFe1KK1Njn9EFUhQ/B7LrVKGZBFhI2ItyYq8b+nZbjsfYAz9wo5flKPMtD1Oks X-Received: by 10.107.16.29 with SMTP id y29mr3312744ioi.143.1474557760407; Thu, 22 Sep 2016 08:22:40 -0700 (PDT) MIME-Version: 1.0 Received: by 10.36.204.195 with HTTP; Thu, 22 Sep 2016 08:22:39 -0700 (PDT) In-Reply-To: References: From: Ard Biesheuvel Date: Thu, 22 Sep 2016 16:22:39 +0100 Message-ID: To: valerij zaporogeci Cc: edk2-devel Subject: Re: flat mapping vs identity mapping on ARM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 22 Sep 2016 15:22:41 -0000 Content-Type: text/plain; charset=UTF-8 On 22 September 2016 at 16:19, valerij zaporogeci wrote: > 2016-09-22 18:03 GMT+03:00, Ard Biesheuvel : >> On 22 September 2016 at 15:30, valerij zaporogeci >> wrote: >>> In the ARM architecture, there is such a thing - "flat mapping", where >>> MMU stage 1 is disabled and the mapping done is 1:1 and attributes set >>> to the predefined values. >> >> What do you mean by 'attributes set to the predefined values' ? >> > > I meant what is written in the section B3.2.1, short quote: > "For all other accesses, when a stage 1 MMU is disabled, the assigned > attributes depend on whether > the access is a data access or an instruction access, as follows: > Data access > The stage 1 translation assigns the Strongly-Ordered memory type" > > ... and then, more lengthy description for instruction access. > > Yes, so what this means is that all data accesses are strongly ordered, and instruction fetches are cacheable. So while you can enable both the data and the instruction cache with the MMU off, only the instruction cache is actually functional, since all data accesses or non-cacheable