From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::142; helo=mail-it1-x142.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it1-x142.google.com (mail-it1-x142.google.com [IPv6:2607:f8b0:4864:20::142]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7BF3B208AE36C for ; Fri, 1 Mar 2019 03:39:10 -0800 (PST) Received: by mail-it1-x142.google.com with SMTP id d125so10192174ith.1 for ; Fri, 01 Mar 2019 03:39:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=eBAVtdnZHiuHtvxG0YDSuhGdx1f/HLtiWdlbVLAXdxE=; b=kFVpSPsZ55XETvITF55XhEFCgADkAkrzEL5aO9+Yz2/W/0dPYHAHGLmwgRXZUvy2qk TOF5CvQKy2DjrCrvEoXqqf67Qpzv79Jdm2d/aqDm/NEaYcnHV2gfe9QE7hEMNMcGbmE+ Zy2uIC3rZrBixU/QS1yPE9U+mU/O35GjVtNp5IJor+MFGX44d8Xv7Qr42tpLCSOiZ95M 3oV7NJjVFhPRQ/HTVpOj5ykfij/1Tyi4tJfr3iRe4xcy4LXogh6txfO6pR2w721PQo37 DCxdFvbHYczWEKTSVL9qB1ZFdZc3yg8iqw/SS2hZBfK6hnNqCsfCG1h0XIVKhmlHlD53 gSFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=eBAVtdnZHiuHtvxG0YDSuhGdx1f/HLtiWdlbVLAXdxE=; b=s4yad4jxeRSuj1RpM9vizfxTF9gS6redVn4vxqOJcVjVVbaZqwbsJdnUgD1aHR9zq1 EyMKKPIW3y4me10b6uERJcezsxrgB+qH5jEOTnJJ89AqyzlYa3aIW+uRc9Y7nLIypAXc oBinaKyyWgh8qTX40Jut90A4G+FdX4xxGLXjfIT+zdeziMsLESNyp6CN3uWEGEQkrThU izC85l+DCpxUdaQBGB4Vai2kAlDl4soDgBBvrizMeZDIYjuZ20l7lk6AK99cgj3LXqIJ awEYQnFtj7uDPktKE8dWO0NTYzi5sDUZqeissgwNawcpYuSBgSMlMtgzD7aC57QbB2Bc 3NUw== X-Gm-Message-State: APjAAAUqrMvd+yEw7bfoMvuVvtyi8q8NZPvA1n010URjSJ8E4KM3de0W 7h7IyPNRjy6ffPD1IeTPrz6tVufwrlK1RRlQ9D3kpw== X-Google-Smtp-Source: APXvYqyZnmSRFiDGKxAo7UWmgVjFEIG9XPVT2DQiIsXQeVO8NItvp2zZGIbVtlpfSVg66pBXDVDmxGO9oKjpi4lYDxw= X-Received: by 2002:a05:6638:2a1:: with SMTP id d1mr2319854jaq.2.1551440350050; Fri, 01 Mar 2019 03:39:10 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Ard Biesheuvel Date: Fri, 1 Mar 2019 12:38:59 +0100 Message-ID: To: "Cohen, Eugene" Cc: Ashish Singhal , "Wu, Hao A" , "edk2-devel@lists.01.org" , =?UTF-8?B?S2ltLCBTYW5nd29vICjquYDsg4HsmrAgU1cxTGFiLik=?= Subject: Re: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC v3 64-bit systems X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Mar 2019 11:39:11 -0000 Content-Type: text/plain; charset="UTF-8" On Fri, 1 Mar 2019 at 11:54, Cohen, Eugene wrote: > > Ard, > > > So before these changes, we were in the exact same situation, but since PC > > platforms never enable DMA above 4 GB in the first place, nobody ever > > noticed until we started running this code on arm64 platforms that have no > > 32-bit addressable DRAM to begin with. > > Interesting - I did not realize that there were designs that were crazy enough to have no addressable DRAM below 4G. > You must be new here :-) But seriously, it does make sense for an implementation to, say, put all peripherals, PCIe resource windows etc in the bottom half and all DRAM in the top half of a 40-bit address space, which is how the AMD Seattle SoC ended with its system memory at address 0x80_0000_0000. Note that on this platform, we can still use 32-bit DMA if we want to with the help of the SMMUs, but we haven't wired those up in UEFI (and the generic host bridge driver did not have the IOMMU hooks at the time) > > The obvious conclusion is that the driver should not set the > > EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute if the device does > > not support it, or, which seems to be our case, if the driver does not > > implement the 64-bit DMA mode that the driver does support. However, > > since there are platforms for which bounce buffering is not an option (since > > there is no 32-bit addressable memory to bounce to), this is not just a > > performance optimization, and so it would be useful to fix the code so it can > > drive all 64-bit DMA capable hardware. > > Okay, that's a great reason - let's get V3 64b ADMA2 in! > > Any objection to committing the original patch in the short term? > not at all Acked-by: Ard Biesheuvel