From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::d43; helo=mail-io1-xd43.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io1-xd43.google.com (mail-io1-xd43.google.com [IPv6:2607:f8b0:4864:20::d43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D6ED121959CB2 for ; Fri, 12 Oct 2018 08:55:16 -0700 (PDT) Received: by mail-io1-xd43.google.com with SMTP id l25-v6so9566870ioj.0 for ; Fri, 12 Oct 2018 08:55:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=rBLZVCG4IwsW+H6hCI7ADZ1QX51cM+NkjHl6Z0ijMho=; b=g/kYlJ0iM/ms2B3gZLXvQ6+fNP+GGOM8hYwpWv7ApjiFeO10WrVUfGUTrjm0poLont rn7P9LXCmVXxBepCNr0ryhCMfhp/OqavbB/D7/RaonRoD0+YhBOwga5lH5NCQ3sksDNR jxX71iyNrXoWb2uqueWXa9daOh3uLoCcwv4IA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=rBLZVCG4IwsW+H6hCI7ADZ1QX51cM+NkjHl6Z0ijMho=; b=mmBCPCYFDjyEV/YkI5shFwGwxT7WNS2uup2bjB0QRkaTFk+FaYXD9pxc5nqcsZQpSg m7EYvAY23q7j2mSwRynmBAK37UcI9rqoNdVT1AcmviD7xea8BwtmyT+mjwip6ZdsmJTI phM6e2A4t/L5EQkyyb2giKDfRzX+CLuh1Z0m72N7bnZKw/cKqm2aIllQapBuNzCKa1Lr sND5tey6daKbg7qzz8zlw5YDvAx3TbhpRjaQCRxU/RUU8SONYlMNHEwps7RWo7Hxvhc7 P8Ej5F87+gS95lIc2we1HDcbUKhNFdKE3pJnWSKKwWqfh1Xi0SB41/IFAN2hVblnQGJm gFKg== X-Gm-Message-State: ABuFfohekEyIY8xQeMWiMp/+uJqv/Kn3bJZMYwYyJteXFgbWUVLXGlFc mK4qcPKtmUb92zM3kBJeoIBCYeNzfxw6LDWuDXeF5Q== X-Google-Smtp-Source: ACcGV63/iMhZN0Kf8uHw1Zv5RpqW7VZb/Vxgz6zG0KMIecDbTdJF5Yd2S2acj2vRoLR6tJ0DsRlTuzu8Zpkcc3Hl4WM= X-Received: by 2002:a6b:3787:: with SMTP id e129-v6mr4792691ioa.60.1539359715629; Fri, 12 Oct 2018 08:55:15 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a6b:5910:0:0:0:0:0 with HTTP; Fri, 12 Oct 2018 08:55:14 -0700 (PDT) In-Reply-To: References: <1538745911-22484-1-git-send-email-mw@semihalf.com> <1538745911-22484-3-git-send-email-mw@semihalf.com> From: Ard Biesheuvel Date: Fri, 12 Oct 2018 17:55:14 +0200 Message-ID: To: Marcin Wojtas Cc: "Wu, Hao A" , "Ni, Ruiyu" , "Tian, Feng" , Tomasz Michalec , Eric Dong , edk2-devel-01 , "Gao, Liming" , Nadav Haklai , "Kinney, Michael D" , "Zeng, Star" Subject: Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Oct 2018 15:55:17 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On 12 October 2018 at 07:06, Marcin Wojtas wrote: > pt., 12 pa=C5=BA 2018 o 03:41 Wu, Hao A napisa=C5=82= (a): >> >> > -----Original Message----- >> > From: Marcin Wojtas [mailto:mw@semihalf.com] >> > Sent: Thursday, October 11, 2018 11:43 PM >> > To: Wu, Hao A >> > Cc: Ni, Ruiyu; Ard Biesheuvel; Tian, Feng; Tomasz Michalec; Dong, Eric= ; edk2- >> > devel-01; Gao, Liming; nadavh@marvell.com; Kinney, Michael D; Zeng, St= ar >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add >> > UhsSignaling to SdMmcOverride protocol >> > >> > wt., 9 pa=C5=BA 2018 o 13:51 Marcin Wojtas napisa=C5= =82(a): >> > > >> > > wt., 9 pa=C5=BA 2018 o 13:45 Ard Biesheuvel >> > napisa=C5=82(a): >> > > > >> > > > On 9 October 2018 at 13:32, Marcin Wojtas wrote: >> > > > > wt., 9 pa=C5=BA 2018 o 13:28 Wu, Hao A napi= sa=C5=82(a): >> > > > >> >> > > > >> > -----Original Message----- >> > > > >> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On >> > Behalf Of Ard >> > > > >> > Biesheuvel >> > > > >> > Sent: Monday, October 08, 2018 11:10 PM >> > > > >> > To: Marcin Wojtas; Ni, Ruiyu; Wu, Hao A >> > > > >> > Cc: Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-devel-01; G= ao, >> > Liming; >> > > > >> > Nadav Haklai; Kinney, Michael D; Zeng, Star >> > > > >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe= : >> > Add >> > > > >> > UhsSignaling to SdMmcOverride protocol >> > > > >> > >> > > > ... >> > > > >> > >> > > > >> > I suppose this is defined by the eMMC spec. >> > > > >> > >> > > > >> > Ruiyu, Hao, could you clarify? Are the host control 2 registe= r values >> > > > >> > for HS200/HS400 defined by the eMMC spec? >> > > > >> >> > > > >> Hi Ard and Marcin, >> > > > >> >> > > > >> As far as I know, the EMMC Electrical Standard Spec 5.1 (latest= ) does >> > not >> > > > >> mention on how to set the "UHS Mode Select" field of the Host >> > Control 2 >> > > > >> Register when switching to HS200/HS400. (Actually, the EMMC spe= c >> > does not >> > > > >> mention Host Control 2 Register at all) >> > > > >> >> > > > >> When it comes to setting the bus mode for EMMC devices, the cur= rent >> > > > >> implementation of the SdMmcPciHcDxe driver does a mapping when >> > setting the >> > > > >> Host Control 2 Register: >> > > > >> >> > > > >> EMMC High Speed SDR - Freq: 0-52 MHz, Data Rate: Single >> > > > >> matches >> > > > >> SD SDR25 - Freq: 0-50 MHz, Data Rate: Single >> > > > >> >> > > > >> EMMC High Speed DDR - Freq: 0-52 MHz, Data Rate: Dual >> > > > >> matches >> > > > >> SD DDR50 - Freq: 0-50 MHz, Data Rate: Dual >> > > > >> >> > > > >> EMMC HS200 - Freq: 0-200 MHz, Data Rate: Single >> > > > >> matches >> > > > >> SD SDR104 - Freq: 0-208 MHz, Data Rate: Single >> > > > >> >> > > > >> EMMC HS400 - Freq: 0-200 MHz, Data Rate: Dual >> > > > >> matches >> > > > >> SD None >> > > > >> >> > > > >> And there is no obvious counterpart for the EMMC HS400 mode in = the >> > SD >> > > > >> spec. The driver currently sets the "UHS Mode Select" field to = a >> > reserved >> > > > >> value 0x5. >> > > > >> >> > > > > >> > > > > Thank you Hao, above is on par with what the default UhsSignalin= g >> > > > > routine does in this patch. IMO especially in case the EMMC stan= dard >> > > > > is not unequivocal regarding UHS_MODE_SEL, I'd encourage to acce= pt >> > > > > some way of updating HostControl2 register, depending on the >> > > > > implementation. What is your opinion Ard? >> > > > > >> > > > >> > > > I would like to know where the current values in SdMmcPciHcDxe com= e >> > > > from if they are not defined in any spec. >> > > > >> > > > How do we know which ones are the correct ones? >> > > >> > > Hao, can you justify used values? >> > > >> > >> > Hi Hao, >> > >> > Can you please take a look at the UHS_MODE_SEL values source for eMMC? >> >> Hi Marcin, >> >> Sorry for the delayed response. >> >> For the current implementation of the SdMmcPciHcDxe driver, the selectin= g >> of "UHS Mode Select" field value of the Host Control 2 Register is based >> on a Max Clock Frequency & Data Rate (Single or Dual) matching >> relationship between the: >> >> A. Table 3-6 of the SD Specifications Part 1 Physical Layer Simplified >> Specification Version 4.10 >> >> and >> >> B. Table 4 of the EMMC Electrical Standard Spec 5.1 >> >> The matching details was included in my previous reply. The only missing >> part is there seems no matching for the EMMC HS400 mode in the SD >> specifications. For this case, we are currently using the same approach >> with the Linux implementation, that is to set the "UHS Mode Select" to a >> value of 0x5 (not standard). >> > > Hao, > > Thanks a lot for the clarification. > > Ard, > > Knowing the numbers details, what is your view of the UhsSignaling handli= ng? > I think it makes sense to be able to override the SD->MMC mapping for HC2 attributes. But it seems to me that this mapping is rather ad-hoc and so it should apply to all configuration that is inferred: UhsSignalling does not quite cover it. So I think the approach is correct, but we need a better name.