From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-it0-x22e.google.com (mail-it0-x22e.google.com [IPv6:2607:f8b0:4001:c0b::22e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5B46F81C4D for ; Wed, 2 Nov 2016 06:40:16 -0700 (PDT) Received: by mail-it0-x22e.google.com with SMTP id e187so17809394itc.0 for ; Wed, 02 Nov 2016 06:40:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=lVEz7/9oepP5/7ZgOpRRzg6nOeIxTZ4DH0SvwTWGeSA=; b=HLEPGKC/oIRNwUAI221J7ulierwXYpnK2mT/d1dId00y08bebZWkNkHfUv+2TxsbBW JZy3z8TkY4eKSSU3/lUdxW5Rxpa8DbsHUF3GXyCDelhFeAQZvJpRvVhKSUp6q7tncxWZ b6sd0GWk4Pe4J0ARo+3bil2MNBy4ODOsky/JI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=lVEz7/9oepP5/7ZgOpRRzg6nOeIxTZ4DH0SvwTWGeSA=; b=h7glpDDQD8oToSQ103tdS/LsuuYvbSeC831YNr9TR9QMWOmFx4Cle9JmgXVnxnv6nO HmTD0JLMaVmWpK3M/BFj56COTOdqa3jtsjdVhBppxmNta3h6+mJtqGSr1sJk/QwheBXl fIdWwBiAlhdw/jsk7SRWf7qeILc3jv3R39m9gYb6PKi0a8BxPLGXkvCXIvoV/EcEH8he X1bTf4072Qyww2wjlwcgyy8znSXHsC0J9vKZz5H0rOXZnJHZ2n00PiDUOHmJ8zmKAyht /esbEfOp+cozp4/kFQCdBpXiu8QmQkVNLychvohZJCVg6bfhk9JVxxgtAvTV/Ew15MOn 1z3g== X-Gm-Message-State: ABUngvdozlIaTfWc7izW97/bh2e6Wie4Bx/9gpm+Rj/CZSiuHuByVtBOcrbsigrNjRaI3Nv5QsgnKPYkXMR3EOKw X-Received: by 10.107.28.148 with SMTP id c142mr4133764ioc.45.1478094017424; Wed, 02 Nov 2016 06:40:17 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.59.147 with HTTP; Wed, 2 Nov 2016 06:40:17 -0700 (PDT) In-Reply-To: <20161101223227.GP1161@bivouac.eciton.net> References: <1477937590-10361-1-git-send-email-ard.biesheuvel@linaro.org> <1477937590-10361-5-git-send-email-ard.biesheuvel@linaro.org> <20161101223227.GP1161@bivouac.eciton.net> From: Ard Biesheuvel Date: Wed, 2 Nov 2016 13:40:17 +0000 Message-ID: To: Leif Lindholm Cc: edk2-devel-01 Subject: Re: [PATCH 4/5] ArmPkg/CpuDxe: set DmaBufferAlignment according to CWG X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Nov 2016 13:40:16 -0000 Content-Type: text/plain; charset=UTF-8 On 1 November 2016 at 22:32, Leif Lindholm wrote: > On Mon, Oct 31, 2016 at 06:13:09PM +0000, Ard Biesheuvel wrote: >> The DmaBufferAlignment currently defaults to 4, which is dangerously >> small and may result in lost data on platform that perform non-coherent >> DMA. So instead, take the CWG value from the cache info registers. >> >> Contributed-under: TianoCore Contribution Agreement 1.0 >> Signed-off-by: Ard Biesheuvel >> --- >> ArmPkg/Drivers/CpuDxe/CpuDxe.c | 4 +++- >> 1 file changed, 3 insertions(+), 1 deletion(-) >> >> diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/ArmPkg/Drivers/CpuDxe/CpuDxe.c >> index d089cb2d119f..ddc64fd255a0 100644 >> --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.c >> +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.c >> @@ -225,7 +225,7 @@ EFI_CPU_ARCH_PROTOCOL mCpu = { >> CpuGetTimerValue, >> CpuSetMemoryAttributes, >> 0, // NumberOfTimers >> - 4, // DmaBufferAlignment >> + 2048, // DmaBufferAlignment >> }; >> >> EFI_STATUS >> @@ -239,6 +239,8 @@ CpuDxeInitialize ( >> >> InitializeExceptions (&mCpu); >> >> + mCpu.DmaBufferAlignment = ArmCacheWritebackGranule (); >> + > > Could we hide the internal structure of mCpu here by moving this to a > helper function and calling > InitializeDma (&mCpu); > (or something)? > We could, but why? The actual struct is defined 10 lines up