From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::d44; helo=mail-io1-xd44.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io1-xd44.google.com (mail-io1-xd44.google.com [IPv6:2607:f8b0:4864:20::d44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 17A0421164EE6 for ; Sat, 20 Oct 2018 07:06:07 -0700 (PDT) Received: by mail-io1-xd44.google.com with SMTP id z16-v6so24631196iol.6 for ; Sat, 20 Oct 2018 07:06:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=CW9b4yTaxYpFmZ5a3jrAz0lVRJmHnZbUW8LGj4DzY5w=; b=Bs8Dl2WxMMfqexV8ZOKTQ3JTpNSCJXa2xSp3hcLvqzWe+hJb5HAGaUc/66JCOnl35Z OpgDk4dwWg38to63yGYiSu+ZLjVVI4X0OXj8C7V9fVPQmyyWtjNerf+uCqbbupM9+O7o YvrO3f4RZx8s/6FU4VEDoJX4CXoK5b7NjfLJI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=CW9b4yTaxYpFmZ5a3jrAz0lVRJmHnZbUW8LGj4DzY5w=; b=Y3rmppxiyouS7dZbDXXC3EIXnZfKEjRgmZ8IyQbzrg8pw23W3xFFXpm7lHMoj9kyk9 wIGU9WVUbTM9vFy+Bi2v6wF7TnNJSHbdTi3F7MSExJ9PAx8SxaXD6zsZPfbBgIqSBLw7 VkV37QB/uZbfwt+X5+tyiwhFzaS2B3Wu2Vbxoivwp+i4DtEcP4y2I5MbY2GZa5fgdu7k sTRrb9KuDl3e39U273PrnK/tZbLd906qal5LrB2h3ouqfAR2ZA0r3xW9GkwgLNa60l4+ 6CEhbnRbjTe8hkuEQs0YWeupjLSTk5kGTnU3RJx9oxLr8sgnDaCIvOs165uxxFbubGS9 zruA== X-Gm-Message-State: AGRZ1gJxIQfu2G8X/x+eoWBYPEKyea96jKjLmHE5Z8kZDS901vovc27l 9JKZCU5O1GKUEPOaf1KQaUVihrJJ8E2c1YbiIFh8pQ== X-Google-Smtp-Source: AJdET5eTqT9B5kurYt/jhAjofXyiXA/e0ANN1Vj3lFqX/ThMgsntpsyGG1TSXYo95tkSyKUXiQ5b2W+YDXAWesvHjPU= X-Received: by 2002:a6b:be83:: with SMTP id o125-v6mr5233036iof.173.1540044367013; Sat, 20 Oct 2018 07:06:07 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a6b:5910:0:0:0:0:0 with HTTP; Sat, 20 Oct 2018 07:06:06 -0700 (PDT) In-Reply-To: References: <20181019104826.23073-1-ard.biesheuvel@linaro.org> From: Ard Biesheuvel Date: Sat, 20 Oct 2018 22:06:06 +0800 Message-ID: To: Leif Lindholm Cc: "edk2-devel (edk2-devel@lists.01.org)" , Masahisa Kojima Subject: Re: [PATCH edk2-platforms] Silicon/SynQuacerPciCpuIo2Dxe: fix PCIe I/O translation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 20 Oct 2018 14:06:08 -0000 Content-Type: text/plain; charset="UTF-8" On 20 October 2018 at 14:52, Leif Lindholm wrote: > Looks good functionality-wise, but is a bit of a handful to look at (and not > just because I'm code reviewing on a phone). > Could you do it with a couple of temp vars? > Yes, but then CpuIoServiceWrite would deviate from CpuIoServiceRead, so I should probably break this out into a helper function as well. > On Fri, 19 Oct 2018, 18:48 Ard Biesheuvel, > wrote: >> >> Commit 9dd8190e4995 ("Silicon/SynQuacer: tweak PCI I/O windows for >> ACPI/Linux support") updated the min/max/offset definitions for the >> PCIe I/O resource windows on SynQuacer, and updated the read path of >> the platform's EfiCpuIo2 protocol implementation, but failed to update >> the write path as well, resulting in spurious errors if when attempting >> to write to PCIe I/O ports on PCIe RC #1, which uses translation for the >> I/O BAR window. >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ard Biesheuvel >> --- >> >> Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.c >> | 18 ++++++++++++------ >> 1 file changed, 12 insertions(+), 6 deletions(-) >> >> diff --git >> a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.c >> b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.c >> index 736b20cd5129..e5cc3aef908d 100644 >> --- >> a/Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.c >> +++ >> b/Silicon/Socionext/SynQuacer/Drivers/SynQuacerPciCpuIo2Dxe/SynQuacerPciCpuIo2Dxe.c >> @@ -518,12 +518,18 @@ CpuIoServiceWrite ( >> return Status; >> } >> >> - if ((Address >= SYNQUACER_PCI_SEG0_PORTIO_MIN) && >> - (Address <= SYNQUACER_PCI_SEG0_PORTIO_MAX)) { >> - Address += SYNQUACER_PCI_SEG0_PORTIO_MEMBASE; >> - } else if ((Address >= SYNQUACER_PCI_SEG1_PORTIO_MIN) && >> - (Address <= SYNQUACER_PCI_SEG1_PORTIO_MAX)) { >> - Address += SYNQUACER_PCI_SEG1_PORTIO_MEMBASE; >> + if ((Address >= (SYNQUACER_PCI_SEG0_PORTIO_MIN + >> + SYNQUACER_PCI_SEG0_PORTIO_OFFSET)) && >> + (Address <= (SYNQUACER_PCI_SEG0_PORTIO_MAX + >> + SYNQUACER_PCI_SEG0_PORTIO_OFFSET))) { >> + Address += SYNQUACER_PCI_SEG0_PORTIO_MEMBASE - >> + SYNQUACER_PCI_SEG0_PORTIO_OFFSET; >> + } else if ((Address >= (SYNQUACER_PCI_SEG1_PORTIO_MIN + >> + SYNQUACER_PCI_SEG1_PORTIO_OFFSET)) && >> + (Address <= (SYNQUACER_PCI_SEG1_PORTIO_MAX + >> + SYNQUACER_PCI_SEG1_PORTIO_OFFSET))) { >> + Address += SYNQUACER_PCI_SEG1_PORTIO_MEMBASE - >> + SYNQUACER_PCI_SEG1_PORTIO_OFFSET; >> >> } else { >> ASSERT (FALSE); >> -- >> 2.17.1 >> >