From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::241; helo=mail-io0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x241.google.com (mail-io0-x241.google.com [IPv6:2607:f8b0:4001:c06::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 48CCC2034D81D for ; Tue, 7 Nov 2017 10:09:32 -0800 (PST) Received: by mail-io0-x241.google.com with SMTP id 134so3115112ioo.0 for ; Tue, 07 Nov 2017 10:13:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=yP+tpgrGQvgM2yVpBe4SF6VH3ZR18ikoyKvTmod5Lng=; b=gZCSUpMvnruJPOU2w/w2mQuwnnYNrIs5L9JSkMyTCSHbDjJW+HB40olXghFnelOLMf A6vBPP+iOvNm7pmG/rTWH+XzVEFTWnzVbNM27KNoKnDqKaw+TntFn8UWLzxUPF9w/zo8 Yzm8Ufc/Gw3o5rjLZJd+XZMZkeAGIRrReM3vQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=yP+tpgrGQvgM2yVpBe4SF6VH3ZR18ikoyKvTmod5Lng=; b=EVPA3ZHiUftLs57eHpXN3BEo45Bk5o1qubCP4NkKtOSdGrPFuEluB+HDa1K4aexqov LKldeVSCK7l0evV9T2A8L0rqEhrdTKqpyIhDyjq5w/+ZIDUhAOo2Ms+1p1hiXCwI0SKT 1UrLBzwyC3BOOMqQtPVTwuD5q1kgAb3jp/pyMtl/+6Vx1We0RjPa+lqr/t7Tku/Iw17W Mnfqc1A6yzR6vqxcXT4YvxAwoONNayaql1sQkWPP5wmmQAl7qbJEXeF51iNGLG531gF7 wSysYpj3cyTqNy8FttBgkS8y/f5X6Md6xBhjQS8giOg+J22otKEBOnBqeYSwGKcga89f LsPw== X-Gm-Message-State: AJaThX7oJXO48KdAXIr8tIjE0YLqNB/gOvCUAcQjO2Ju6k5sffKjqGG7 SVqxIG511NG/0eXgvqpfg2gUsRRpw6Y/dS+HzwaZDg== X-Google-Smtp-Source: ABhQp+SBHztgrsZHXzvPfhJG/8N8j+CzMQNCTTt97psonk/jMZLvoPtgh1KvDqmunKjF5FxMMa+mNONI76Tlr0+bBDU= X-Received: by 10.107.151.19 with SMTP id z19mr25255641iod.248.1510078411961; Tue, 07 Nov 2017 10:13:31 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.131.167 with HTTP; Tue, 7 Nov 2017 10:13:31 -0800 (PST) In-Reply-To: References: <20171103113352.8604-1-ard.biesheuvel@linaro.org> <20171105055245.xbicmlagfeu7xt2o@bivouac.eciton.net> From: Ard Biesheuvel Date: Tue, 7 Nov 2017 18:13:31 +0000 Message-ID: To: Laszlo Ersek Cc: Leif Lindholm , "edk2-devel@lists.01.org" , "Gao, Liming" Subject: Re: [PATCH v2] ArmPlatformPkg/PrePeiCore: seed temporary stack before entering PEI core X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 07 Nov 2017 18:09:33 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On 7 November 2017 at 18:09, Laszlo Ersek wrote: > On 11/05/17 17:29, Ard Biesheuvel wrote: >> On 5 November 2017 at 16:27, Ard Biesheuvel = wrote: >>> On 5 November 2017 at 05:52, Leif Lindholm w= rote: >>>> On Fri, Nov 03, 2017 at 11:33:52AM +0000, Ard Biesheuvel wrote: >>>>> DEBUG builds of PEI code will print a diagnostic message regarding >>>>> the utilization of temporary RAM before switching to permanent RAM. >>>>> For example, >>>>> >>>>> Total temporary memory: 16352 bytes. >>>>> temporary memory stack ever used: 4820 bytes. >>>>> temporary memory heap used for HobList: 4720 bytes. >>>>> >>>>> Tracking stack utilization like this requires the stack to be seeded >>>>> with a known magic value, and this needs to occur before entering C >>>>> code, given that it uses the stack. Currently, only Nt32Pkg appears >>>>> to implement this feature, but it is useful nonetheless, so let's >>>>> wire it up for PrePeiCore as well. >>>>> >>>>> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D748 >>>>> Contributed-under: TianoCore Contribution Agreement 1.1 >>>>> Signed-off-by: Ard Biesheuvel >>>> >>>> OK, this may sound completely unreasonable, but seeing those >>>> implementations overwrite callee-saved registers without saving them >>>> makes my brain unhappy. (Yes, I know.) >>>> >>>> Could they either: >>>> - Have a comment prepended establishing the implicit ABI of which >>>> registers the caller cannot rely on reusing after return. >>>> Preferably somewhat echoed at the call site. >>>> - Be rewritten to use only scratch registers? >>>> >>> >>> I think it is implied that the startup code does not adhere to the >>> AAPCS. That code already uses r5 and r6 without stacking them, simply >>> because we're in the middle of preparing the stack and other execution >>> context, precisely so the C code we call into can rely on AAPCS >>> guarantees. >> >> >> Ehm, hold on, what do you mean by 'call site'? This code just runs and >> jumps back to a local label. There are no functions calls here until >> the point where we call into C (with the exception of the lovely >> ArmPlatformPeiBootAction() we added so Juno can find out how much DRAM >> it can use) > > Please continue the discussion with Leif on this; from my side, I'm > happy with the patch (I've sort of deduced what the assembly code does, > also relying on your v1 notes). > > The only eyebrow-raising part was: > > + MOV64 (x9, FixedPcdGet32 (PcdInitValueInTempStack) |\ > + FixedPcdGet32 (PcdInitValueInTempStack) << 32) > > where we left-shift a constant that is "in theory" UINT32 by 32 binary > places, using the << operator. In C that would be undefined behavior, > but this is assembly, so what do I know? =C2=AF\_(=E3=83=84)_/=C2=AF > > Acked-by: Laszlo Ersek > Thanks. And you're right, this is not C so no need to worry about that. > ( > > By the way, just to see if I remember correctly, isn't STP: > > +0:stp x9, x9, [x8], #16 > > the kind of instruction that modifies multiple operands at once, and so > if it faults, it cannot be virtualized well? (Because the syndrome > register or whatever does not tell the VMM the whole picture about the > fault?) > > Totally irrelevant here, I'm just curious. > STP =3D=3D STore Pair, and so it stores the values in the registers to memory. The only register that gets modified here is x8, due to the post-increment. But its converse LDP , , [], # is indeed such an instruction, given that it modifies three registers at once, and so the registers that encode the exception run out of space. Note that this only affects virtualized MMIO.