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From: "Ard Biesheuvel" <ard.biesheuvel@linaro.org>
Date: Fri, 24 May 2019 15:08:14 +0200
Message-ID: <CAKv+Gu_CbXobav=Mcb5+DQqaeYQzCmkY72pBKf8Y1nq1zRx93A@mail.gmail.com>
Subject: Re: [edk2-platforms: PATCH v2 06/14] Marvell/Armada7k8k: Add PciExpressLib implementation
To: Marcin Wojtas <mw@semihalf.com>
Cc: edk2-devel-groups-io <devel@edk2.groups.io>, Leif Lindholm <leif.lindholm@linaro.org>, 
	=?UTF-8?B?SmFuIETEhWJyb8Wb?= <jsd@semihalf.com>, 
	Grzegorz Jaszczyk <jaz@semihalf.com>, Kostya Porotchkin <kostap@marvell.com>, Jici Gao <Jici.Gao@arm.com>, 
	Rebecca Cran <rebecca@bluestop.org>, Mark Kettenis <kettenis@jive.eu>
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On Fri, 24 May 2019 at 15:03, Marcin Wojtas <mw@semihalf.com> wrote:
>
> pt., 24 maj 2019 o 14:50 Ard Biesheuvel <ard.biesheuvel@linaro.org> napis=
a=C5=82(a):
> >
> > On Mon, 20 May 2019 at 17:27, Marcin Wojtas <mw@semihalf.com> wrote:
> > >
> > > From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> > >
> > > Implement a special version of PciExpressLib that takes the quirky
> > > nature of the Synopsys Designware PCIe IP into account. In particular=
,
> > > we need to ignore config space accesses to all devices on the first
> > > bus except device 0, because the broadcast nature of type 0 configura=
tion
> > > cycles will result in whatever device is in the slot to appear at eac=
h
> > > of the 32 device positions.
> > >
> >
> > I never bothered to implement multisegment support for this SoC, since
> > MacchiatoBin has only one segment wired up, but since your interest is
> > in generic support, it might make sense to drop this patch and
> > implement PciSegmentLib instead (without depending on any of the other
> > library classes that the generic PciExpressLib depends on)
> >
>
> This was (and still is) my plan, but I've been having some serious
> time shortages for extra development. In order not to postpone this
> support any longer I prefer to get merged, what I have and possibly
> rework on top.
>
> About depending on a generic PciExpressLib - do you mean I can filter
> out devices from bus0 in PciSegmentLib?
>

Yes, please look at Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegment=
Lib

If you follow the same approach, you no longer need PciLib or
PciExpressLib, it is all flattened into PciSegmentLib.