From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-it0-x235.google.com (mail-it0-x235.google.com [IPv6:2607:f8b0:4001:c0b::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0AC4721A00ADA for ; Wed, 28 Jun 2017 05:47:12 -0700 (PDT) Received: by mail-it0-x235.google.com with SMTP id m68so29024148ith.1 for ; Wed, 28 Jun 2017 05:48:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=FVlCAyPhysZLVhq+hTi0LAJK2mBfOLDnVDgPbXeK4Bo=; b=P3EXFiFld7dQpAEyVy41PPNUMXs8u2c2sUyJs4XnM9QFrqG3ckUOS2WxMHaU77MO/V RL1RkROOrzeOZEGQzGR53ok28zrtPyaYUC5DzQYVLladsCh4WREfJyHH7lri9ajClVKu +gLERgggDtKN9UoR4HTukwP+0d2Br5sNtksIw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=FVlCAyPhysZLVhq+hTi0LAJK2mBfOLDnVDgPbXeK4Bo=; b=jPycne+UAW5CfljZ8isC6aKtnpW8DJVOSlz8EJ0fBjD1d1A9XQIYEt+7Uira7eaK9r F7WgqTQiKp0dTj9i0xozMP1kOnUGssB7SNtbofrqX6WJ4WM11VnRF/KEQNmIIwggG5jd 0tmCXZPWAyAv3Ptfy2mwDR8fS9H3mLHYr/q0EWq+YMF+TrE9vPqxJ9sta/ptmcjhavxH vkQ+GMblcFj2e0lWVmwt6kL7SW8VO1F5B+03a6qy3Sd+0emizLlOZHz304nbq6DsOmU2 OHQhzp8BZ51yguxFQY7fl3t9cLC6kN2YxQUjvbNREdqSCFYI/fI76Ro2oKGIt8BiC7fS U68g== X-Gm-Message-State: AKS2vOzPBgrXUzZf5/yjVC9eFwJlYb6i4+wkZQry5dzXWLCZUjFxGB93 TCFR0mkTw0SF6cExOmw+kmW6s2Etr2yk X-Received: by 10.36.26.21 with SMTP id 21mr7751368iti.6.1498654122946; Wed, 28 Jun 2017 05:48:42 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.134.134 with HTTP; Wed, 28 Jun 2017 05:48:42 -0700 (PDT) In-Reply-To: <0C09AFA07DD0434D9E2A0C6AEB0483103B8EF746@shsmsx102.ccr.corp.intel.com> References: <20170628105101.31525-1-ard.biesheuvel@linaro.org> <0C09AFA07DD0434D9E2A0C6AEB0483103B8EF746@shsmsx102.ccr.corp.intel.com> From: Ard Biesheuvel Date: Wed, 28 Jun 2017 12:48:42 +0000 Message-ID: To: "Zeng, Star" Cc: "edk2-devel@lists.01.org" , "Dong, Eric" , "Tian, Feng" , "leif.lindholm@linaro.org" Subject: Re: [PATCH v3] MdeModulePkg/AtaAtapiPassThru: relax PHY detect timeout X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Jun 2017 12:47:12 -0000 Content-Type: text/plain; charset="UTF-8" On 28 June 2017 at 10:55, Zeng, Star wrote: > Reviewed-by: Star Zeng > Thanks Pushed as 1fb805b1eb5b > -----Original Message----- > From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] > Sent: Wednesday, June 28, 2017 6:51 PM > To: edk2-devel@lists.01.org; Zeng, Star ; Dong, Eric > Cc: Tian, Feng ; leif.lindholm@linaro.org; Ard Biesheuvel > Subject: [PATCH v3] MdeModulePkg/AtaAtapiPassThru: relax PHY detect timeout > > The SATA spec mandates that link detection by the PHY completes within > 10 ms after receiving a reset signal. However, there is no obligation to uphold this requirement at the driver end as strictly as we do, and as it turns out, some combinations of host and device (e.g., Samsung > 850 EVO connected to a LeMaker Cello) are only borderline compliant, which means the device is not detected reliably. > > So let's allow for a bit of margin, and increase the PHY detect timeout value to 15 ms. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel > --- > v3: update comment AhciModeInitialization() again > > MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c | 3 +-- MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.h | 3 ++- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c > index 4d01c1dd7fca..b954de81015e 100644 > --- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c > +++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c > @@ -2376,8 +2376,7 @@ AhciModeInitialization ( > AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE); > > // > - // Wait no longer than 10 ms to wait the Phy to detect the presence of a device. > - // It's the requirment from SATA1.0a spec section 5.2. > + // Wait for the Phy to detect the presence of a device. > // > PhyDetectDelay = EFI_AHCI_BUS_PHY_DETECT_TIMEOUT; > Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS; diff --git a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.h b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.h > index 6401fb2e9fcd..809bcc307fc4 100644 > --- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.h > +++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.h > @@ -41,8 +41,9 @@ typedef union { > > // > // Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms. > +// Add a bit of margin for robustness. > // > -#define EFI_AHCI_BUS_PHY_DETECT_TIMEOUT 10 > +#define EFI_AHCI_BUS_PHY_DETECT_TIMEOUT 15 > // > // Refer SATA1.0a spec, the FIS enable time should be less than 500ms. > // > -- > 2.9.3 >