From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by mx.groups.io with SMTP id smtpd.web10.9426.1576761150497934484 for ; Thu, 19 Dec 2019 05:12:31 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@linaro.org header.s=google header.b=Cd8KUYwS; spf=pass (domain: linaro.org, ip: 209.85.128.66, mailfrom: ard.biesheuvel@linaro.org) Received: by mail-wm1-f66.google.com with SMTP id d73so5387224wmd.1 for ; Thu, 19 Dec 2019 05:12:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=4vn4kZprubgeRcjdWAHWZf8QwgEG1RD9kpV7Kqrij6w=; b=Cd8KUYwSrre55S6EOcYuGYqLBtxeUSMtsrrLGuXhSZdKgJGxdv5jxrrVHLu90PRZMI 3DAdgPZvrcVUxnhE/rjgdI9ziHGUhVlKG+QWU2jgrzW1Huhss4JUxBsLt9+jm7ina0SY irAIIi/jOn2jnqFhdizx5+746miRgKXiF2GFenwi6CgnVDqnrr4FeG8+yhvjSjGgQLTn NIQJWM+wYuuLePfGmz8UzNOZ8GfSYAchHJPVcaN3sJd1iJ0eYurAtec7HH4JebsAyIVN feElsvwMo3xedOzbZX4TViqHpmRTQEoFAsoSgOb6nfhCLzxYRkcUT3E8Z4+biddBo23F KhAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=4vn4kZprubgeRcjdWAHWZf8QwgEG1RD9kpV7Kqrij6w=; b=Vi3hMsxx7/RbDXzYYTyJLMVuO0PYISj43g1kkksaA9A3E/kJf8Gfm+YTFaORS/lKdH 37IZOG+3YjiedK8bHRfV9mNqlSOA3BRcbZeTDcGASW0S5SjQh3zznPd7xQ2D9at17pdJ CyxBDKoXT4DIIiGCuuXGTGTYK6iKRM9I6NJoSCIfHM7SWH7A+fTrYiSAr+A/SFu5edlL MHmwhSSaB5mdKmY3sVVIglm4FIe+ySu2jx+OMHvZSqfi5bW5GZUg/67RtaXzDHLdVblX rircWpJ3PjhQy+xu4F6wJQZGWIOioZvbHWOn2PV7kmS3VZPJ+Jwi+Vw5vG0ZoiFwZF/o FeDw== X-Gm-Message-State: APjAAAUio/nCKXJBPnkSzpzj5RwvpJE/keV3w450rF2hi0lwp8uoVBYK QbrdeEhhTs2jgfj5uIGZFPEvSImgrmccYaEatDz3vA== X-Google-Smtp-Source: APXvYqxqtHA53pSfr0k4vbl7FITADaexHSFtbUeOcZPeoWaW2pfV20lOd8+7H/j+JU4BmLav8g+p7cdoHWTAqYXSQPw= X-Received: by 2002:a1c:9d52:: with SMTP id g79mr10088237wme.148.1576761148614; Thu, 19 Dec 2019 05:12:28 -0800 (PST) MIME-Version: 1.0 References: <20191219121434.2856-1-pete@akeo.ie> <20191219121434.2856-7-pete@akeo.ie> In-Reply-To: <20191219121434.2856-7-pete@akeo.ie> From: "Ard Biesheuvel" Date: Thu, 19 Dec 2019 13:12:23 +0000 Message-ID: Subject: Re: [edk2-platforms][PATCH v2 6/7] Platform/RPi4: Add XHCI ACPI table To: Pete Batard Cc: edk2-devel-groups-io , Leif Lindholm , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" Hi Pete, On Thu, 19 Dec 2019 at 14:14, Pete Batard wrote: > > From: Andrei Warkentin > > Since the RPi4 PCIe host bridge is not ECAM compliant, we can > not expose it as a host bridge to the OS via ACPI. However, > given the hardwired nature of this platform, we can expose the > xHCI controller that is guaranteed to live at the base of the > MMIO32 BAR window as a platform device directly. > > It should be noted that the xHCI table is not finalized at this > stage, as Windows xHCI support is still a major question mark. > > Signed-off-by: Pete Batard > --- > Platform/RaspberryPi/RPi4/AcpiTables/AcpiTables.inf | 3 + > Platform/RaspberryPi/RPi4/AcpiTables/Dsdt.asl | 1 + > Platform/RaspberryPi/RPi4/AcpiTables/Xhci.asl | 137 ++++++++++++++++++++ > 3 files changed, 141 insertions(+) > ... > diff --git a/Platform/RaspberryPi/RPi4/AcpiTables/Xhci.asl b/Platform/RaspberryPi/RPi4/AcpiTables/Xhci.asl > new file mode 100644 > index 000000000000..e1fd501ab895 > --- /dev/null > +++ b/Platform/RaspberryPi/RPi4/AcpiTables/Xhci.asl > @@ -0,0 +1,137 @@ > +/** @file > + * > + * Copyright (c) 2019 Linaro, Limited. All rights reserved. > + * Copyright (c) 2019 Andrei Warkentin > + * > + * SPDX-License-Identifier: BSD-2-Clause-Patent > + * > + **/ > + > +#include > + > +/* > + * The following can be used to remove parenthesis from > + * defined macros that the compiler complains about. > + */ > +#define ISOLATE_ARGS(...) __VA_ARGS__ > +#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x > + > +#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW) > +#define SANITIZED_PCIE_REG_BASE REMOVE_PARENTHESES(PCIE_REG_BASE) > + > +/* > + * According to UEFI boot log for the VLI device on Pi 4. > + */ > +#define XHCI_REG_LENGTH 0x1000 > + > +Device (SCB0) { > + Name (_HID, "ACPI0004") > + Name (_UID, 0x0) > + Name (_CCA, 0x0) > + > + Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings > + /* > + * Container devices with _DMA must have _CRS, meaning SCB0 > + * to provide all resources that XHC0 consumes (except > + * interrupts). > + */ > + Name (RBUF, ResourceTemplate () { > + QWordMemory (ResourceProducer, > + , > + MinFixed, > + MaxFixed, > + NonCacheable, > + ReadWrite, > + 0x0, > + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN > + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX > + 0x0, > + 0x1, // LEN > + , > + , > + MMIO > + ) > + }) > + CreateQwordField (RBUF, MMIO._MAX, MMBE) > + CreateQwordField (RBUF, MMIO._LEN, MMLE) > + Add (MMBE, XHCI_REG_LENGTH - 1, MMBE) > + Add (MMLE, XHCI_REG_LENGTH - 1, MMLE) > + Return (RBUF) > + } > + > + Name (_DMA, ResourceTemplate() { > + /* > + * XHC0 is limited to DMA to first 3GB. Note this > + * only applies to PCIe, not GENET or other devices > + * next to the A72. > + */ > + QWordMemory (ResourceConsumer, > + , > + MinFixed, > + MaxFixed, > + NonCacheable, > + ReadWrite, > + 0x0, > + 0x0, // MIN > + 0xbfffffff, // MAX > + 0x0, // TRA > + 0xc0000000, // LEN > + , > + , > + ) > + }) > + > + Device (XHC0) > + { > + Name (_HID, "11063483") // _HID: Hardware ID I failed to spot this detail before. Even if MS appears to do so, I don't think it is OK to string random digits together to create hardware identifiers (and yes, I am aware it's the vendor and device IDs concatenated) What's wrong with using the below as the _HID? > + Name (_CID, "PNP0D10") // _CID: Hardware ID > + Name (_UID, 0x0) // _UID: Unique ID > + Name (_CCA, 0x0) // _CCA: Cache Coherency Attribute > + > + Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings > + Name (RBUF, ResourceTemplate () { > + QWordMemory (ResourceConsumer, > + , > + MinFixed, > + MaxFixed, > + NonCacheable, > + ReadWrite, > + 0x0, > + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN > + SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX > + 0x0, > + 0x1, // LEN > + , > + , > + MMIO > + ) > + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) { > + 175 > + } > + }) > + CreateQwordField (RBUF, MMIO._MAX, MMBE) > + CreateQwordField (RBUF, MMIO._LEN, MMLE) > + Add (MMBE, XHCI_REG_LENGTH - 1, MMBE) > + Add (MMLE, XHCI_REG_LENGTH - 1, MMLE) > + Return (RBUF) > + } > + > + Method (_INI, 0, Serialized) { > + OperationRegion (PCFG, SystemMemory, SANITIZED_PCIE_REG_BASE + PCIE_EXT_CFG_DATA, 0x1000) > + Field (PCFG, AnyAcc, NoLock, Preserve) { > + Offset (0), > + VNID, 16, // Vendor ID > + DVID, 16, // Device ID > + CMND, 16, // Command register > + STAT, 16, // Status register > + } > + > + // Set command register to: > + // 1) decode MMIO (set bit 1) > + // 2) enable DMA (set bit 2) > + // 3) enable interrupts (clear bit 10) > + Debug = "xHCI enable" > + Store (0x6, CMND) > + } > + } > +} > -- > 2.21.0.windows.1 >