From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-it0-x233.google.com (mail-it0-x233.google.com [IPv6:2607:f8b0:4001:c0b::233]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 20A9E21DFA8F2 for ; Thu, 6 Apr 2017 11:46:52 -0700 (PDT) Received: by mail-it0-x233.google.com with SMTP id 19so10796644itj.1 for ; Thu, 06 Apr 2017 11:46:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=VUQhsSwkJ8spFTvNrEJB2spC5I55NTOzoznfRMS7qNY=; b=LiPFctdG9/AnFqrI7X11veGpIC3OW+u7l4Ernv50bwLcipZIjTzuL5xq5/fy91pTX8 XQITQSsBue/CEomz0weC3980t90wRCXJjwYvJS7vwLKDKpKUgjMDv3B6OzmxT6s4BR3y B20PpoWosof+pnYyRB+9xy54JazlfCB8scPz0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=VUQhsSwkJ8spFTvNrEJB2spC5I55NTOzoznfRMS7qNY=; b=qw5fv7vnlZFRdwZYJlCrR4dFRfKwPjD1q79HSbXIPypNoh58D+BerwkPe9AuBIgCk5 8BCzDJCgl3dO9PIEETL4S2rF5WUwKgDEVHdu+oBmP//OX9WZaT2U9oGCqg3bEvOK/VPW ViKaqcm7YPii+K2ep9tInQ1Obk8fzZv/uHW0bpNUqiXBn7lKl9QGb1dzmlg/bcvNK37z +q/Pu1XZ61OYRrS38tJFIUGQcQVZDHSy1/2H+ln1JuZVrYeA1eet+xsorKto04s+Jf5x v4qwPCVi/9XNekVwUIqrGFTULu5vVMJysX0Rxq/8RTp58l/XVPY36sPqMA+QG1TpdG34 KrrQ== X-Gm-Message-State: AFeK/H04rKk9Y4yq1bgStiJIv5DQHw6OXTzSZUi4p+EpL21tiyM/hAiQC9EbB2YHr3zM+bAXsEeC3XTvh8JKUL+z X-Received: by 10.36.27.196 with SMTP id 187mr11808917its.37.1491504411409; Thu, 06 Apr 2017 11:46:51 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.10.27 with HTTP; Thu, 6 Apr 2017 11:46:50 -0700 (PDT) In-Reply-To: <20170406184507.GO25239@bivouac.eciton.net> References: <20170406131551.3322-1-ard.biesheuvel@linaro.org> <20170406131551.3322-2-ard.biesheuvel@linaro.org> <20170406182648.GK25239@bivouac.eciton.net> <20170406184507.GO25239@bivouac.eciton.net> From: Ard Biesheuvel Date: Thu, 6 Apr 2017 19:46:50 +0100 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" , Ryan Harkin , Evan Lloyd , Jeremy Linton Subject: Re: [PATCH v2 1/5] ArmPlatformPkg/FVP: map motherboard VRAM as uncached memory X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Apr 2017 18:46:52 -0000 Content-Type: text/plain; charset=UTF-8 On 6 April 2017 at 19:45, Leif Lindholm wrote: > On Thu, Apr 06, 2017 at 07:31:13PM +0100, Ard Biesheuvel wrote: >> On 6 April 2017 at 19:26, Leif Lindholm wrote: >> > On Thu, Apr 06, 2017 at 02:15:47PM +0100, Ard Biesheuvel wrote: >> >> The VRAM of the PL111 on the FVP Base/Foundation models is described as >> >> device memory rather than uncached memory, which is not an accurate >> >> description of the nature of the region (i.e., a framebuffer), and may >> >> result in problems when using accelerated string routines to access the >> >> region, since this may legally involve unaligned accesses or DC ZVA >> >> instructions, which are not allowed on device mappings. >> >> >> >> So split of the 8 MB VRAM region into a separate region, and map it using >> >> memory attributes. >> > >> > "Normal memory attributes"? >> > >> >> OK >> >> >> >> >> Contributed-under: TianoCore Contribution Agreement 1.0 >> >> Signed-off-by: Ard Biesheuvel >> >> --- >> >> ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h | 10 ++++++---- >> >> ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c | 8 +++++++- >> >> 2 files changed, 13 insertions(+), 5 deletions(-) >> >> >> >> diff --git a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h >> >> index 06414e6e7208..4e17c800a34f 100644 >> >> --- a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h >> >> +++ b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h >> >> @@ -40,9 +40,11 @@ >> >> #define ARM_VE_SMB_SRAM_BASE 0x2E000000 >> >> #define ARM_VE_SMB_SRAM_SZ SIZE_64KB >> >> // USB, Ethernet, VRAM >> >> -#define ARM_VE_SMB_PERIPH_BASE 0x18000000 >> >> -#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE >> >> -#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB >> >> +#define ARM_VE_SMB_PERIPH_BASE 0x18800000 >> >> +#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB - SIZE_8MB) >> >> + >> >> +#define PL111_CLCD_VRAM_MOTHERBOARD_BASE 0x18000000 >> >> +#define PL111_CLCD_VRAM_MOTHERBOARD_SIZE SIZE_8MB >> >> >> >> // DRAM >> >> #define ARM_VE_DRAM_BASE PcdGet64 (PcdSystemMemoryBase) >> >> @@ -75,6 +77,6 @@ >> >> #define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1 >> >> >> >> // VRAM offset for the PL111 Colour LCD Controller on the motherboard >> >> -#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000) >> >> +#define VRAM_MOTHERBOARD_BASE (PL111_CLCD_VRAM_MOTHERBOARD_BASE) >> >> >> >> #endif >> >> diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c >> >> index 14c7e8e1d672..70c17ae70478 100644 >> >> --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c >> >> +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c >> >> @@ -21,7 +21,7 @@ >> >> #include >> >> >> >> // Number of Virtual Memory Map Descriptors >> >> -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 8 >> >> +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9 >> >> >> >> // DDR attributes >> >> #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK >> >> @@ -130,6 +130,12 @@ ArmPlatformGetVirtualMemoryMap ( >> >> VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ; >> >> VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; >> >> >> >> + // VRAM >> >> + VirtualMemoryTable[++Index].PhysicalBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE; >> >> + VirtualMemoryTable[Index].VirtualBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE; >> >> + VirtualMemoryTable[Index].Length = PL111_CLCD_VRAM_MOTHERBOARD_SIZE; >> >> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; >> > >> > Hmm, looking at this made me a bit confused though. Normal uncached >> > memory is certainly bufferable (that's basically what write-combining >> > means). >> > >> >> It maps to MAIR attribute encoding 0x44, which translates as >> >> Normal Memory, Outer Non-Cacheable, Inner Non-Cacheable > > Exactly - which is definitely "buffered". > >> > This looks like a naming hangover from ARMv5 translation table format. >> > Is it about time we clean this up? >> >> The whole 'ARM_MEMORY_REGION_xxxx' intermediate namespace should be >> removed, I think. > > That sounds like a good idea to me. > There's also _NONSECURE crud in there. > Yes. But I hope you're not saying you want that to be done first before this patch can go in?