From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::d43; helo=mail-io1-xd43.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io1-xd43.google.com (mail-io1-xd43.google.com [IPv6:2607:f8b0:4864:20::d43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 21B9A21163272 for ; Mon, 8 Oct 2018 08:10:03 -0700 (PDT) Received: by mail-io1-xd43.google.com with SMTP id q4-v6so16108436iob.8 for ; Mon, 08 Oct 2018 08:10:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=bzWPsYCW+SP6mDtsP8xjYU1eJ1g7l6HRVl7O1pIl5tw=; b=MFCx/pWz41O2N+ChQ9tR/VdWFxUaYL/fq+ANPQW3cBIXRo8JN39Ptv0nS/9Vni8wSu 5IliLrxXzMKOVd+q3OqJnxfBI11dLLhNV2cJSsR0UCRqi1LNyw1Dl8e/s14zMzG1eHTA kF1oy80Ta3NN2oiRiKKlLl2UCLoLED4fZ+jMc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=bzWPsYCW+SP6mDtsP8xjYU1eJ1g7l6HRVl7O1pIl5tw=; b=VCirt4DYw9qbaCc2NBknDvmg6Dmi8NkQqJ6qy6PdtdpgS+PsgIIoU3Cy2OTcXg26Vx Dt058A+jBVqvOCNM8j7W4zTvvx7/2G4Q8aZvm59ZoKQgrVyIDm3F3Mkp4uScE2adVbQE eDGDbqzT61o7Z6qCnEG6zD6dA+ZCYi5wg+PwK30rHuA/Cpzz10BWET+Sm5rNgb4WdDdC GLevnNKcEIdeq9HnOqIHZFzj0Y8u3eDhne/QeLyg4dwan/mRHA4Xjre1scMo1QwnSiID ensUx3RYQ4osHrWtar8w7JArUDHtdXtjJkdbSgZqQUNg2w3Yt0GahgOJRJ77gmvEn7J+ cBxw== X-Gm-Message-State: ABuFfogwTh0geSAWsw1fcYwE5wxIMCYX9kJw2wUMptFKLwdRLQx7ltWX 06yqvucwvqCPwr89N1K/57eczEpn67P6oSTO9siYUw== X-Google-Smtp-Source: ACcGV61CWYftPDe4EXBncbbuEKpEOTn/YY6M8na7cI/N6/ICVa/MwLj9nbyyC/0yo4SJq7ZOg6J/waK+cHUh85ZFGz8= X-Received: by 2002:a6b:be83:: with SMTP id o125-v6mr16017205iof.173.1539011403081; Mon, 08 Oct 2018 08:10:03 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a6b:5910:0:0:0:0:0 with HTTP; Mon, 8 Oct 2018 08:10:02 -0700 (PDT) In-Reply-To: References: <1538745911-22484-1-git-send-email-mw@semihalf.com> <1538745911-22484-3-git-send-email-mw@semihalf.com> From: Ard Biesheuvel Date: Mon, 8 Oct 2018 17:10:02 +0200 Message-ID: To: Marcin Wojtas , "Ni, Ruiyu" , "Wu, Hao A" Cc: "Zeng, Star" , Eric Dong , edk2-devel-01 , "Tian, Feng" , "Kinney, Michael D" , "Gao, Liming" , Leif Lindholm , Nadav Haklai , "jsd@semihalf.com" , Tomasz Michalec Subject: Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 08 Oct 2018 15:10:04 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On 8 October 2018 at 16:52, Marcin Wojtas wrote: > pon., 8 pa=C5=BA 2018 o 15:43 Ard Biesheuvel = napisa=C5=82(a): >> >> On 8 October 2018 at 15:37, Marcin Wojtas wrote: >> > pon., 8 pa=C5=BA 2018 o 15:27 Ard Biesheuvel napisa=C5=82(a): >> >> >> >> On 8 October 2018 at 15:17, Marcin Wojtas wrote: >> >> > pon., 8 pa=C5=BA 2018 o 15:07 Ard Biesheuvel napisa=C5=82(a): >> >> >> >> >> >> On 8 October 2018 at 14:59, Marcin Wojtas wrote: >> >> >> > Hi Ard, >> >> >> > >> >> >> > pon., 8 pa=C5=BA 2018 o 14:41 Ard Biesheuvel napisa=C5=82(a): >> >> >> >> >> >> >> >> (add MdeModulePkg maintainers) >> >> >> >> >> >> >> >> On 5 October 2018 at 15:25, Marcin Wojtas wro= te: >> >> >> >> > From: Tomasz Michalec >> >> >> >> > >> >> >> >> > Some SD Host Controlers use different values in Host Control = 2 Register >> >> >> >> > to select UHS Mode. This patch adds a new UhsSignaling type r= outine to >> >> >> >> > the NotifyPhase of the SdMmcOverride protocol. >> >> >> >> > >> >> >> >> > UHS signaling configuration is moved to a common, default rou= tine >> >> >> >> > (SdMmcHcUhsSignaling), which is called when SdMmcOverride doe= s not >> >> >> >> > cover this functionality. >> >> >> >> > >> >> >> >> > Contributed-under: TianoCore Contribution Agreement 1.1 >> >> >> >> > Signed-off-by: Marcin Wojtas >> >> >> >> > --- >> >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 50 +++++= ++ >> >> >> >> > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 2 + >> >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 153 +++++= +++++++-------- >> >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 37 +++-- >> >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 69 +++++= ++++ >> >> >> >> > 5 files changed, 243 insertions(+), 68 deletions(-) >> >> >> >> > >> >> >> >> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h= b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h >> >> >> >> > index e389d52..a03160d 100644 >> >> >> >> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h >> >> >> >> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h >> >> >> >> > @@ -63,6 +63,39 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF A= NY KIND, EITHER EXPRESS OR IMPLIED. >> >> >> >> > #define SD_MMC_HC_CTRL_VER 0xFE >> >> >> >> > >> >> >> >> > // >> >> >> >> > +// SD Host Controler bits to HOST_CTRL2 register >> >> >> >> > +// >> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_MASK 0x0007 >> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000 >> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001 >> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002 >> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003 >> >> >> >> > +#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004 >> >> >> >> > +#define SD_MMC_HC_CTRL_MMC_DDR52 0x0004 >> >> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR50 0x0002 >> >> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR25 0x0001 >> >> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR12 0x0000 >> >> >> >> > +#define SD_MMC_HC_CTRL_HS200 0x0003 >> >> >> >> > +#define SD_MMC_HC_CTRL_HS400 0x0005 >> >> >> >> > + >> > >> > In case we move enums to SdMmcOverride.h, would it be desired, to move >> > there register fields values as well? Or should I rather use Xenon >> > macros for all of above locally? >> > >> >> No, I think the macros should be kept locally. >> >> >> >> >> > +// >> >> >> >> > +// Timing modes for uhs >> >> >> >> > +// >> >> >> >> > +typedef enum { >> >> >> >> > + SdMmcUhsSdr12, >> >> >> >> > + SdMmcUhsSdr25, >> >> >> >> > + SdMmcUhsSdr50, >> >> >> >> > + SdMmcUhsSdr104, >> >> >> >> > + SdMmcUhsDdr50, >> >> >> >> > + SdMmcMmcDdr52, >> >> >> >> > + SdMmcMmcSdr50, >> >> >> >> > + SdMmcMmcSdr25, >> >> >> >> > + SdMmcMmcSdr12, >> >> >> >> > + SdMmcMmcHs200, >> >> >> >> > + SdMmcMmcHs400, >> >> >> >> > +} SD_MMC_UHS_TIMING; >> >> >> >> > + >> >> >> >> >> >> >> >> Here, we end up with two sets of symbolic constants for the sam= e >> >> >> >> thing, and I suppose this enum will be duplicated in your >> >> >> >> SdMmcOverride implementation? >> >> >> >> >> >> >> > >> >> >> > Why duplicated? Macros are for generic UHS_MODE_SEL field values= for >> >> >> > SD and MMC in HostControl2Register. >> >> >> > >> >> >> > SD_MMC_UHS_TIMING is just a timing mode indicator, it can be use= d not >> >> >> > only in UhsSignaling routine (actually the next patch, with >> >> >> > SwitchClockFreqPost, use it...). >> >> >> > >> >> >> > In my SdMmcOverride implementation this enum is not duplicated, >> >> >> > because this file (SdMmcPciHci.h) is included via >> >> >> > Protocol/SdMmcOverride.h. >> >> >> > >> >> >> >> >> >> Ah ok. Please don't expose internal headers of the SD/MMC driver v= ia >> >> >> Protocol/SdMmcOverride.h >> >> >> >> >> > >> >> > OK. >> >> > >> >> >> I think it should be fine to add the enum definition to >> >> >> Protocol/SdMmcOverride.h instead. >> >> >> >> >> > >> >> > OK. >> >> > >> >> >> But wouldn't it be much easier to have a hook for setting >> >> >> HostControl2Register that decodes the value and modifies it accord= ing >> >> >> to what the platform requires? >> >> >> >> >> > >> >> > Can you please explain, how it will be different from UhsSignaling = in >> >> > current shape (read required timing value and update UHS_MODE_SEL >> >> > field)? >> >> > >> >> >> >> Well, you decode the value, and if, e.g., the SD_MMC_HC_CTRL_HS200 >> >> bits are set, you substitute them with the appropriate xenon values. >> > >> > Because values can be same for SD and MMC (e.g. UHS_104 and HS200), >> > from the controller driver perspective, how would I know, which mode >> > is requested? >> > >> >> Good point. >> >> >> >> >> Also, how important is it to drive the SD/MMC at its max rated speed >> >> at boot time? On Synquacer, I just disable HS200 in the capability >> >> struct so I can forget about all this stuff >> > >> > Some customers want it - a real life scenario from one of them: >> > applications, Linux binaries and rootfs stores in the MMC. Each boot a >> > couple of hundreds of MB to be loaded. Thanks to HS200 we have huge >> > time saving. >> > >> >> Do you mean in the initrd? Because otherwise, Linux will use its own >> driver and select its own mode. > > No, I mean loading >300MB images from eMMC to memory in the DXE phase, > before booting anything. > Yikes >> >> And btw, does the spec permit using different HC2 values for HS200 / HS4= 00 ? > > According to SD Host Controller Specification v4.20, UHS_MODE_SEL > values 0x5 and 0x6 are "reserved". According to Linux code, HS400 > value is treated as "non-standard" and HS200 should be same as for > SDR104 (0x3). Nothing is written about permiting different values, but > given Linux 'sdhci_set_uhs_signaling' and whole bunch of other quirks > used under drivers/mmc overriding standard behavior is very common. > Please let know your desired way of handling custom UhsSignaling. > I suppose this is defined by the eMMC spec. Ruiyu, Hao, could you clarify? Are the host control 2 register values for HS200/HS400 defined by the eMMC spec?