From mboxrd@z Thu Jan  1 00:00:00 1970
Authentication-Results: mx.groups.io;
 dkim=pass header.i=@linaro.org header.s=google header.b=xvFAOTvs;
 spf=pass (domain: linaro.org, ip: 209.85.128.66, mailfrom: ard.biesheuvel@linaro.org)
Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66])
 by groups.io with SMTP; Thu, 19 Sep 2019 05:37:04 -0700
Received: by mail-wm1-f66.google.com with SMTP id a6so4289831wma.5
        for <devel@edk2.groups.io>; Thu, 19 Sep 2019 05:37:03 -0700 (PDT)
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
        d=linaro.org; s=google;
        h=mime-version:references:in-reply-to:from:date:message-id:subject:to
         :cc;
        bh=0Q2NJpDc97fyG9ExboPFtso6kV7MLO3V2CA/DwKyFgs=;
        b=xvFAOTvsY4rY08C6bIuMBMWN2moZ2hFNsviDB9H9ewjoa1fNN2Gt7JRJJynBRJDtB7
         bczjVtWzyro8KHBsKmVcPzhAI4kqeYIzAXBnrB9jnFc3Ggu6lVPklRQL1bzADlJwjnOQ
         ooqwFH0ZNebVZGZlRJ8hDiFOAgU4JIsTzlQRGGW08YGn/aGj8lfAt4CSxwOC1RdeGDkZ
         9O3oKMaYZizEDIVXFqyBXA08REP2kM7MnL7CSwhr+RPFOTkieXB7+AfIjKZc93XQAZvn
         X1ilpdX2BFu26ZFEaLcgOhCYgxtj6l9AD7T8bxspdg+LqTnilyJ9qF6HIxLE+Dlf0l/M
         cWiQ==
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
        d=1e100.net; s=20161025;
        h=x-gm-message-state:mime-version:references:in-reply-to:from:date
         :message-id:subject:to:cc;
        bh=0Q2NJpDc97fyG9ExboPFtso6kV7MLO3V2CA/DwKyFgs=;
        b=mxQDr5r3rA62aARmq/Z4t3LycSghTkElXMMZ0h6afwh2Z5CTdByO+vWMBU4lDo6Jax
         VrZuV8pi0OkjfPILS3a0K/VZyfS4Kyp/W02tQj3zhZg1MTzfk11TJsidWIqA4sbAHCgQ
         7n1nn4WpeY8UVU3nL/2brO/R0shWokz9hwjY8XO/MdU+p3GFUATjXEY6a7ccQmqkV8Vx
         ljY7NVMdBKLU+zTTmHbvRs66W/caRFTXcXMDv/U72LE9kPyzkcF1dX9O+TEv07LKX4Zj
         lAfDUOQEoGwChvvfneXB/dqF8Z0dxfd/OUpjoH6ieh7HeMYXuIKJZXJVBO74h9zCJWvL
         aGFw==
X-Gm-Message-State: APjAAAX2/mwXNM1NLwgooQKz4lw6PLouDGxE+5bsBvHF8KEhlFbOXRuh
	e2hXA/wwu28u29cy2SnXBbm9fAj3Z1p/jGPlZL9Low==
X-Google-Smtp-Source: APXvYqwH0k08dP8OsfCult74SaStRjGiqKeOItq94Dqbkh9V3eYpzVWxUuMzC5Nzupak7wkLl6CYBP3r8GQXA1m0VZU=
X-Received: by 2002:a1c:2546:: with SMTP id l67mr2827919wml.10.1568896621907;
 Thu, 19 Sep 2019 05:37:01 -0700 (PDT)
MIME-Version: 1.0
References: <0d024d72b50b7f5a6d3d908d309810f350c5b1f5.1568808805.git.baptiste.gerondeau@linaro.org>
 <CAKv+Gu_kJf9=cDf7UVBdZTvAurfSfSRAqL_mj46oaaEG9omn8g@mail.gmail.com>
 <20190919094846.GO28454@bivouac.eciton.net> <CAKv+Gu_-mwE2Qa96i4mX5UbgXrfFHC3pC28TOQcSncw8DJUa8g@mail.gmail.com>
 <20190919100921.GR28454@bivouac.eciton.net> <CAKv+Gu9AWVtFL3f-gc3Bxoyka3-1NqgkWeK6Du+4oh1Evxg8ug@mail.gmail.com>
 <CAPiwApxBDj97XbStUaYmDgKfbMsfJ6tRiBr1z6OfqEU-s9KzMw@mail.gmail.com>
 <CAKv+Gu9r8M1EXe0U=R-9ESKLA2d3-VqGe=UheYPR-K4Kj=SP_A@mail.gmail.com>
 <20190919104711.GT28454@bivouac.eciton.net> <CAKv+Gu9S0g5BAC+PeN7AmFtaJvHJT37gGKr_qVksMSy076e3Dw@mail.gmail.com>
 <20190919112531.GU28454@bivouac.eciton.net>
In-Reply-To: <20190919112531.GU28454@bivouac.eciton.net>
From: "Ard Biesheuvel" <ard.biesheuvel@linaro.org>
Date: Thu, 19 Sep 2019 15:36:50 +0300
Message-ID: <CAKv+Gu_L+8Mdu+xxfQAsSdB7NJQQHVd03K1u5qCvK4m5cvzVrQ@mail.gmail.com>
Subject: Re: [PATCH 2/3] ARM/Assembler: Correct syntax from RVCT for MSFT
To: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Baptiste Gerondeau <baptiste.gerondeau@linaro.org>, 
	edk2-devel-groups-io <devel@edk2.groups.io>, "Kinney, Michael D" <michael.d.kinney@intel.com>, 
	"Gao, Liming" <liming.gao@intel.com>, "Zhang, Shenglei" <shenglei.zhang@intel.com>, 
	Baptiste GERONDEAU <bgerondeau@gmail.com>
Content-Type: text/plain; charset="UTF-8"

On Thu, 19 Sep 2019 at 14:25, Leif Lindholm <leif.lindholm@linaro.org> wrote:
>
> On Thu, Sep 19, 2019 at 01:53:35PM +0300, Ard Biesheuvel wrote:
> > > > I mean that I'd prefer to assemble the .asm files in ARM mode,
> > > > especially since I am not convinced that the startup code we have is
> > > > guaranteed to switch into the right mode after the CPU comes out of
> > > > reset in ARM mode.
> > >
> > > That could be resolved with a trivial branch at that point (or just
> > > forcing ARM for the whole entry file) though.
> > >
> >
> > Of course.
> >
> > The problem is that the first branch instruction is patched into the
> > FV files by the BaseTools, and so the startup code is entered in ARM
> > mode by default.
> >
> > So that means we'll either have to
> > 1) switch to ARM mode
> > 2) emit one branch instruction
> > 3) switch back to Thumb mode
>
> I was thinking more like tying down the entry function (or as I said,
> the whole file) as ARM, then letting the toolchain decide for the bits
> where we don't have instuction-set dependent ABIs.
>
> > 4) fix up all the code so it assembles in Thumb mode
>
> Which is what Baptiste has done in this set.
>
> > 1) switch to ARM mode
>
> In all 48 files (+3 in edk2-platforms), or just the ones where not
> doing so triggers build errors? Currently.
>
> I'm OK with restricting ourselves to just setting ARM in the
> triggering files for simplicity, especially in order to streamline the
> toolchain migration from RVCT to VS (and the subsequent purge of PVCT
> support). I'm not seeing it as a solution.
>

As long as we align the .asm files with the .S files, I am fine with
that. And since we focus on v7+ only these days, I'm fine with
changing existing ARM files to Thumb2.

What I don't want is a situation where the toolchain's default decides
how code is assembled, since that means you have to test all your code
changes twice.