From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::22a; helo=mail-it0-x22a.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x22a.google.com (mail-it0-x22a.google.com [IPv6:2607:f8b0:4001:c0b::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3BF4321FD73E6 for ; Mon, 19 Feb 2018 00:14:32 -0800 (PST) Received: by mail-it0-x22a.google.com with SMTP id l187so8431819ith.4 for ; Mon, 19 Feb 2018 00:20:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=6pD+W5507kn8sCwPgyInxoZVA8UC4smOnAHzySx+i44=; b=FVi10yxHg18d9iTrHbdnpbmmMoUMo3YyePXW06ex0zCkNDrUge9P8KNNwpaeS/us3y hAO2ARSs3XHMnfw79ZkgC6v4H0Z0l+UScE38LEbh/zi5erpNEdQZwQGMtoYk+D1t6JEb dulkgs7kBQEGdTIFAtfTve238IBoIZxeSkDYk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=6pD+W5507kn8sCwPgyInxoZVA8UC4smOnAHzySx+i44=; b=tJhSLCDt7YFyzoKn5ePinhYQL+L0u4syMZBH+cLlIjO2NTmq40wUphRwop5Y3Yf7t9 sQDkmV5zUwc9PmRbNDpotB8HIN87RbNFla9YEalK8iNG6RC7q77Kyg3Y1TVt/jyYMicV BqWsQeS55Z4I+XkkG5/RCWfB3pibsNxnPri733HLGjLTltdLtqCJ2+XIcYWKjiZ4yvCN MMcE76Yw/LM/ywKnwLRsP3wahGfvPFktP5b2JtK/I1T7RKXNEC6XUFahlcM+aEhwz16H 7rZ7nqp90przJ6NWkKFoyZCiFdPRAliih/ZxI8tynw1kWp6ZXyTU+hlBYJzSMOu1TBIU dPzQ== X-Gm-Message-State: APf1xPCMEr3dL89GcQiclPPy15XESNtYt3fBpV6vcEurd3c541IpM0GA z9s7miCyMncFGlwCX7Y4XhBAAtcaa4G+E/8jLu8KBA== X-Google-Smtp-Source: AH8x225A+eeu8Nfe3ufaS6t4HU29H19rho/+nsRUJ4Ysg1QRXc7EhoDm81bA9Cd4U34aof7t+8Her6O7Xz78D0sTGo8= X-Received: by 10.36.90.5 with SMTP id v5mr445691ita.138.1519028428893; Mon, 19 Feb 2018 00:20:28 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.138.209 with HTTP; Mon, 19 Feb 2018 00:20:28 -0800 (PST) In-Reply-To: <20180218113936.6f4fdemn7yurjac3@bivouac.eciton.net> References: <20180215172054.27452-1-ard.biesheuvel@linaro.org> <20180215172054.27452-2-ard.biesheuvel@linaro.org> <20180216170020.inkadbvnr25zczhh@bivouac.eciton.net> <20180218113936.6f4fdemn7yurjac3@bivouac.eciton.net> From: Ard Biesheuvel Date: Mon, 19 Feb 2018 08:20:28 +0000 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" , Joakim Bech Subject: Re: [PATCH edk2-platforms 1/5] Silicon/SynQuaver/DeviceTree: add node for SPI controller X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 19 Feb 2018 08:14:33 -0000 Content-Type: text/plain; charset="UTF-8" On 18 February 2018 at 11:39, Leif Lindholm wrote: > On Fri, Feb 16, 2018 at 06:34:30PM +0000, Ard Biesheuvel wrote: >> On 16 February 2018 at 17:00, Leif Lindholm wrote: >> > On Thu, Feb 15, 2018 at 05:20:50PM +0000, Ard Biesheuvel wrote: >> >> Add a node for the SPI controller to the device tree so the OS may >> >> attach to it. This is the SPI controller that is attached to the >> >> 96boards mezzanine connector on Developer Box. >> > >> > Just a generic question (which also applies to the subsequent patch): >> > Are there any implications here with regards to this bus running in >> > master or slave mode? >> > >> >> Not really, since that depends entirely on the OS. We just assert the >> presence of a certain IP block at a certain memory offset, and whether >> the hardware supports slave mode is left unspecified. Whether the OS >> supports slave mode (for this particular IP block) is not a property >> of the hardware. > > I was thinking more along the lines of whether the hardware supports > slave mode or not (perhaps as a synthesis option). > > But, fair enough. > > If you change SynQuaver -> SynQuacer in 1-2 subject lines, for the series: > Reviewed-by: Leif Lindholm > Excellent, thanks. However, I am going to respin this and make it much more generic: - create a separate, generic MezzanineDxe driver (with its own HII menu option) - redefine all GPIO, I2C and SPI references in terms of the 96boards spec, e.g., GPIO-A, GPIO-B, GPIO-C That way, you can basically specify how the LS connector has been integrated (which I2C/SPI/GPIO), and support anything that the generic driver supports. This is only up to a point, of course. Using the Secure96 RNG in UEFI requires a UEFI driver, and some I2C plumbing, but I am trying to make that generic as well (which is feasible if the I2C bus on the LS connector does not contain anything else that UEFI cares about)