From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::234; helo=mail-io0-x234.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x234.google.com (mail-io0-x234.google.com [IPv6:2607:f8b0:4001:c06::234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 61E962035B2C5 for ; Sat, 23 Dec 2017 05:39:23 -0800 (PST) Received: by mail-io0-x234.google.com with SMTP id k202so18937605ioe.10 for ; Sat, 23 Dec 2017 05:44:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=vIpsrPSenJ5d6HCCKtxF2Sn6laJ2dh3tdwNWXtJtasw=; b=A8TlRpFF+WjizWbteOW+NkfMe9HQ332dInp0C1h4d2EZwPRJk3R6mriiwCjgs3LNIj fhGUriCrLe3zE3QGJqJesznW/B6687Objs7w871efO1eGhOiEVuLNx9islCGw2H0Hz2x XXkQdAIqpi/88JEE8bvO1QarmkRc8RtLQrZnw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=vIpsrPSenJ5d6HCCKtxF2Sn6laJ2dh3tdwNWXtJtasw=; b=sBcWosACHBF3P3wUoXABD8gYYYCOA1uvd4CAkUqpIdBS3OVc19CEgFAAwf3OYCYx12 HwiD50twxCQPIwUFwXZdZ3SrqCvhe9brWq2bB8jXhJLCI72mnqc4PkwxygK55jbFUXZE 3eNTJY9XKWmh1xoOCEbdNlSrXCtOzqIbslGp/Avc4QLyp3KchsPzOuNIuJV+0AtYklFM +VKoCQABhZSlpCK/SysyYomox4txfUjQHIavpRAyvbTaGP+FUNsf/JkzUIDiBQq0b9bP pV68RmZMP2VNEp0DxEOzrAFjV99RDcY8IUPqoJHbrsBI3PtqMhaAFLDVxaQ4FrKjlNn0 hrkA== X-Gm-Message-State: AKGB3mJYRpSO1TWoSG0fH2DkYtTjp7dkLwDXQxwAh0jozxtlNd15fc4H VV9XcTb7cFkbRX7xRXn/HZaMHYYbcaqL9r3UdQ1wkw== X-Google-Smtp-Source: ACJfBouJ48idBOw3f/K2A+JStcls1l0xrxqiB787VIKS6X+62nwgtMlRXruZGLZrg9jULHahRPS0AZ1EhSrvze4y7Js= X-Received: by 10.107.137.15 with SMTP id l15mr22192501iod.52.1514036653350; Sat, 23 Dec 2017 05:44:13 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.52.14 with HTTP; Sat, 23 Dec 2017 05:44:12 -0800 (PST) In-Reply-To: <20171222183418.8616-13-evan.lloyd@arm.com> References: <20171222183418.8616-1-evan.lloyd@arm.com> <20171222183418.8616-13-evan.lloyd@arm.com> From: Ard Biesheuvel Date: Sat, 23 Dec 2017 13:44:12 +0000 Message-ID: To: Evan Lloyd Cc: "edk2-devel@lists.01.org" , <"ard.biesheuvel@linaro.org"@arm.com>, <"leif.lindholm@linaro.org"@arm.com>, <"Matteo.Carlini@arm.com"@arm.com>, <"nd@arm.com"@arm.com> Subject: Re: [PATCH v2 12/13] ArmPlatformPkg: New DP500/DP550/DP650 GOP driver. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 23 Dec 2017 13:39:23 -0000 Content-Type: text/plain; charset="UTF-8" On 22 December 2017 at 18:34, wrote: > From: Girish Pathak > > This change adds support for the ARM Mali DP500/DP500/DP650 display > processors using the GOP protocol. It has been tested on FVP base > models + DP550 support. This change adds platform independant LcdHwLib > library. A corresponding platform specific library will be submitted > to edk-platforms/Platform/ARM/VExpressPkg. > > This change does not modify functionality provided by PL111 or > HDLCD. This LcdHwLib implementation should be suitable for those > platforms that implement ARM Mali DP500/DP550/DP650 replacing > PL111/HDLCD. > > Only graphics layer of the ARM Mali DP is configured for rendering > the RGB/BGR format frame buffer to satisfy the UEFI GOP requirements > Other layers e.g. video layers are not configured. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Girish Pathak > Signed-off-by: Evan Lloyd > --- > ArmPlatformPkg/ArmPlatformPkg.dec | 4 + > ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.inf | 44 +++ > ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.h | 243 ++++++++++++ > ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.c | 414 ++++++++++++++++++++ > 4 files changed, 705 insertions(+) > Please add this library as a component to ArmPlatformPkg.dsc as well, so we can do build testing on it. > diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec > index a887ffcfd9f3b168bfb19ff0a84e310c7891b527..a05cf59fbe6278bc69a674f128a4349477052e3d 100644 > --- a/ArmPlatformPkg/ArmPlatformPkg.dec > +++ b/ArmPlatformPkg/ArmPlatformPkg.dec > @@ -93,6 +93,10 @@ [PcdsFixedAtBuild.common] > gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026 > gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027 > > + ## ARM Mali Display Processor DP500/DP550/DP650 > + gArmPlatformTokenSpaceGuid.PcdArmMaliDpBase|0x0|UINT64|0x00000050 > + gArmPlatformTokenSpaceGuid.PcdArmMaliDpMemoryRegionLength|0x0|UINT32|0x00000051 > + > ## If set, frame buffer memory will be reserved and mapped in the system RAM > gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize|0x0|UINT32|0x00000043 > gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase|0x0|UINT64|0x00000044 > diff --git a/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.inf b/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.inf > new file mode 100644 > index 0000000000000000000000000000000000000000..461b194b2719d1b3761bee2bbb0e3a245d72fdc1 > --- /dev/null > +++ b/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.inf > @@ -0,0 +1,44 @@ > +#/** @file ArmMaliDp.inf > +# > +# Component description file for ArmMaliDp module > +# > +# Copyright (c) 2017, ARM Ltd. All rights reserved.
> +# This program and the accompanying materials > +# are licensed and made available under the terms and conditions of the BSD License > +# which accompanies this distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +# > +#**/ > + > +[Defines] > + INF_VERSION = 0x00010019 > + BASE_NAME = ArmMaliDp > + FILE_GUID = E724AAF7-19E2-40A3-BAE1-D82A7C8B7A76 > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = LcdHwLib > + > +[Sources.common] > + ArmMaliDp.c > + > +[Packages] > + ArmPkg/ArmPkg.dec > + ArmPlatformPkg/ArmPlatformPkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + Platform/ARM/VExpressPkg/ArmVExpressPkg.dec Please drop references to edk2-platforms. This driver should be able to be used independently from VExpress platform code. > + > +[LibraryClasses] > + BaseLib > + BaseMemoryLib > + DebugLib > + IoLib > + LcdPlatformLib > + UefiLib > + > +[FixedPcd] > + gArmPlatformTokenSpaceGuid.PcdArmMaliDpBase > + > diff --git a/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.h b/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.h > new file mode 100644 > index 0000000000000000000000000000000000000000..ca071093ebb6b0da8ace50ab57d3506b86d53fe9 > --- /dev/null > +++ b/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.h > @@ -0,0 +1,243 @@ > +/** @file > + > + This header file contains the platform independent parts of ARM Mali DP > + > + Copyright (c) 2017, ARM Ltd. All rights reserved.
> + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the BSD License > + which accompanies this distribution. The full text of the license may be found at > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > +**/ > +#ifndef ARMMALIDP_H_ > +#define ARMMALIDP_H_ > + > +#define DP_BASE (FixedPcdGet64 (PcdArmMaliDpBase)) > + > +// MALI DP Ids > +#define MALIDP_NOT_PRESENT 0xFFF > +#define MALIDP_500 0x500 > +#define MALIDP_550 0x550 > +#define MALIDP_650 0x650 > + > +// DP500 Peripheral Ids > +#define DP500_ID_PART_0 0x00 > +#define DP500_ID_DES_0 0xB > +#define DP500_ID_PART_1 0x5 > + > +#define DP500_ID_REVISION 0x1 > +#define DP500_ID_JEDEC 0x1 > +#define DP500_ID_DES_1 0x3 > + > +#define DP500_PERIPHERAL_ID0_VAL (DP500_ID_PART_0) > +#define DP500_PERIPHERAL_ID1_VAL ((DP500_ID_DES_0 << 4) \ > + | DP500_ID_PART_1) > +#define DP500_PERIPHERAL_ID2_VAL ((DP500_ID_REVISION << 4) \ > + | (DP500_ID_JEDEC << 3) \ > + | (DP500_ID_DES_1)) > + > +// DP550 Peripheral Ids > +#define DP550_ID_PART_0 0x50 > +#define DP550_ID_DES_0 0xB > +#define DP550_ID_PART_1 0x5 > + > +#define DP550_ID_REVISION 0x0 > +#define DP550_ID_JEDEC 0x1 > +#define DP550_ID_DES_1 0x3 > + > +#define DP550_PERIPHERAL_ID0_VAL (DP550_ID_PART_0) > +#define DP550_PERIPHERAL_ID1_VAL ((DP550_ID_DES_0 << 4) \ > + | DP550_ID_PART_1) > +#define DP550_PERIPHERAL_ID2_VAL ((DP550_ID_REVISION << 4) \ > + | (DP550_ID_JEDEC << 3) \ > + | (DP550_ID_DES_1)) > + > +// DP650 Peripheral Ids > +#define DP650_ID_PART_0 0x50 > +#define DP650_ID_DES_0 0xB > +#define DP650_ID_PART_1 0x6 > + > +#define DP650_ID_REVISION 0x0 > +#define DP650_ID_JEDEC 0x1 > +#define DP650_ID_DES_1 0x3 > + > +#define DP650_PERIPHERAL_ID0_VAL (DP650_ID_PART_0) > +#define DP650_PERIPHERAL_ID1_VAL ((DP650_ID_DES_0 << 4) \ > + | DP650_ID_PART_1) > +#define DP650_PERIPHERAL_ID2_VAL ((DP650_ID_REVISION << 4) \ > + | (DP650_ID_JEDEC << 3) \ > + | (DP650_ID_DES_1)) > + > +// Display Engine (DE) control register offsets for DP550/DP650 > +#define DP_DE_STATUS 0x00000 > +#define DP_DE_IRQ_SET 0x00004 > +#define DP_DE_IRQ_MASK 0x00008 > +#define DP_DE_IRQ_CLEAR 0x0000C > +#define DP_DE_CONTROL 0x00010 > +#define DP_DE_PROG_LINE 0x00014 > +#define DP_DE_AXI_CONTROL 0x00018 > +#define DP_DE_AXI_QOS 0x0001C > +#define DP_DE_DISPLAY_FUNCTION 0x00020 > + > +#define DP_DE_H_INTERVALS 0x00030 > +#define DP_DE_V_INTERVALS 0x00034 > +#define DP_DE_SYNC_CONTROL 0x00038 > +#define DP_DE_HV_ACTIVESIZE 0x0003C > +#define DP_DE_DISPLAY_SIDEBAND 0x00040 > +#define DP_DE_BACKGROUND_COLOR 0x00044 > +#define DP_DE_DISPLAY_SPLIT 0x00048 > +#define DP_DE_OUTPUT_DEPTH 0x0004C > + > +// Display Engine (DE) control register offsets for DP500 > +#define DP_DE_DP500_CORE_ID 0x00018 > +#define DP_DE_DP500_CONTROL 0x0000C > +#define DP_DE_DP500_PROG_LINE 0x00010 > +#define DP_DE_DP500_H_INTERVALS 0x00028 > +#define DP_DE_DP500_V_INTERVALS 0x0002C > +#define DP_DE_DP500_SYNC_CONTROL 0x00030 > +#define DP_DE_DP500_HV_ACTIVESIZE 0x00034 > +#define DP_DE_DP500_BG_COLOR_RG 0x0003C > +#define DP_DE_DP500_BG_COLOR_B 0x00040 > + > +/* Display Engine (DE) graphics layer (LG) register offsets > + * NOTE: For DP500 it will be LG2. > + */ > +#define DE_LG_OFFSET 0x00300 > +#define DP_DE_LG_FORMAT (DE_LG_OFFSET) > +#define DP_DE_LG_CONTROL (DE_LG_OFFSET + 0x04) > +#define DP_DE_LG_COMPOSE (DE_LG_OFFSET + 0x08) > +#define DP_DE_LG_IN_SIZE (DE_LG_OFFSET + 0x0C) > +#define DP_DE_LG_CMP_SIZE (DE_LG_OFFSET + 0x10) > +#define DP_DE_LG_OFFSET (DE_LG_OFFSET + 0x14) > +#define DP_DE_LG_H_STRIDE (DE_LG_OFFSET + 0x18) > +#define DP_DE_LG_PTR_LOW (DE_LG_OFFSET + 0x1C) > +#define DP_DE_LG_PTR_HIGH (DE_LG_OFFSET + 0x20) > +#define DP_DE_LG_CHROMA_KEY (DE_LG_OFFSET + 0x2C) > +#define DP_DE_LG_AD_CONTROL (DE_LG_OFFSET + 0x30) > +#define DP_DE_LG_MMU_CONTROL (DE_LG_OFFSET + 0x48) > + > +// Display core (DC) control register offsets. > +#define DP_DC_OFFSET 0x0C000 > +#define DP_DC_STATUS (DP_DC_OFFSET + 0x00) > +#define DP_DC_IRQ_SET (DP_DC_OFFSET + 0x04) > +#define DP_DC_IRQ_MASK (DP_DC_OFFSET + 0x08) > +#define DP_DC_IRQ_CLEAR (DP_DC_OFFSET + 0x0C) > +#define DP_DC_CONTROL (DP_DC_OFFSET + 0x10) > +#define DP_DC_CONFIG_VALID (DP_DC_OFFSET + 0x14) > +#define DP_DC_CORE_ID (DP_DC_OFFSET + 0x18) > + > +// DP500 has a global configuration register. > +#define DP_DP500_CONFIG_VALID (0xF00) > + > +// Display core ID register offsets. > +#define DP_DC_ID_OFFSET 0x0FF00 > +#define DP_DC_ID_PERIPHERAL_ID4 (DP_DC_ID_OFFSET + 0xD0) > +#define DP_DC_CONFIGURATION_ID (DP_DC_ID_OFFSET + 0xD4) > +#define DP_DC_PERIPHERAL_ID0 (DP_DC_ID_OFFSET + 0xE0) > +#define DP_DC_PERIPHERAL_ID1 (DP_DC_ID_OFFSET + 0xE4) > +#define DP_DC_PERIPHERAL_ID2 (DP_DC_ID_OFFSET + 0xE8) > +#define DP_DC_COMPONENT_ID0 (DP_DC_ID_OFFSET + 0xF0) > +#define DP_DC_COMPONENT_ID1 (DP_DC_ID_OFFSET + 0xF4) > +#define DP_DC_COMPONENT_ID2 (DP_DC_ID_OFFSET + 0xF8) > +#define DP_DC_COMPONENT_ID3 (DP_DC_ID_OFFSET + 0xFC) > + > +#define DP_DP500_ID_OFFSET 0x0F00 > +#define DP_DP500_ID_PERIPHERAL_ID4 (DP_DP500_ID_OFFSET + 0xD0) > +#define DP_DP500_CONFIGURATION_ID (DP_DP500_ID_OFFSET + 0xD4) > +#define DP_DP500_PERIPHERAL_ID0 (DP_DP500_ID_OFFSET + 0xE0) > +#define DP_DP500_PERIPHERAL_ID1 (DP_DP500_ID_OFFSET + 0xE4) > +#define DP_DP500_PERIPHERAL_ID2 (DP_DP500_ID_OFFSET + 0xE8) > +#define DP_DP500_COMPONENT_ID0 (DP_DP500_ID_OFFSET + 0xF0) > +#define DP_DP500_COMPONENT_ID1 (DP_DP500_ID_OFFSET + 0xF4) > +#define DP_DP500_COMPONENT_ID2 (DP_DP500_ID_OFFSET + 0xF8) > +#define DP_DP500_COMPONENT_ID3 (DP_DP500_ID_OFFSET + 0xFC) > + > +// Display status configuration mode activation flag > +#define DP_DC_STATUS_CM_ACTIVE_FLAG (0x1U << 16) > + > +// Display core control configuration mode > +#define DP_DC_CONTROL_SRST_ACTIVE (0x1U << 18) > +#define DP_DC_CONTROL_CRST_ACTIVE (0x1U << 17) > +#define DP_DC_CONTROL_CM_ACTIVE (0x1U << 16) > + > +#define DP_DE_DP500_CONTROL_SOFTRESET_REQ (0x1U << 16) > +#define DP_DE_DP500_CONTROL_CONFIG_REQ (0x1U << 17) > + > +// Display core configuration valid register > +#define DP_DC_CONFIG_VALID_CVAL (0x1U) > + > +// DC_CORE_ID > +// Display core version register PRODUCT_ID > +#define DP_DC_CORE_ID_SHIFT 16 > +#define DP_DE_DP500_CORE_ID_SHIFT DP_DC_CORE_ID_SHIFT > + > +// Timing settings > +#define DP_DE_HBACKPORCH_SHIFT 16 > +#define DP_DE_VBACKPORCH_SHIFT 16 > +#define DP_DE_VSP_SHIFT 28 > +#define DP_DE_VSYNCWIDTH_SHIFT 16 > +#define DP_DE_HSP_SHIFT 13 > +#define DP_DE_V_ACTIVE_SHIFT 16 > + > +// BACKGROUND_COLOR > +#define DP_DE_BG_R_PIXEL_SHIFT 16 > +#define DP_DE_BG_G_PIXEL_SHIFT 8 > + > +//Graphics layer LG_FORMAT Pixel Format > +#define DP_PIXEL_FORMAT_ARGB_8888 0x8 > +#define DP_PIXEL_FORMAT_ABGR_8888 0x9 > +#define DP_PIXEL_FORMAT_RGBA_8888 0xA > +#define DP_PIXEL_FORMAT_BGRA_8888 0xB > +#define DP_PIXEL_FORMAT_XRGB_8888 0x10 > +#define DP_PIXEL_FORMAT_XBGR_8888 0x11 > +#define DP_PIXEL_FORMAT_RGBX_8888 0x12 > +#define DP_PIXEL_FORMAT_BGRX_8888 0x13 > +#define DP_PIXEL_FORMAT_RGB_888 0x18 > +#define DP_PIXEL_FORMAT_BGR_888 0x19 > + > +// DP500 format code are different than DP550/DP650 > +#define DP_PIXEL_FORMAT_DP500_ARGB_8888 0x2 > +#define DP_PIXEL_FORMAT_DP500_ABGR_8888 0x3 > +#define DP_PIXEL_FORMAT_DP500_XRGB_8888 0x4 > +#define DP_PIXEL_FORMAT_DP500_XBGR_8888 0x5 > + > +// Graphics layer LG_PTR_LOW and LG_PTR_HIGH > +#define DP_DE_LG_PTR_LOW_MASK 0xFFFFFFFFU > +#define DP_DE_LG_PTR_HIGH_SHIFT 32 > + > +// Graphics layer LG_CONTROL register characteristics > +#define DP_DE_LG_L_ALPHA_SHIFT 16 > +#define DP_DE_LG_CHK_SHIFT 15 > +#define DP_DE_LG_PMUL_SHIFT 14 > +#define DP_DE_LG_COM_SHIFT 12 > +#define DP_DE_LG_VFP_SHIFT 11 > +#define DP_DE_LG_HFP_SHIFT 10 > +#define DP_DE_LG_ROTATION_SHIFT 8 > + > +#define DP_DE_LG_LAYER_BLEND_NO_BG 0x0U > +#define DP_DE_LG_PIXEL_BLEND_NO_BG 0x1U > +#define DP_DE_LG_LAYER_BLEND_BG 0x2U > +#define DP_DE_LG_PIXEL_BLEND_BG 0x3U > +#define DP_DE_LG_ENABLE 0x1U > + > +// Graphics layer LG_IN_SIZE register characteristics > +#define DP_DE_LG_V_IN_SIZE_SHIFT 16 > + > +// Graphics layer LG_CMP_SIZE register characteristics > +#define DP_DE_LG_V_CMP_SIZE_SHIFT 16 > +#define DP_DE_LG_V_OFFSET_SHIFT 16 > + > +// Helper display timing macro functions. > +#define H_INTERVALS(Hfp, Hbp) ((Hbp << DP_DE_HBACKPORCH_SHIFT) | Hfp) > +#define V_INTERVALS(Vfp, Vbp) ((Vbp << DP_DE_VBACKPORCH_SHIFT) | Vfp) > +#define SYNC_WIDTH(Hsw, Vsw) ((Vsw << DP_DE_VSYNCWIDTH_SHIFT) | Hsw) > +#define HV_ACTIVE(Hor, Ver) ((Ver << DP_DE_V_ACTIVE_SHIFT) | Hor) > + > +// Helper layer graphics macros. > +#define FRAME_IN_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_IN_SIZE_SHIFT) | Hor) > +#define FRAME_CMP_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_CMP_SIZE_SHIFT) | Hor) > + > +#endif /* ARMMALIDP_H_ */ > diff --git a/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.c b/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.c > new file mode 100644 > index 0000000000000000000000000000000000000000..804c292060bef9851dd56bdc60664027df2c3b6a > --- /dev/null > +++ b/ArmPlatformPkg/Library/ArmMaliDp/ArmMaliDp.c > @@ -0,0 +1,414 @@ > +/** @file > + > + ARM Mali DP 500/550/650 display controller driver > + > + Copyright (c) 2017, ARM Ltd. All rights reserved.
> + > + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the BSD License > + which accompanies this distribution. The full text of the license may be found at > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > + > +#include "ArmMaliDp.h" > + > +// CORE_ID of the MALI DP > +STATIC UINT32 mDpDeviceId; > + > +/** Disable the graphics layer > + > + This is done by clearing the EN bit of the LG_CONTROL register. > +**/ > +STATIC > +VOID > +LayerGraphicsDisable (VOID) > +{ > + MmioAnd32 (DP_BASE + DP_DE_LG_CONTROL, ~DP_DE_LG_ENABLE); > +} > + > +/** Enable the graphics layer > + > + This is done by setting the EN bit of the LG_CONTROL register. > +**/ > +STATIC > +VOID > +LayerGraphicsEnable (VOID) > +{ > + MmioOr32 (DP_BASE + DP_DE_LG_CONTROL, DP_DE_LG_ENABLE); > +} > + > +/** Set the frame address of the graphics layer. > + > + @param[in] FrameBaseAddress Address of the data buffer to be used as > + a frame buffer. > +**/ > +STATIC > +VOID > +LayerGraphicsSetFrame ( > + IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress > + ) > +{ > + // Disable the graphics layer. > + LayerGraphicsDisable (); > + > + // Set up memory address of the data buffer for graphics layer. > + // write lower bits of the address. > + MmioWrite32 ( > + DP_BASE + DP_DE_LG_PTR_LOW, > + DP_DE_LG_PTR_LOW_MASK & FrameBaseAddress > + ); > + > + // Write higher bits of the address. > + MmioWrite32 ( > + DP_BASE + DP_DE_LG_PTR_HIGH, > + (UINT32)(FrameBaseAddress >> DP_DE_LG_PTR_HIGH_SHIFT) > + ); > + > + // Enable the graphics layer. > + LayerGraphicsEnable (); > +} > + > +/** Configures various graphics layer characteristics. > + > + @param[in] UefiGfxPixelFormat This must be either > + PixelBlueGreenRedReserved8BitPerColor > + OR > + PixelRedGreenBlueReserved8BitPerColor > + @param[in] HRes Horizontal resolution of the graphics layer. > + @param[in] VRes Vertical resolution of the graphics layer. > +**/ > +STATIC > +VOID > +LayerGraphicsConfig ( > + IN CONST EFI_GRAPHICS_PIXEL_FORMAT UefiGfxPixelFormat, > + IN CONST UINT32 HRes, > + IN CONST UINT32 VRes > + ) > +{ > + UINT32 PixelFormat; > + > + // Disable the graphics layer before configuring any settings. > + LayerGraphicsDisable (); > + > + // Setup graphics layer size. > + MmioWrite32 (DP_BASE + DP_DE_LG_IN_SIZE, FRAME_IN_SIZE (HRes, VRes)); > + > + // Setup graphics layer composition size. > + MmioWrite32 (DP_BASE + DP_DE_LG_CMP_SIZE, FRAME_CMP_SIZE (HRes, VRes)); > + > + // Setup memory stride (total visible pixels on a line * 4). > + MmioWrite32 (DP_BASE + DP_DE_LG_H_STRIDE, (HRes * sizeof (UINT32))); > + > + // Set the format. > + > + // In PixelBlueGreenRedReserved8BitPerColor format, byte 0 represents blue, > + // byte 1 represents green, byte 2 represents red, and byte 3 is reserved > + // which is equivalent to XRGB format of the DP500/DP550/DP650. Whereas > + // PixelRedGreenBlueReserved8BitPerColor is equivalent to XBGR of the > + // DP500/DP550/DP650. > + if (UefiGfxPixelFormat == PixelBlueGreenRedReserved8BitPerColor) { > + PixelFormat = (mDpDeviceId == MALIDP_500) ? DP_PIXEL_FORMAT_DP500_XRGB_8888 > + : DP_PIXEL_FORMAT_XRGB_8888; > + } else { > + PixelFormat = (mDpDeviceId == MALIDP_500) ? DP_PIXEL_FORMAT_DP500_XBGR_8888 > + : DP_PIXEL_FORMAT_XBGR_8888; > + } > + > + MmioWrite32 (DP_BASE + DP_DE_LG_FORMAT, PixelFormat); > + > + // Enable graphics layer. > + LayerGraphicsEnable (); > +} > + > +/** Configure timing information of the display. > + > + @param[in] Horizontal Pointer to horizontal timing parameters. > + (Resolution, Sync, Back porch, Front porch) > + @param[in] Vertical Pointer to vertical timing parameters. > + (Resolution, Sync, Back porch, Front porch) > +**/ > +STATIC > +VOID > +SetDisplayEngineTiming ( > + IN CONST SCAN_TIMINGS * CONST Horizontal, > + IN CONST SCAN_TIMINGS * CONST Vertical > + ) > +{ > + UINTN RegHIntervals; > + UINTN RegVIntervals; > + UINTN RegSyncControl; > + UINTN RegHVActiveSize; > + > + if (mDpDeviceId == MALIDP_500) { > + // MALI DP500 timing registers. > + RegHIntervals = DP_BASE + DP_DE_DP500_H_INTERVALS; > + RegVIntervals = DP_BASE + DP_DE_DP500_V_INTERVALS; > + RegSyncControl = DP_BASE + DP_DE_DP500_SYNC_CONTROL; > + RegHVActiveSize = DP_BASE + DP_DE_DP500_HV_ACTIVESIZE; > + } else { > + // MALI DP550/DP650 timing registers. > + RegHIntervals = DP_BASE + DP_DE_H_INTERVALS; > + RegVIntervals = DP_BASE + DP_DE_V_INTERVALS; > + RegSyncControl = DP_BASE + DP_DE_SYNC_CONTROL; > + RegHVActiveSize = DP_BASE + DP_DE_HV_ACTIVESIZE; > + } > + > + // Horizontal back porch and front porch. > + MmioWrite32 ( > + RegHIntervals, > + H_INTERVALS (Horizontal->FrontPorch, Horizontal->BackPorch) > + ); > + > + // Vertical back porch and front porch. > + MmioWrite32 ( > + RegVIntervals, > + V_INTERVALS (Vertical->FrontPorch, Vertical->BackPorch) > + ); > + > + // Sync control, Horizontal and Vertical sync. > + MmioWrite32 ( > + RegSyncControl, > + SYNC_WIDTH (Horizontal->Sync, Vertical->Sync) > + ); > + > + // Set up Horizontal and Vertical area size. > + MmioWrite32 ( > + RegHVActiveSize, > + HV_ACTIVE (Horizontal->Resolution, Vertical->Resolution) > + ); > +} > + > +/** Return CORE_ID of the ARM Mali DP. > + > + @retval 0xFFF No Mali DP found. > + @retval 0x500 Mali DP core id for DP500. > + @retval 0x550 Mali DP core id for DP550. > + @retval 0x650 Mali DP core id for DP650. > +**/ > +STATIC > +UINT32 > +ArmMaliDpGetCoreId ( > + ) > +{ > + UINT32 DpCoreId; > + > + // First check for DP500 as register offset for DP550/DP650 CORE_ID > + // is beyond 3K/4K register space of the DP500. > + DpCoreId = MmioRead32 (DP_BASE + DP_DE_DP500_CORE_ID); > + DpCoreId >>= DP_DE_DP500_CORE_ID_SHIFT; > + > + if (DpCoreId == MALIDP_500) { > + return DpCoreId; > + } > + > + // Check for DP550 or DP650. > + DpCoreId = MmioRead32 (DP_BASE + DP_DC_CORE_ID); > + DpCoreId >>= DP_DC_CORE_ID_SHIFT; > + > + if (DpCoreId == MALIDP_550 > + || DpCoreId == MALIDP_650) { indentation looks funny here - could you move the || to the preceding line and align 'DpCoreId' please? > + return DpCoreId; > + } > + > + return MALIDP_NOT_PRESENT; > +} > + > +/** Check for presence of MALI. > + > + This function returns success if the platform implements > + DP500/DP550/DP650 ARM Mali display processor. > + > + @retval EFI_SUCCESS DP500/DP550/DP650 display processor found > + on the platform. > + @retval EFI_NOT_FOUND DP500/DP550/DP650 display processor not found > + on the platform. > +**/ > +EFI_STATUS > +LcdIdentify (VOID) > +{ > +#if (DP_BASE == 0) > +#error ARM Mali DP peripheral base address is invalid > +#endif > + > + DEBUG ((DEBUG_WARN, > + "Probing ARM Mali DP500/DP550/DP650 at base address 0x%p\n", > + DP_BASE > + )); > + > + if (mDpDeviceId == 0) { > + mDpDeviceId = ArmMaliDpGetCoreId (); > + } > + > + if (mDpDeviceId == MALIDP_NOT_PRESENT) { > + DEBUG ((DEBUG_WARN, "ARM Mali DP not found...\n")); > + return EFI_NOT_FOUND; > + } > + > + DEBUG ((DEBUG_WARN, "Found ARM Mali DP %x\n", mDpDeviceId)); > + return EFI_SUCCESS; > +} > + > +/** Initialize platform display. > + > + @param[in] FrameBaseAddress Address of the frame buffer. > + > + @retval EFI_SUCCESS Display initialization successful. > + @retval !(EFI_SUCCESS) Display initialization failure. > +**/ > +EFI_STATUS > +LcdInitialize ( > + IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress > + ) > +{ > + DEBUG ((DEBUG_WARN, "Frame buffer base address = %p\n", FrameBaseAddress)); > + > + if (mDpDeviceId == 0) { > + mDpDeviceId = ArmMaliDpGetCoreId (); > + } > + > + if (mDpDeviceId == MALIDP_NOT_PRESENT) { > + DEBUG ((DEBUG_ERROR, "ARM Mali DP initialization failed," > + "no ARM Mali DP present\n")); > + return EFI_NOT_FOUND; > + } > + > + // We are using graphics layer of the Mali DP as a main frame buffer. > + LayerGraphicsSetFrame (FrameBaseAddress); > + > + return EFI_SUCCESS; > +} > + > +/** Set ARM Mali DP in cofiguration mode. > + > + The ARM Mali DP must be in the configuration mode for > + configuration of the H_INTERVALS, V_INTERVALS, SYNC_CONTROL > + and HV_ACTIVESIZE. > +**/ > +STATIC > +VOID > +SetConfigurationMode (VOID) > +{ > + // Request configuration Mode. > + if (mDpDeviceId == MALIDP_500) { > + MmioOr32 (DP_BASE + DP_DE_DP500_CONTROL, DP_DE_DP500_CONTROL_CONFIG_REQ); > + } else { > + MmioOr32 (DP_BASE + DP_DC_CONTROL, DP_DC_CONTROL_CM_ACTIVE); > + } > +} > + > +/** Set ARM Mali DP in normal mode. > + > + Normal mode is the main operating mode of the display processor > + in which display layer data is fetched from frame buffer and > + displayed. > +**/ > +STATIC > +VOID > +SetNormalMode (VOID) > +{ > + // Disable configuration Mode. > + if (mDpDeviceId == MALIDP_500) { > + MmioAnd32 (DP_BASE + DP_DE_DP500_CONTROL, ~DP_DE_DP500_CONTROL_CONFIG_REQ); > + } else { > + MmioAnd32 (DP_BASE + DP_DC_CONTROL, ~DP_DC_CONTROL_CM_ACTIVE); > + } > +} > + > +/** Set the global configuration valid flag. > + > + Any new configuration parameters written to the display engine are not > + activated until the global configuration valid flag is set in the > + CONFIG_VALID register. > +**/ > +STATIC > +VOID > +SetConfigValid (VOID) > +{ > + if (mDpDeviceId == MALIDP_500) { > + MmioOr32 (DP_BASE + DP_DP500_CONFIG_VALID, DP_DC_CONFIG_VALID); > + } else { > + MmioOr32 (DP_BASE + DP_DC_CONFIG_VALID, DP_DC_CONFIG_VALID); > + } > +} > + > +/** Set requested mode of the display. > + > + @param[in] ModeNumber Display mode number. > + > + @retval EFI_SUCCESS Display mode set successful. > + @retval EFI_DEVICE_ERROR Display mode not found/supported. > +**/ > +EFI_STATUS > +LcdSetMode ( > + IN CONST UINT32 ModeNumber > + ) > +{ > + EFI_STATUS Status; > + CONST SCAN_TIMINGS *Horizontal; > + CONST SCAN_TIMINGS *Vertical; > + > + EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo; > + > + // Get the display mode timings and other relevant information. > + Status = LcdPlatformGetTimings ( > + ModeNumber, > + &Horizontal, > + &Vertical > + ); > + if (EFI_ERROR (Status)) { > + ASSERT_EFI_ERROR (Status); > + return Status; > + } > + > + ASSERT (Horizontal != NULL); > + ASSERT (Vertical != NULL); > + > + // Get the pixel format information. > + Status = LcdPlatformQueryMode (ModeNumber, &ModeInfo); > + if (EFI_ERROR (Status)) { > + ASSERT_EFI_ERROR (Status); > + return Status; > + } > + > + // Request configuration mode. > + SetConfigurationMode (); > + > + // Configure the graphics layer. > + LayerGraphicsConfig ( > + ModeInfo.PixelFormat, > + Horizontal->Resolution, > + Vertical->Resolution > + ); > + > + // Set the display engine timings. > + SetDisplayEngineTiming (Horizontal, Vertical); > + > + // After configuration, set Mali DP in normal mode. > + SetNormalMode (); > + > + // Any parameters written to the display engine are not activated until > + // CONFIG_VALID is set. > + SetConfigValid (); > + > + return EFI_SUCCESS; > +} > + > +/** This function de-initializes the display. > + > +**/ > +VOID > +LcdShutdown (VOID) > +{ > + // Disable graphics layer. > + LayerGraphicsDisable (); > +} > -- > Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") >