From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::241; helo=mail-io0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x241.google.com (mail-io0-x241.google.com [IPv6:2607:f8b0:4001:c06::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A54A021A10994 for ; Sun, 26 Nov 2017 02:25:48 -0800 (PST) Received: by mail-io0-x241.google.com with SMTP id u42so33366814ioi.9 for ; Sun, 26 Nov 2017 02:30:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=pMnAyOeuyUvuXQsNVsJIgIxtEhARyavf5oaYSgaI4b8=; b=YQLXt/kMa7nHthJRbwy08zIfd5946fU7P3bsY4NzMGQs//03iGCt1KeNOfC1rdJbzV +/UvJ9qfIi6gkKbCCBlnyQgcK88YCw54l5x3CdPdXAoEcTXlkh8tpDzW+9wb//qbvA2q Nk6EUQwRilVczKXxeHnNQw71sho+Enmnzkqls= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=pMnAyOeuyUvuXQsNVsJIgIxtEhARyavf5oaYSgaI4b8=; b=TA0rqK6mK6KNvgUv5t0adPKjZMEFe7ikxSCIxbWBBtJq9xmqUwfHbYj/0kvlRGzPJz ZQC2M5cukKG+nF28yIjlq/hRtbNXY9eizLI0D08jaE01R+TvCIFZYvSfBc8EuACP12+R 5hiwDvfKUEoeWlq/ingKyqzayuYAJPD7lwxq0opM5itmWcBI1lM74pgJXMhWKlL57fV6 UcFrZRchjkKOjzPwtwtmmeN7+45FI/NguALEOydtKFA1kPd8dQqe8L4t8z4naTypNWA2 wGIW+U7U41iL6PX3jMiPTCfjDXMjcwppeJrnkn5hy9pGEqfW0IP5zCihcrtm0Fh34D5V EccA== X-Gm-Message-State: AJaThX5LdGQbJGtjRv6vTSeVnJ4bfFvxv/prg9mbS0HB+Q8nArRgGmsO 661ZkhUbYMsHLdPNvY1Hk90J+UG9J9trjhz7kQz9CA== X-Google-Smtp-Source: AGs4zMahmD3O74LT27BUeVKxRb9w63fzWjUhr2L3gpOvx9vY6lWA+V5nLFWSEZL+KWUS2fln/Coo/02+N04x1kCLWks= X-Received: by 10.107.178.145 with SMTP id b139mr38104819iof.52.1511692207726; Sun, 26 Nov 2017 02:30:07 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.104.16 with HTTP; Sun, 26 Nov 2017 02:30:07 -0800 (PST) In-Reply-To: <20171125122333.d2uzog5aefjcudij@bivouac.eciton.net> References: <20171117190423.19511-1-ard.biesheuvel@linaro.org> <20171125122333.d2uzog5aefjcudij@bivouac.eciton.net> From: Ard Biesheuvel Date: Sun, 26 Nov 2017 10:30:07 +0000 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" , Daniel Thompson , =?UTF-8?B?UGlwYXQv44Oh44K/44Ov44OL44OD44OI44Od44OzIOODlOODkeODg+ODiA==?= , Masahisa Kojima , Masami Hiramatsu Subject: Re: [PATCH edk2-platforms v5 0/6] add remaining support for Socionext SynQuacer X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 26 Nov 2017 10:25:48 -0000 Content-Type: text/plain; charset="UTF-8" On 25 November 2017 at 12:23, Leif Lindholm wrote: > On Fri, Nov 17, 2017 at 07:04:17PM +0000, Ard Biesheuvel wrote: >> These are the remaining patches that still need review after the majority >> of the Socionext SynQuacer support patches were merged. > > All remaining patches in series: > Reviewed-by: Leif Lindholm Thanks. Patches 1 -5 pushed as 563c2efbfa05..89a256625016 Patch #6 depends on the SD/MMC override protocol which is still under discussion. > >> Changes since v4: >> - minor changes, please see the notes in the individual patches >> >> Changes since v3: >> - remove ACPI support for now, we can add it on top if we manage to sort >> out all the SoC quirks that make it difficult to have full support under >> ACPI >> - add RTC support to DeveloperBox >> - add eMMC support to SynQuacerEvalBoard >> - incorporate review feedback on the SPI NOR driver (which was possible >> after noticing that I did in fact have a manual for this IP) >> - map NOR and EEPROM as writeback cacheable non-shareable; this allows the >> split FV hack to be reverted, and improves boot time considerably >> - some other minor changes have been applied, these have been added to the >> individual patches as notes >> >> Changes since v2: >> - converted NETSEC driver to UEFI driver model >> - added a platform DXE driver that declares the non-discoverable NETSEC >> device for the UEFI driver model driver to bind to >> - remove hardcoded DRAM information - everything is now retrieved from >> ARM Trusted Firmware >> - added DT descriptions of the GPIO and interrupt controller IP blocks >> - addressed various style issues and merge errors highlighted by Leif >> >> Ard Biesheuvel (6): >> Silicon/SynQuacer: implement 'clear NVRAM' feature using a DIP switch >> Silicon/SynQuacer: add DT description of the SDHCI controller >> Silicon/Socionext: implement I2C master protocol for SynQuacer I2C >> Silicon/NXP: add RTC support library for PCF8563 I2C IP >> Platform/DeveloperBox: wire up RTC support >> Platform/SynQuacerEvalBoard: add eMMC driver stack >> >> Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 13 +- >> Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 6 + >> Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 12 + >> Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 8 + >> Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c | 402 +++++++++++++ >> Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec | 31 ++ >> Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf | 52 ++ >> Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 27 + >> Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts | 4 + >> Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 201 +++++++ >> Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 88 ++- >> Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 37 ++ >> Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 11 +- >> Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/ComponentName.c | 185 ++++++ >> Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/DriverBinding.c | 238 ++++++++ >> Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c | 588 ++++++++++++++++++++ >> Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.h | 162 ++++++ >> Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf | 59 ++ >> Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 8 + >> Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 4 + >> Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c | 30 +- >> Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf | 6 + >> Silicon/Socionext/SynQuacer/SynQuacer.dec | 8 + >> 23 files changed, 2160 insertions(+), 20 deletions(-) >> create mode 100644 Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c >> create mode 100644 Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec >> create mode 100644 Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf >> create mode 100644 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c >> create mode 100644 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h >> create mode 100644 Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/ComponentName.c >> create mode 100644 Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/DriverBinding.c >> create mode 100644 Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c >> create mode 100644 Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.h >> create mode 100644 Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf >> >> -- >> 2.11.0 >>