From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::243; helo=mail-io0-x243.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x243.google.com (mail-io0-x243.google.com [IPv6:2607:f8b0:4001:c06::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4D962207E5407 for ; Mon, 21 May 2018 02:29:32 -0700 (PDT) Received: by mail-io0-x243.google.com with SMTP id f21-v6so13552582iob.13 for ; Mon, 21 May 2018 02:29:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=0GLUpAgL47Tksd86/A+XaqsvAXEFpnsqNm6fJR/iK9c=; b=and7dL2PGkno8W8phFhFVYoeWrJZbSSe4fslKFnPAflKIx9SATRSMSYsm9zb5U/U9e oJzg22hrSsLME1Wn1Rp1pot8WrnrQwhA2UN6mIx5HI1pexCQ4X0Ub+RNk7ChA15msRKQ bo+UKeyUOSgterXHGml7/HPUk4Zesx3v8fmpo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=0GLUpAgL47Tksd86/A+XaqsvAXEFpnsqNm6fJR/iK9c=; b=S3jHaKULYnGr2KEpk96NHj+6ePLcYDFozZgDhvR6oNpTH1TiDzM3qRaWe2OwTtudpY X7okvzHCLNUh1XW0pXWJ/tp8hQLnyshrUz7mqcXznHLHek5M2/E86oO9OeNQjIx7m0WS sqzKkBJunCxFENu2apQwU4F4s+JkD9FKyPIozq+wARre0MZp04ePk5Zx30qqyxJxgSEX j7RpBsnTRdz74qvXld4jSqK6zKuFkD8Dulg6K4zAEqkmhOtP16GpkJ4A4uahsNZ60VeK IGPHjReEZM0dk5mikJUVSdu/VDuZkrHj/Q8NcdATHjL6B6tqaKZ/C63uT0Oq1mWkSMmz g6uw== X-Gm-Message-State: ALKqPwd8dEbV7Ol5HmbMBdak7xBsm+HY9HSj4tpCCtIudI1NudvYJtVI qdC+AQc8McIhMONmWNw+qq87Y2psypZvdOv2jt/CVlew2q4= X-Google-Smtp-Source: AB8JxZond2GLLJsDjca0nAnJBm53Y+FeiUqQWH2+rrm5pECx8sHdeIa+5tQU2VX9QAwexd+niA1mPkglRKCkANG3fII= X-Received: by 2002:a6b:4014:: with SMTP id k20-v6mr7330027ioa.277.1526894971438; Mon, 21 May 2018 02:29:31 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.187.134 with HTTP; Mon, 21 May 2018 02:29:31 -0700 (PDT) In-Reply-To: <1526891152-18739-10-git-send-email-thomas.abraham@arm.com> References: <1526891152-18739-1-git-send-email-thomas.abraham@arm.com> <1526891152-18739-10-git-send-email-thomas.abraham@arm.com> From: Ard Biesheuvel Date: Mon, 21 May 2018 11:29:31 +0200 Message-ID: To: Thomas Abraham Cc: "edk2-devel@lists.01.org" , Leif Lindholm Subject: Re: [PATCH edk2-platforms v4 9/9] Platform/ARM/Sgi: Add Ssdt, Iort and Mcfg tables X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 21 May 2018 09:29:32 -0000 Content-Type: text/plain; charset="UTF-8" On 21 May 2018 at 10:25, Thomas Abraham wrote: > SGI platforms support a AHCI controller which is attached to a PCIe > root complex and it can generate PCIe ITS-MSI transactions. So the > Ssdt, Iort and Mcfg ACPI tables to desribe this topology to the > linux kernel. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Thomas Abraham > --- > .../ARM/SgiPkg/AcpiTables/Sgi575/AcpiTables.inf | 5 + > Platform/ARM/SgiPkg/AcpiTables/Sgi575/Iort.aslc | 106 +++++++++++++++++++++ > Platform/ARM/SgiPkg/AcpiTables/Sgi575/Mcfg.aslc | 59 ++++++++++++ > Platform/ARM/SgiPkg/AcpiTables/Sgi575/Ssdt.asl | 91 ++++++++++++++++++ > 4 files changed, 261 insertions(+) > create mode 100644 Platform/ARM/SgiPkg/AcpiTables/Sgi575/Iort.aslc > create mode 100644 Platform/ARM/SgiPkg/AcpiTables/Sgi575/Mcfg.aslc > create mode 100644 Platform/ARM/SgiPkg/AcpiTables/Sgi575/Ssdt.asl > > diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/AcpiTables.inf > index 2c9bd98..485f819 100644 > --- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/AcpiTables.inf > +++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/AcpiTables.inf > @@ -25,8 +25,11 @@ > Dsdt.asl > Fadt.aslc > Gtdt.aslc > + Iort.aslc > Madt.aslc > + Mcfg.aslc > Spcr.aslc > + Ssdt.asl > > [Packages] > ArmPkg/ArmPkg.dec > @@ -51,3 +54,5 @@ > gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase > gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase > gArmPlatformTokenSpaceGuid.PL011UartInterrupt > + > + gArmSgiTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress > diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Iort.aslc b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Iort.aslc > new file mode 100644 > index 0000000..f3b3105 > --- /dev/null > +++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Iort.aslc > @@ -0,0 +1,106 @@ > +/** @file > +* I/O Remapping Table (Iort) > +* > +* Copyright (c) 2018, ARM Ltd. All rights reserved. > +* > +* This program and the accompanying materials are licensed and made available > +* under the terms and conditions of the BSD License which accompanies this > +* distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +#include > +#include > +#include > +#include "SgiAcpiHeader.h" > + > +#pragma pack(1) > + > +typedef struct > +{ > + EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE ItsNode; > + UINT32 ItsIdentifiers; > +} ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE; > + > +typedef struct > +{ > + EFI_ACPI_6_0_IO_REMAPPING_RC_NODE RcNode; > + EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE RcIdMap; > +} ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE; > + > +typedef struct > +{ > + EFI_ACPI_6_0_IO_REMAPPING_TABLE Header; > + ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE ItsNode; > + ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE RcNode; > +} ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE; > + > +#pragma pack () > + > +ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort = > +{ > + // EFI_ACPI_6_0_IO_REMAPPING_TABLE > + { > + ARM_ACPI_HEADER // EFI_ACPI_DESCRIPTION_HEADER > + ( > + EFI_ACPI_6_0_IO_REMAPPING_TABLE_SIGNATURE, > + ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, > + EFI_ACPI_IO_REMAPPING_TABLE_REVISION > + ), > + 2, // NumNodes > + sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE), // NodeOffset > + 0, // Reserved > + }, > + // ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE > + { > + // EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE > + { > + // EFI_ACPI_6_0_IO_REMAPPING_NODE > + { > + EFI_ACPI_IORT_TYPE_ITS_GROUP, // Type > + sizeof (ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE), // Length > + 0, // Revision > + 0, // Reserved > + 0, // NumIdMappings > + 0, // IdReference > + }, > + 1, // GIC ITS Identifiers > + }, > + 0, > + }, > + // ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE > + { > + // EFI_ACPI_6_0_IO_REMAPPING_RC_NODE > + { > + // EFI_ACPI_6_0_IO_REMAPPING_NODE > + { > + EFI_ACPI_IORT_TYPE_ROOT_COMPLEX, // Type > + sizeof (ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE), // Length > + 0, // Revision > + 0, // Reserved > + 1, // NumIdMappings > + __builtin_offsetof (ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE, RcIdMap), // IdReference > + }, > + 1, // CacheCoherent > + 0, // AllocationHints > + 0, // Reserved > + 0, // MemoryAccessFlags > + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, // AtsAttribute > + 0x0, // PciSegmentNumber > + }, > + // EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE > + { > + 0x0038, // InputBase > + 0x0001, // NumIds > + 0x0038, // OutputBase This looks slightly dodgy to me. NumIds is zero based, so you are mapping device IDs 0x38 and 0x39 only. Is that what you intended? It is best to identity remap the entire RID range, even if the virtual AHCI is the only one that ever uses it. Alternatively, you can create a EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE mapping for the particular device ID that the AHCI uses. > + __builtin_offsetof (ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, ItsNode), // OutputReference > + 0, // Flags > + } > + } > +}; > + > +VOID* CONST ReferenceAcpiTable = &Iort; > diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Mcfg.aslc b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Mcfg.aslc > new file mode 100644 > index 0000000..22a1018 > --- /dev/null > +++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Mcfg.aslc > @@ -0,0 +1,59 @@ > +/** @file > +* Memory mapped configuration space base address description table (MCFG) > +* > +* Copyright (c) 2018, ARM Ltd. All rights reserved. > +* > +* This program and the accompanying materials are licensed and made available > +* under the terms and conditions of the BSD License which accompanies this > +* distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +#include > +#include > +#include > +#include "SgiAcpiHeader.h" > +#include "SgiPlatform.h" > + > +#include > +#include > +#include > + > +#pragma pack(1) > +typedef struct > +{ > + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header; > + EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE Structure[1]; > +} EFI_ACPI_PCI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE; > +#pragma pack() > + > +EFI_ACPI_PCI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE Mcfg = { > + { > + ARM_ACPI_HEADER ( > + EFI_ACPI_6_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE, > + EFI_ACPI_PCI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_DESCRIPTION_TABLE, > + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION > + ), > + EFI_ACPI_RESERVED_QWORD, //Reserved > + }, > + { > + // PCIe ECAM > + { > + FixedPcdGet32 (PcdPciConfigurationSpaceBaseAddress), // Base Address > + 0x0, // Segment Group Number > + 0x0, // Start Bus Number > + 0xff, // End Bus Number Please use the BusMin and BusMax PCDs here. > + 0x00000000, // Reserved > + } > + } > +}; > + > +// > +// Reference the table being generated to prevent the optimizer from removing the > +// data structure from the executable > +// > +VOID* CONST ReferenceAcpiTable = &Mcfg; > diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Ssdt.asl b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Ssdt.asl > new file mode 100644 > index 0000000..bd418c7 > --- /dev/null > +++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Ssdt.asl > @@ -0,0 +1,91 @@ > +/** @file > +* Secondary System Description Table (SSDT) > +* > +* Copyright (c) 2018, ARM Limited. All rights reserved. > +* > +* This program and the accompanying materials are licensed and made available > +* under the terms and conditions of the BSD License which accompanies this > +* distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +#include "SgiAcpiHeader.h" > + > +DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-SGI575", > + EFI_ACPI_ARM_OEM_REVISION) > +{ > + Scope (_SB) { > + // PCI Root Complex > + Device(PCI0) { > + Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge > + Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge > + Name (_SEG, Zero) // PCI Segment Group number > + Name (_BBN, Zero) // PCI Base Bus Number > + Name (_CCA, 1) // Cache Coherency Attribute > + Does this RC not support legacy INTx interrupts? > + // Root complex resources > + Method (_CRS, 0, Serialized) { > + Name (RBUF, ResourceTemplate () { > + WordBusNumber ( // Bus numbers assigned to this root > + ResourceProducer, > + MinFixed, > + MaxFixed, > + PosDecode, > + 0, // AddressGranularity > + 0, // AddressMinimum - Minimum Bus Number > + 255, // AddressMaximum - Maximum Bus Number > + 0, // AddressTranslation - Set to 0 > + 256 // RangeLength - Number of Busses > + ) > + > + DWordMemory ( // 32-bit BAR Windows > + ResourceProducer, > + PosDecode, > + MinFixed, > + MaxFixed, > + Cacheable, > + ReadWrite, > + 0x00000000, // Granularity > + 0x70000000, // Min Base Address > + 0x777FFFFF, // Max Base Address > + 0x00000000, // Translate > + 0x07800000 // Length > + ) > + > + QWordMemory ( // 64-bit BAR Windows > + ResourceProducer, > + PosDecode, > + MinFixed, > + MaxFixed, > + Cacheable, > + ReadWrite, > + 0x00000000, // Granularity > + 0x500000000, // Min Base Address > + 0x7FFFFFFFF, // Max Base Address > + 0x00000000, // Translate > + 0x300000000 // Length > + ) > + > + DWordIo ( // IO window > + ResourceProducer, > + MinFixed, > + MaxFixed, > + PosDecode, > + EntireRange, > + 0x00000000, // Granularity > + 0x00000000, // Min Base Address > + 0x007FFFFF, // Max Base Address > + 0x77800000, // Translate > + 0x00800000 // Length You need to set the TypeTranslation attribute here. > + ) > + }) // Name(RBUF) > + > + Return (RBUF) > + } // Method (_CRS) > + } > + } > +} > -- > 2.7.4 >