From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::22a; helo=mail-io0-x22a.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x22a.google.com (mail-io0-x22a.google.com [IPv6:2607:f8b0:4001:c06::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F3D12202E5E71 for ; Thu, 9 Nov 2017 13:05:43 -0800 (PST) Received: by mail-io0-x22a.google.com with SMTP id n137so11356013iod.6 for ; Thu, 09 Nov 2017 13:09:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=JMrn8uhBZYkwJ1QBxDFTyNB/TBZ0NCcI3QGDOg8mQF0=; b=PewVujZJoAcExGFiEFETMLHIniJ3K6gb3wTpZl4n3kupRgPUfpEVkJIqP6wrhHc3OG Qt/N6vs84AfTHD57JXv4WUQ3/YM5//835+1H25Y5wszMRv03fJMH8nF8ykddTTpaw1R/ G6T5mUzlk/IgTr8HpktdG+3YuuWCCmRIuzeUc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=JMrn8uhBZYkwJ1QBxDFTyNB/TBZ0NCcI3QGDOg8mQF0=; b=dQFCv3h9baGUgW0S6ZuEjtKgEvaIc5Yb/UIpFFa1fBA9o1zLKkjynSjn/5S83LHVNu QWsg4oxLCJtbleqlfMcDxGJ/LdkL1wEOPuEZDBpVh+eWQC8mNPOxMwHCaVD8QhDr10Xp zsMnuzXdMW6wMJ0B3UL76lyCshiBZ/3kIO4VrpWWO1LC/aRb6AJYeiUoei8Ab5LZjUbx /X5pBl/VUU2hlGsDGWiffZb7Q8/1P/rWgJhrKIx7DplksFxcsRT70VA12mmTA8NAwvB/ YEVjdDBWsJVBKgXowuRcuDbd2M96G3MiKnQiRwpPGROQjAf0HSgnlwMAh78WzIGUKruR 41Yw== X-Gm-Message-State: AJaThX6XZR4MmRFPGB4Q4yd+2Pax9OVMgOMMoruD3HFKwClxfJCInTeE 0ELH3fsLS+zo7Hbo6HMSl9YBXXVQZ84ep96FXQ0KrA== X-Google-Smtp-Source: ABhQp+QtfAPIoVzz5TH1NXPxq7TiGvgEb3VABmB84T8/W2TZqc5lUdT4fNT/zSisoIdQFlp9yfm8v33cwspKoyPQUlk= X-Received: by 10.107.151.19 with SMTP id z19mr2298246iod.248.1510261785005; Thu, 09 Nov 2017 13:09:45 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.131.167 with HTTP; Thu, 9 Nov 2017 13:09:44 -0800 (PST) In-Reply-To: <20171108161246.2c7ppy562fpizjcd@bivouac.eciton.net> References: <20171103113352.8604-1-ard.biesheuvel@linaro.org> <20171105055245.xbicmlagfeu7xt2o@bivouac.eciton.net> <20171108161246.2c7ppy562fpizjcd@bivouac.eciton.net> From: Ard Biesheuvel Date: Thu, 9 Nov 2017 21:09:44 +0000 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" , Laszlo Ersek , "Gao, Liming" Subject: Re: [PATCH v2] ArmPlatformPkg/PrePeiCore: seed temporary stack before entering PEI core X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 09 Nov 2017 21:05:44 -0000 Content-Type: text/plain; charset="UTF-8" On 8 November 2017 at 16:12, Leif Lindholm wrote: > On Sun, Nov 05, 2017 at 04:29:15PM +0000, Ard Biesheuvel wrote: >> >> OK, this may sound completely unreasonable, but seeing those >> >> implementations overwrite callee-saved registers without saving them >> >> makes my brain unhappy. (Yes, I know.) >> >> >> >> Could they either: >> >> - Have a comment prepended establishing the implicit ABI of which >> >> registers the caller cannot rely on reusing after return. >> >> Preferably somewhat echoed at the call site. >> >> - Be rewritten to use only scratch registers? >> >> >> > >> > I think it is implied that the startup code does not adhere to the >> > AAPCS. That code already uses r5 and r6 without stacking them, simply >> > because we're in the middle of preparing the stack and other execution >> > context, precisely so the C code we call into can rely on AAPCS >> > guarantees. >> >> Ehm, hold on, what do you mean by 'call site'? This code just runs and >> jumps back to a local label. There are no functions calls here until >> the point where we call into C (with the exception of the lovely >> ArmPlatformPeiBootAction() we added so Juno can find out how much DRAM >> it can use) > > Yeah, you're right, I was misreading the block as a subroutine. > > Seems the only register that must be preserved across jumps is r5/x5, > and neither of these modifications touch those (or change that fact). > > Reviewed-by: Leif Lindholm > Thanks. Pushed as 7e2a8dfe8a9a