From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-it0-x232.google.com (mail-it0-x232.google.com [IPv6:2607:f8b0:4001:c0b::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BF5F11A1EBD for ; Thu, 22 Sep 2016 08:23:22 -0700 (PDT) Received: by mail-it0-x232.google.com with SMTP id n143so84899244ita.1 for ; Thu, 22 Sep 2016 08:23:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=f6UWxnGmMdSZQAn+EclRAyLyW0cPktxmpc3qSj3JyHQ=; b=k1xGFk6tfnjGqumda4OHcDsfzP8NhbZl0N2hXLxvuBGyn3yVxJfZFA5gKz4Kuxw8n8 2UEuhhKCOZgIvQx6LdKtpAIWb9zouNV/aWw/myrOKWj55Fjbx1rPJHWzJnl0GMVMlU86 qZ3tuaSJvBC9ikTx8y6dWo45gkfZC3MmW0Ls8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=f6UWxnGmMdSZQAn+EclRAyLyW0cPktxmpc3qSj3JyHQ=; b=bmqDUKZ2Jb2GB0JKtlzoG6Z4ZcRXeQ3bm/ntNChSKFbuEW+zRB/aEpu735PkpFdtLn dTzIRBqMgZ6zXUVUCg0DTDZ7grYM7wq2pmD6MVj3Ju/+GmX7TO+iGuRxei9caqzeoEoX /TJSJZ2MKnvJm+wyxeyqM3Cbmr9ocUWckcP7RsueUH1/FwhNy2SqQ1cF5KoeNn4g4o+P gVB1dtlW6wdPTbeG3CM+wyDPtPaZACPlewPx/vnMT8x10oAaB6E954o8KvMgPRySFT17 twqLjOnVb0fRkhP+HKedIQ7KVIeimLKvY6wkfM3oYXgctIN0xKc860IJi4IP56C/E79J T6Xg== X-Gm-Message-State: AE9vXwMjEAtErJYtBNRKawQfzSimplLTNXuqRgT+MyYAV9COcyc7NCB0GlTR6+aZHFDA0YL3VeuXOYmQL4/zajsg X-Received: by 10.36.209.196 with SMTP id w187mr3358683itg.47.1474557801986; Thu, 22 Sep 2016 08:23:21 -0700 (PDT) MIME-Version: 1.0 Received: by 10.36.204.195 with HTTP; Thu, 22 Sep 2016 08:23:21 -0700 (PDT) In-Reply-To: References: From: Ard Biesheuvel Date: Thu, 22 Sep 2016 16:23:21 +0100 Message-ID: To: valerij zaporogeci Cc: edk2-devel Subject: Re: flat mapping vs identity mapping on ARM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 22 Sep 2016 15:23:23 -0000 Content-Type: text/plain; charset=UTF-8 On 22 September 2016 at 16:22, Ard Biesheuvel wrote: > On 22 September 2016 at 16:19, valerij zaporogeci wrote: >> 2016-09-22 18:03 GMT+03:00, Ard Biesheuvel : >>> On 22 September 2016 at 15:30, valerij zaporogeci >>> wrote: >>>> In the ARM architecture, there is such a thing - "flat mapping", where >>>> MMU stage 1 is disabled and the mapping done is 1:1 and attributes set >>>> to the predefined values. >>> >>> What do you mean by 'attributes set to the predefined values' ? >>> >> >> I meant what is written in the section B3.2.1, short quote: >> "For all other accesses, when a stage 1 MMU is disabled, the assigned >> attributes depend on whether >> the access is a data access or an instruction access, as follows: >> Data access >> The stage 1 translation assigns the Strongly-Ordered memory type" >> >> ... and then, more lengthy description for instruction access. >> >> > > Yes, so what this means is that all data accesses are strongly > ordered, and instruction fetches are cacheable. > > So while you can enable both the data and the instruction cache with > the MMU off, only the instruction cache is actually functional, since > all data accesses or non-cacheable *are* non-cacheable