From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::d42; helo=mail-io1-xd42.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io1-xd42.google.com (mail-io1-xd42.google.com [IPv6:2607:f8b0:4864:20::d42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2B7692118FF23 for ; Thu, 15 Nov 2018 04:37:18 -0800 (PST) Received: by mail-io1-xd42.google.com with SMTP id h19-v6so14294585iog.9 for ; Thu, 15 Nov 2018 04:37:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=5juFkQdB+qyR+3Yts8Miq7xdaNFVAwytbuRiVFYbnBI=; b=dlaBBKTBvPKdnKIG95pesTxNSIiYBqAsHjyLkIj6n+DjmlDZeh7Zf0HKbX3p///H4A Vj6xNW3Imjc+AYDT8cuB0hFpbNRrZhUtwdRThy63E5WuXajCXBl4toAaA6NlpxE0dhoj 527AJVVUHRL7EmIw1jdPm/XbLduwK7uY65+34= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=5juFkQdB+qyR+3Yts8Miq7xdaNFVAwytbuRiVFYbnBI=; b=k0vVwMZeHFtvrf/sHjxTz+sb2GgGbA8gnT+fHodWWhMexGtMRWwG2K6/FOdKnRLh00 ahp+nzMZVs8j5kVh2G52r4zNJ/PIiKlYAWUWapeGRjkeaExk03PeG2C1AyFK0Ddx1IV7 hj1Dt9ETuu2mCM7pg6oH0jcTvqnujjkpscMN3L+U6APy6dMCoMusJ8uyfEJxODey9Q6A odZI+Oz9IuhgKxCNOreQRc7GDDob0aUosb3fuRYawCcVWBtXcA9N73AKqEUf0+o9RiOG bhUOxafVk9PKq29RFN/4nYbc5U+uuUI/PUrGKitlSiKgziHZcbJ3HqN2Mcr0KxNIzLwL AUNg== X-Gm-Message-State: AA+aEWYJhssVYq3cmpAN3mAq3hStGzjCIBrnV4PqqGJRQcz+RHpt0YSL acivdJKI+MxQjSihMDncEITyY4eryOxh5//FM36MZA== X-Google-Smtp-Source: AJdET5f6zIDEBa+sAGoVuqvDzWip8VoQMgmQ5l/mC8pdgQTp/LiAzq4fT81Ekoi8PrfP9vIehBt5SjfoexPRf5CmvIg= X-Received: by 2002:a6b:5d01:: with SMTP id r1mr4611580iob.170.1542285437582; Thu, 15 Nov 2018 04:37:17 -0800 (PST) MIME-Version: 1.0 References: <20181114192724.27068-1-ard.biesheuvel@linaro.org> <20181114200036.o5nv5qnkwlmbkwxu@bivouac.eciton.net> In-Reply-To: From: Ard Biesheuvel Date: Thu, 15 Nov 2018 04:37:06 -0800 Message-ID: To: Laszlo Ersek Cc: Leif Lindholm , "edk2-devel@lists.01.org" Subject: Re: [PATCH] ArmPkg/ArmGicDxe ARM: fix encoding for GICv3 interrupt acknowledge X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Nov 2018 12:37:19 -0000 Content-Type: text/plain; charset="UTF-8" On Wed, 14 Nov 2018 at 14:11, Laszlo Ersek wrote: > > On 11/14/18 21:00, Leif Lindholm wrote: > > On Wed, Nov 14, 2018 at 11:27:24AM -0800, Ard Biesheuvel wrote: > >> Fix a typo in the 32-bit ARM version of the GICv3 driver, which uses > >> the wrong system register encoding to access ICC_IAR1, and attempted > >> to access ICC_IAR0 instead. This results in boot time hangs both > >> under QEMU emulation and on real hardware. > >> > >> Contributed-under: TianoCore Contribution Agreement 1.1 > >> Signed-off-by: Ard Biesheuvel > > > > Reviewed-by: Leif Lindholm > > > > I would say given how long we've gone without finding this, > > Right, that makes me curious -- what has changed now? What exposed this bug? > I was regression testing a EFI workaround I put in the kernel for GICv3, which was apparently the first time anyone tried running EDK2/ARM on a GICv3 system (which is one of the reasons I wanted to get you one of the Socionext SynQuacer boards: it has a GICv3 with GICv2 compatibility and support for 32-bit guests, but sadly, we still don't have any with fixed silicon)