From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::d2f; helo=mail-io1-xd2f.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io1-xd2f.google.com (mail-io1-xd2f.google.com [IPv6:2607:f8b0:4864:20::d2f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EE51221962301 for ; Tue, 25 Sep 2018 08:51:56 -0700 (PDT) Received: by mail-io1-xd2f.google.com with SMTP id v14-v6so20861930iob.4 for ; Tue, 25 Sep 2018 08:51:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=U9kwUMorhQJBRY++oNnZmjvIXCoHXZ1IsbWPIP6VR7o=; b=CmprrmQ5QcFGD4gRtt07CPh+W68skWCLprRGV6yNu19VtmIckBuzPIIHaFkD/eqV0n lNtDjZu0WXyN6e1tAxQOLfK4NXdDSI7BQSzXQSZj2VMKyJzViyYigPzqlCaJz1Iqtqbf tGlK/oSoqxLWmYOD/uBhnOuUSrVfYCPGqdu54= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=U9kwUMorhQJBRY++oNnZmjvIXCoHXZ1IsbWPIP6VR7o=; b=MJSXBOrrlA9q4SgxE/v7p3okhDzL0Ldgx+Rr4TMH4urBU6m9zfU4ExJYkgykG+h5j2 dePACn3Ysqi3NPbl6OP/NmfdmV8qmlT8FqEqqq8i6g9V59LdnOW1+I0HgtiM1lcMbt1C bi8edj9NVY46NK9cVGgS5YqLphaNiIs7oo5AXgrUTjsSX5VkmIxD4IreOLxWCNZ6SDX0 MFHnIgcCVGP/8tdvi3PboO//WFckR7lGUNLHB+8kTzewv/VpOFXcRUajM3Aak+Zvs6gr kfQJAWL3ETH212fEHD0LUw5mnmKVtkD4fl4CnuzLRD9Q4mAei69ZSAdIU5qThmqJ/7kn MlFQ== X-Gm-Message-State: ABuFfohrjVzKlBBdFgJlp25SHYm5MdOjpzpVp0u0NSec83r+GLR8hams SK+ywdBIfDAgneVM6MOpipo/1oQGPr+fvAZqusLV6w== X-Google-Smtp-Source: ACcGV61Kz+tJT2c1HVXCzmcgsWh68MZQuLNOHAhdCWt/r1cA9S2oyRuvPMNcdzKzYqRcFPJkBBmb9Bm9LzEIzVuw1Rk= X-Received: by 2002:a6b:be83:: with SMTP id o125-v6mr1446352iof.173.1537890715571; Tue, 25 Sep 2018 08:51:55 -0700 (PDT) MIME-Version: 1.0 References: <1536631417-39920-1-git-send-email-star.zeng@intel.com> <734D49CCEBEEF84792F5B80ED585239D5BE028B7@SHSMSX104.ccr.corp.intel.com> In-Reply-To: From: Ard Biesheuvel Date: Tue, 25 Sep 2018 17:51:38 +0200 Message-ID: To: Marcin Wojtas Cc: "Zeng, Star" , "edk2-devel@lists.01.org" , Ruiyu Ni , fei1.wang@intel.com, Grzegorz Jaszczyk , Nadav Haklai Subject: Re: [PATCH] MdeModulePkg XhciDxe: Set HSEE Bit if SERR# Enable Bit is set X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Sep 2018 15:51:57 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 25 Sep 2018 at 17:41, Marcin Wojtas wrote: > > Hi Star, Ard > > With this patch, my platforms which use NonDiscoverableDevices layer > for supporting generic Xhci controller, fail in a strange way: > "Synchronous Exception at 0x000000003F910AFC > PC 0x00003F910AFC (0x00003F908000+0x00008AFC) [ 0] DxeCore.dll > PC 0x00003F910AE0 (0x00003F908000+0x00008AE0) [ 0] DxeCore.dll > PC 0x00003F91BDF4 (0x00003F908000+0x00013DF4) [ 0] DxeCore.dll > PC 0x0000BF5BD000 (0x0000BF5AF000+0x0000E000) [ 1] XhciDxe.dll > PC 0xAFAFAFAFAFAFAFAF > > Recursive exception occurred while dumping the CPU state" > > I've quickly checked and although XhcSetHsee() is eventually called > from XhcDriverBindingStart() sequence, > below line is not even executed: > XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_HSEE); > The XhcDriverBindingStart() returns EFI_SUCCESS and we get the sync > abort right afterwards (haven't found exact place yet). > FYI I am seeing something similar with a Renesas uPD70201. > What makes the difference is commenting out in XhcSetHsee(): > // Status =3D PciIo->Pci.Read ( > // PciIo, > // EfiPciIoWidthUint16, > // PCI_COMMAND_OFFSET, > // sizeof (XhciCmd), > // &XhciCmd > // ); > > With that everything keeps working as usual. I'd appreciate any hint. > > Best regards. > Marcin > > wt., 11 wrz 2018 o 04:30 Ni, Ruiyu napisa=C5=82(a): > > > > Reviewed-by: Ruiyu Ni > > > > Thanks/Ray > > > > > -----Original Message----- > > > From: Zeng, Star > > > Sent: Tuesday, September 11, 2018 10:04 AM > > > To: edk2-devel@lists.01.org > > > Cc: Zeng, Star ; Ni, Ruiyu ;= Wang, > > > Jian J ; Wang, Fei1 > > > Subject: [PATCH] MdeModulePkg XhciDxe: Set HSEE Bit if SERR# Enable B= it is > > > set > > > > > > When the HSEE in the USBCMD bit is a '1' and the HSE bit in the USBST= S > > > register is a '1', the xHC shall assert out-of-band error signaling t= o the host > > > and assert the SERR# pin. > > > To prevent masking any potential issues with SERR, this patch is to s= et > > > USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR# Enable Bit = is > > > set. > > > > > > Cc: Ruiyu Ni > > > Cc: Jian J Wang > > > Cc: Fei1 Wang > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > > Signed-off-by: Star Zeng > > > --- > > > MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c | 41 > > > ++++++++++++++++++++++++++++++++++ > > > 1 file changed, 41 insertions(+) > > > > > > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c > > > b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c > > > index 5f0736a516b6..89f073e1d83f 100644 > > > --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c > > > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c > > > @@ -587,6 +587,39 @@ XhcIsSysError ( > > > } > > > > > > /** > > > + Set USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR# Enab= le > > > Bit is set. > > > + > > > + The USBCMD HSEE Bit will be reset to default 0 by USBCMD Host Cont= roller > > > Reset(HCRST). > > > + This function is to set USBCMD HSEE Bit if PCICMD SERR# Enable Bit= is set. > > > + > > > + @param Xhc The XHCI Instance. > > > + > > > +**/ > > > +VOID > > > +XhcSetHsee ( > > > + IN USB_XHCI_INSTANCE *Xhc > > > + ) > > > +{ > > > + EFI_STATUS Status; > > > + EFI_PCI_IO_PROTOCOL *PciIo; > > > + UINT16 XhciCmd; > > > + > > > + PciIo =3D Xhc->PciIo; > > > + Status =3D PciIo->Pci.Read ( > > > + PciIo, > > > + EfiPciIoWidthUint16, > > > + PCI_COMMAND_OFFSET, > > > + sizeof (XhciCmd), > > > + &XhciCmd > > > + ); > > > + if (!EFI_ERROR (Status)) { > > > + if ((XhciCmd & EFI_PCI_COMMAND_SERR) !=3D 0) { > > > + XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_HSEE); > > > + } > > > + } > > > +} > > > + > > > +/** > > > Reset the XHCI host controller. > > > > > > @param Xhc The XHCI Instance. > > > @@ -628,6 +661,14 @@ XhcResetHC ( > > > // > > > gBS->Stall (XHC_1_MILLISECOND); > > > Status =3D XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, > > > XHC_USBCMD_RESET, FALSE, Timeout); > > > + > > > + if (!EFI_ERROR (Status)) { > > > + // > > > + // The USBCMD HSEE Bit will be reset to default 0 by USBCMD HC= RST. > > > + // Set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set. > > > + // > > > + XhcSetHsee (Xhc); > > > + } > > > } > > > > > > return Status; > > > -- > > > 2.7.0.windows.1 > > > > _______________________________________________ > > edk2-devel mailing list > > edk2-devel@lists.01.org > > https://lists.01.org/mailman/listinfo/edk2-devel