From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::242; helo=mail-io0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x242.google.com (mail-io0-x242.google.com [IPv6:2607:f8b0:4001:c06::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 661472242384E for ; Thu, 1 Mar 2018 00:22:52 -0800 (PST) Received: by mail-io0-x242.google.com with SMTP id l12so6247979ioc.10 for ; Thu, 01 Mar 2018 00:29:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=rQxhcJRownoRmnH+gp/FqRDPiddPBlDrw+o0Ndn4q7M=; b=iC0NyddwNNeU/Dy2DmcrDwwhHSu05KX1oLqJZCfr+Eqqwl1h+n0uNhG9pMwqSr/QDW DVeTixa43L7lowPWYEX5dwk3b6hVfU9Pl8IC3lqynYysH3ycUOQXEloqIQ449JkJLY+f +poq0WaQZSpvX/Hr9oSKcXoGjILulTBoMU6B0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=rQxhcJRownoRmnH+gp/FqRDPiddPBlDrw+o0Ndn4q7M=; b=Juk8LjN9b0RMGIvnrhlf1Wr3Bt3zR324lKU/z2uvDthvQ4FJzDhPCIlnJTHqEMCQqc 06ks2e/duygZRWnQH3BcbkH9KzD/z5zpumwxU3bvW3D0MLV2ZMzTLufu9+DBKL2ZdBou +O1S5T+ppR8mtmXmWsPw9nae7CNZPca8NzandG+rxhqV1sru0oxg1rl9QDJ2ArZcZGz9 TxVFMs7AlGy3NgPWVJCmW9Nd89jrvFke8/20OsW9vF7g8Ada/0NLpqPhRuhZC75iPwtQ sVYLPxRp3BfdO2cxl/NDFX4KSQzhOa8YeW8y6OGqczbq5cs+mxdvPfPrKZEDSBce7P3X +Qdw== X-Gm-Message-State: AElRT7EHOGE9gOvrago2X0yCrxTME/KHgGCR9zmYo9oBOBXpE8OsUkNS PbyvoIGvPJLcpw89g+gv0oE2RsCh5rGnG5ensDZu0g== X-Google-Smtp-Source: AG47ELvt/V8G/U6AZV1ZYhfvlVO9f9z3D/klxcyGGPamNZihlqmkCNm1uSwu7Ibez+VCI+ftfeJzDfBItY7hHnNsE1A= X-Received: by 10.107.56.69 with SMTP id f66mr49163ioa.170.1519892939417; Thu, 01 Mar 2018 00:28:59 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.138.209 with HTTP; Thu, 1 Mar 2018 00:28:58 -0800 (PST) In-Reply-To: <1519887444-75510-1-git-send-email-heyi.guo@linaro.org> References: <1519887444-75510-1-git-send-email-heyi.guo@linaro.org> From: Ard Biesheuvel Date: Thu, 1 Mar 2018 08:28:58 +0000 Message-ID: To: Heyi Guo Cc: "edk2-devel@lists.01.org" , Ruiyu Ni , Star Zeng , Eric Dong , Laszlo Ersek , Michael D Kinney , Maurice Ma , Prince Agyeman , Benjamin You , Jordan Justen , Anthony Perard , Julien Grall Subject: Re: [PATCH v5 0/6] Add translation support to generic PciHostBridge X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Mar 2018 08:22:52 -0000 Content-Type: text/plain; charset="UTF-8" On 1 March 2018 at 06:57, Heyi Guo wrote: > Patch v5 inherits the code from RFC v4; we don't restart the version number for > RFC to PATCH change. > > v5: > - Patch 4/6: Modify the code according to the comments from Ray. > - Patch 1/6 and 2/6 are totally new. They add initialization for all fields of > PCI_ROOT_BRIDGE_APERTURE temporary variables in PciHostBridgeLib instances, so > that they will not suffer from extension of PCI_ROOT_BRIDGE_APERTURE > structure. > - Generate a separate patch (3/6) for PciHostBridgeLib.h change. Though it is a > prerequisite for patch 4/6, it does not change the code in PciHostBridge > driver and won't cause any build failure or functional issue. > > > v4: > - Modify the code according to the comments from Ray, Laszlo and Ard (Please see > the notes of Patch 1/3) > - Ignore translation of bus in CreateRootBridge. > > > v3: > - Keep definition of Translation consistent in EDKII code: Translation = device > address - host address. > - Patch 2/2 is split into 2 patches (2/3 and 3/3). > - Refine comments and commit messages to make the code easier to understand. > > > v2: > Changs are made according to the discussion on the mailing list, including: > > - PciRootBridgeIo->Configuration should return CPU view address, as well as > PciIo->GetBarAttributes, and Translation Offset should be equal to PCI view > address - CPU view address. > - Add translation offset to PCI_ROOT_BRIDGE_APERTURE structure definition. > - PciHostBridge driver internally used Base Address is still based on PCI view > address, and translation offset = CPU view - PCI view, which follows the > definition in ACPI, and not the same as that in UEFI spec. > Heyi, Thanks again for taking the time to implement this. I have applied the patches and they appear to work on my SynQuacer system, which has two PCIe RCs of which one uses translation for the I/O space I.e., PCI0 has 0x0..0xffff mapped to MMIO offset 0x67f00000 PCI1 has 0x0..0xffff mapped to MMIO offset 0x77f00000 The only problem I am hitting now is that the 'mm' shell command has a hard coded 16-bit limit for IO space, which we should probably fix as well. If I remove this limit, I can correctly access the I/O space of PCI1 like this: Shell> mm 77f00010 MEM 0x0000000077F00010 : 0x00 > MEM 0x0000000077F00011 : 0x03 > MEM 0x0000000077F00012 : 0x00 > MEM 0x0000000077F00013 : 0x00 > MEM 0x0000000077F00014 : 0x00 > MEM 0x0000000077F00015 : 0xF0 > MEM 0x0000000077F00016 : 0x35 > MEM 0x0000000077F00017 : 0xFD > q Shell> mm 10010 -io IO 0x0000000000010010 : 0x00 > IO 0x0000000000010011 : 0x03 > IO 0x0000000000010012 : 0x00 > IO 0x0000000000010013 : 0x00 > IO 0x0000000000010014 : 0x00 > IO 0x0000000000010015 : 0xF0 > IO 0x0000000000010016 : 0x35 > IO 0x0000000000010017 : 0xFD > q Tested-by: Ard Biesheuvel > Cc: Ruiyu Ni > Cc: Ard Biesheuvel > Cc: Star Zeng > Cc: Eric Dong > Cc: Laszlo Ersek > Cc: Michael D Kinney > Cc: Maurice Ma > Cc: Prince Agyeman > Cc: Benjamin You > Cc: Jordan Justen > Cc: Anthony Perard > Cc: Julien Grall > > Heyi Guo (6): > CorebootPayloadPkg/PciHostBridgeLib: Init PCI aperture to 0 > OvmfPkg/PciHostBridgeLib: Init PCI aperture to 0 > MdeModulePkg/PciHostBridgeLib.h: add address Translation > MdeModulePkg/PciHostBridgeDxe: Add support for address translation > MdeModulePkg/PciBus: convert host address to device address > MdeModulePkg/PciBus: return CPU address for GetBarAttributes > > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h | 21 ++++ > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostResource.h | 3 + > MdeModulePkg/Include/Library/PciHostBridgeLib.h | 19 +++ > CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 5 + > MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 12 +- > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 129 +++++++++++++++++--- > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 118 ++++++++++++++++-- > OvmfPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 4 + > OvmfPkg/Library/PciHostBridgeLib/XenSupport.c | 5 + > 9 files changed, 288 insertions(+), 28 deletions(-) > > -- > 2.7.4 >