From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c06::229; helo=mail-io0-x229.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-io0-x229.google.com (mail-io0-x229.google.com [IPv6:2607:f8b0:4001:c06::229]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0E931208F7903 for ; Wed, 4 Oct 2017 01:12:30 -0700 (PDT) Received: by mail-io0-x229.google.com with SMTP id d16so9822117ioj.3 for ; Wed, 04 Oct 2017 01:15:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=gO8X/wGX/WeFU9MR2HUy4z97yZpVvAcTcAoROkQSUTA=; b=f7hVww/e78VJBK95pxGauMtHUw8zdvSqo6bHTAXFWW7Q2LKKyiN80ESYX4kO1rvcf7 4bw40PfiON0GO1EWm15T4yahILv1dV8U4CNDBy6wXbPIBOWNOsGg73UFVOpfebPCDbzZ HpVdJ+sDJpA6RsXCF48uLCFOPKtht2giWV9OA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=gO8X/wGX/WeFU9MR2HUy4z97yZpVvAcTcAoROkQSUTA=; b=fPnrr9iMwzkytYuB3C4a37dxCaKL24USg0hYy2n7S5TXOFF/HLV/Yz3vewhP79S2kG W6M+fsFPfLwcA0UAObjNVG2MoPi7V7ZziQ9v4qA7ZCell/8dYw5l5wgR2AbW8+6FojzB /PzZAwetk1+0lybaqSgK1B1aNCYZ0xknm75cKENIhAJJY6E3NKnAA++LueEkahQCLYEZ eC/djLrTEDRMOg2Zwyf6Bs59RoGrw1Bkrk9wwT35xriPBhD9gXWNIyRlec4+yraGTr9g 9/JF5qtQxK68CNv6c5B2GY7Tu4eTQWHiX83Pw8WWBWQO8PBzbyHJQvJQMVv0CPxvxGOI AoLA== X-Gm-Message-State: AMCzsaUxI/4ZQGjz1d9kcSPqFbzoVO86BfFMz2GEM9oi8ealTXnOFCyV luf+MwuPXXrnBGtSpVdXKP1rmZ7MrKUB/l856DU1cg== X-Google-Smtp-Source: AOwi7QCPzXnwnwPC4PX0hYcL4/0QMkPDEYNmLroCY1qTm4QydaAb645V8//EhHOpRHzGpbhcFy6UvktmohdF57Huj1k= X-Received: by 10.107.27.149 with SMTP id b143mr30229683iob.2.1507104951201; Wed, 04 Oct 2017 01:15:51 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.152.18 with HTTP; Wed, 4 Oct 2017 01:15:50 -0700 (PDT) In-Reply-To: <20171004081233.5095-1-leif.lindholm@linaro.org> References: <20171004081233.5095-1-leif.lindholm@linaro.org> From: Ard Biesheuvel Date: Wed, 4 Oct 2017 09:15:50 +0100 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" , Heyi Guo Subject: Re: [PATCH] Platform/Hisilicon: fix D02 driver indentation errors X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Oct 2017 08:12:31 -0000 Content-Type: text/plain; charset="UTF-8" On 4 October 2017 at 09:12, Leif Lindholm wrote: > When building with a somewhat recent toolchain (GCC 6.3), the D02 > platform fails due to (the implicit) -Werror=misleading-indentation. > > Cc: Heyi Guo > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Leif Lindholm Reviewed-by: Ard Biesheuvel > --- > Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c | 4 ++-- > Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c | 10 +++++----- > 2 files changed, 7 insertions(+), 7 deletions(-) > > diff --git a/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c b/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c > index d876565a7d..b18b56ddb2 100644 > --- a/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c > +++ b/Silicon/Hisilicon/Drivers/SasV1Dxe/SasV1Dxe.c > @@ -497,8 +497,8 @@ STATIC VOID hisi_sas_v1_init(struct hisi_hba *hba, PLATFORM_SAS_PROTOCOL *plat) > !(dma_rx_status & DMA_RX_STATUS_BUSY)) > break; > > - // Wait for status change in polling > - NanoSecondDelay (100); > + // Wait for status change in polling > + NanoSecondDelay (100); > } > } > > diff --git a/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c b/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c > index 3581b41c90..3739a36e64 100644 > --- a/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c > +++ b/Silicon/Hisilicon/Pv660/Drivers/PcieInitDxe/PcieInitLib.c > @@ -570,7 +570,7 @@ EFI_STATUS AssertPciePcsReset(UINT32 HostBridgeNum,UINT32 Port) > if (pcs_local_status_checked) > DEBUG((EFI_D_ERROR, "pcs local reset status read failed\n")); > > - count = 0; > + count = 0; > do { > MicroSecondDelay(1000); > count ++; > @@ -583,7 +583,7 @@ EFI_STATUS AssertPciePcsReset(UINT32 HostBridgeNum,UINT32 Port) > if (hilink_status_checked) > DEBUG((EFI_D_ERROR, "error:pcs assert reset failed\n")); > > - return EFI_SUCCESS; > + return EFI_SUCCESS; > } > > EFI_STATUS DeassertPciePcsReset(UINT32 HostBridgeNum, UINT32 Port) > @@ -616,7 +616,7 @@ EFI_STATUS DeassertPciePcsReset(UINT32 HostBridgeNum, UINT32 Port) > if (pcs_local_status_checked) > DEBUG((EFI_D_ERROR, "pcs deassert reset failed!\n")); > > - count = 0; > + count = 0; > do { > MicroSecondDelay(1000); > RegRead(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_ST_REG, hilink_reset_status); > @@ -627,7 +627,7 @@ EFI_STATUS DeassertPciePcsReset(UINT32 HostBridgeNum, UINT32 Port) > if (hilink_status_checked) > DEBUG((EFI_D_ERROR, "pcs deassert reset failed!\n")); > > - return EFI_SUCCESS; > + return EFI_SUCCESS; > } > > VOID PcieGen3Config(UINT32 HostBridgeNum, UINT32 Port) > @@ -777,7 +777,7 @@ EFI_STATUS HisiPcieClockCtrl(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, > if (clock_status_checked) > DEBUG((EFI_D_ERROR, "clock operation failed!\n")); > > - return EFI_SUCCESS; > + return EFI_SUCCESS; > } > > VOID PcieSpdSet(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port, UINT8 Spd) > -- > 2.11.0 >