From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::143; helo=mail-it1-x143.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it1-x143.google.com (mail-it1-x143.google.com [IPv6:2607:f8b0:4864:20::143]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B0E8920886F22 for ; Fri, 1 Mar 2019 02:34:20 -0800 (PST) Received: by mail-it1-x143.google.com with SMTP id m137so19439747ita.0 for ; Fri, 01 Mar 2019 02:34:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=P6Li6Kdv/6gt5v7KuNsnM5UQ1K4FI4Ie0Yey0/Y441k=; b=Lhn4Pv/cC31japch5HVRFITFHsfxgpgovjcbHeQ3veCSJSwkcBwrX4ZEbDh/HTD+E5 8iqrnatX4YqD8jCBhHLAXYk9Comm75jM/xJ9oxy9N4Opw540FiT4dFIHO9Dz0QUIy5H5 5JYLTmUgTe6ecULy/keMJWf06xZZfgazCpnT5rWvgNdpoKfPrw6UqJs6jzP4ig6k1YWo ZHpGy456hf6So+DynrHAfkjdmLapX+JAsL25n1zi+OeNZL+xuFCV3Z5Uks0EjcRawyyZ DpXFbuhmHvGKabjp9XNn3AFmIgTThZ7tXWUyLmVhmgbXDSlkrAKDJp0n0SpFtnrlsDzF cbkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=P6Li6Kdv/6gt5v7KuNsnM5UQ1K4FI4Ie0Yey0/Y441k=; b=DnFgycvbQqH3Tl1CEpNOk9Msnoggi/Dr/FYIAbiRM6zOOHVbjgq1nOUqk6fIohqgOI 4xs1h1a0OpXVgGqfWczxBeSYNv15NJaex8l7ZsYbIalsuGYSZ45Cd3ktzXvc1DyVLh4a PWVl7kyc6EH24U1p8SkE79FAAV+4o/bwrc5CQwuOqnms6AyOUFT6E+D7cOOkWsfZ9noh EtIHzd5X9xaoI09ODNz4IdQqyCvr+f/aMm2p66pxLjYaM3xZHZtEn8Aca6kh1ORyyA8B UANKAaXagJn4KZoGHt1GxSZ/TevxkmV4WKPMHD/fH2IWp+lZmPPvtMkjCl855xdJu6al /heg== X-Gm-Message-State: APjAAAXBRGCAx8t1KsoDdtedh/9pH+flHZGbmBIYfGvzcTdx0R42mhoH e+my48G4Iwfe2ZhrsiVE8UnwtEwENWB7pm4Bk5lXIA== X-Google-Smtp-Source: APXvYqyNrV20VSdfnYW082b6KgtObHZ0fOoDoyNA79Jy4YJ4UFTp9BkTY92eCuKXJaKH6SiqC+jIUjBXQyzLPzwi4aM= X-Received: by 2002:a24:2e90:: with SMTP id i138mr2950993ita.158.1551436459910; Fri, 01 Mar 2019 02:34:19 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: Ard Biesheuvel Date: Fri, 1 Mar 2019 11:34:08 +0100 Message-ID: To: Ashish Singhal Cc: "Cohen, Eugene" , "Wu, Hao A" , "edk2-devel@lists.01.org" Subject: Re: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC v3 64-bit systems X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Mar 2019 10:34:20 -0000 Content-Type: text/plain; charset="UTF-8" On Fri, 1 Mar 2019 at 11:32, Ard Biesheuvel wrote: > > On Fri, 1 Mar 2019 at 01:19, Ashish Singhal wrote: > > > > Eugene, > > > > Small question. Did the issue appear after the V4 patch went in? Looking at the code before that patch, we were enabling 64b dma in pci based on capability register already despite of driver supporting only 32b dma. > > > > I think this may have been an oversight on my part when I originally > added the DUAL_ADDRESS_CYCLE handling. > > The following commit added EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE to the > host bridge driver > > commit e58a71d9c50ba641b5ab19f5ce2cbf772187de4d > Author: Ard Biesheuvel > Date: Mon Sep 5 09:55:16 2016 +0100 > > MdeModulePkg/PciHostBridgeDxe: restrict 64-bit DMA to devices that > support it > > Currently, the EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute is completely > ignored by the PCI host bridge driver, which means that, on an > implementation > that supports DMA above 4 GB, allocations above 4 GB may be provided to > devices that have not expressed support for it. > > and the SDHCI driver was fixed accordingly in > > Author: Ard Biesheuvel > Date: Mon Sep 5 09:51:48 2016 +0100 > > MdeModulePkg/SdMmcPciHcDxe: enable 64-bit PCI DMA > > PCI controller drivers must set the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE > attribute if the controller supports 64-bit DMA addressing. > > So before these changes, we were in the exact same situation, but > since PC platforms never enable DMA above 4 GB in the first place, > nobody ever noticed until we started running this code on arm64 > platforms that have no 32-bit addressable DRAM to begin with. > > The obvious conclusion is that the driver should not set the > EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute if the device does > not support it, or, which seems to be our case, if the driver does not > implement the 64-bit DMA mode that the driver does support. Correction: that the *device* does support. > However, > since there are platforms for which bounce buffering is not an option > (since there is no 32-bit addressable memory to bounce to), this is > not just a performance optimization, and so it would be useful to fix > the code so it can drive all 64-bit DMA capable hardware.