Re: [PATCH 2/2] ArmPlatformPkg/PL111LcdArmVExpressLib: use write-combine mapping for VRAM

[Ard Biesheuvel <ard.biesheuvel@linaro.org>]

On 6 April 2017 at 12:14, Ryan Harkin <ryan.harkin@linaro.org> wrote:
> On 5 April 2017 at 21:38, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
>> Replace the uncached memory mapping of the framebuffer with a write-
>> combining one. This improves performance, and avoids issues with
>> unaligned accesses and DC ZVA instructions performed by the accelerated
>> memcpy/memset routines.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.0
>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>
> Well, ... PL111 isn't usually enabled for me. And if I enable it,
> neither Foundation nor AEMv8 models boot with or without this patch.
>
> So it's no worse than before....
>

Not even foundation model? That is strange ...

>
>> ---
>>  ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c
>> index 2000c9bdf436..d18d6b3e1665 100644
>> --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c
>> +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c
>> @@ -192,7 +192,7 @@ LcdPlatformGetVram (
>>      ASSERT_EFI_ERROR(Status);
>>
>>      // Mark the VRAM as un-cachable. The VRAM is inside the DRAM, which is cachable.
>> -    Status = Cpu->SetMemoryAttributes(Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC);
>> +    Status = Cpu->SetMemoryAttributes(Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_WC);
>>      ASSERT_EFI_ERROR(Status);
>>      if (EFI_ERROR(Status)) {
>>        gBS->FreePool(VramBaseAddress);
>> --
>> 2.7.4
>>
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