From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-it0-x22f.google.com (mail-it0-x22f.google.com [IPv6:2607:f8b0:4001:c0b::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4ED6D81F5B for ; Mon, 27 Feb 2017 07:33:57 -0800 (PST) Received: by mail-it0-x22f.google.com with SMTP id h10so60312710ith.1 for ; Mon, 27 Feb 2017 07:33:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=sJuy5riY8K2OFu73HxdBrewSlSqhzqdUfPA7ACFSdFQ=; b=BI+oGumyYYw/wwePRAQLPTlHP+6n/1nSuCRhpAzeA7rfrf+YXiIgGlGZKO6CWG7Ypi 6dLDx6kEUtZmk4mXZM3/HxIf9EZoUsj94ErhryPl1eQvF6G1Z9EOG/WcxiLWheFSSti9 XV+Y8+gPGPtcW+YjdG585TEaxvtQBjmjTzR3c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=sJuy5riY8K2OFu73HxdBrewSlSqhzqdUfPA7ACFSdFQ=; b=uS/C1p/KhqPoWFHa5nCZdIriSjeYCz7hWsgmyMlXCT3qVHbOeZVzGNH7pMEq9UZzma zsdWFFpvVkhxn6vTM0b7TAVZSiLMLYBmTP1JSOePxjYAsnpAFYZiqtfo6ZYt5THwlPCz NFkgepWQ2wbTXPhuQaNJAt4k+7l8j64bIHCikraySrpSnqeSXtTwmvkI8qIxxEASm6V5 diwk36xcbQey32Fepag8H2mBx0a6cjKp6lQdZ7tI1gnxYzsRPcePDph7BRKpmMpTBK3z Uy7aw/DvlNJnep3W1v/4uiKA7qiVVfxGOo/WTE622JJe4KB7Igr+pOE472rIr6a4piii 96lg== X-Gm-Message-State: AMke39kU0484L+7amoRrUAd5FCb71UJWR5F3JIRbqRo0TvXOATE5TVBIeDuJwD03SAZ3P0Ebm7hee2Kms+No034d X-Received: by 10.36.207.212 with SMTP id y203mr14395890itf.63.1488209636566; Mon, 27 Feb 2017 07:33:56 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.10.27 with HTTP; Mon, 27 Feb 2017 07:33:56 -0800 (PST) In-Reply-To: <20170227153227.GD16034@bivouac.eciton.net> References: <1488206291-25768-1-git-send-email-ard.biesheuvel@linaro.org> <1488206291-25768-2-git-send-email-ard.biesheuvel@linaro.org> <20170227153227.GD16034@bivouac.eciton.net> From: Ard Biesheuvel Date: Mon, 27 Feb 2017 15:33:56 +0000 Message-ID: To: Leif Lindholm Cc: "edk2-devel@lists.01.org" , "afish@apple.com" , "Kinney, Michael D" , "Gao, Liming" , "Yao, Jiewen" , Laszlo Ersek , "Tian, Feng" , "Zeng, Star" Subject: Re: [PATCH v4 1/7] ArmPkg/CpuDxe: ignore attribute changes during SyncCacheConfig() X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Feb 2017 15:33:57 -0000 Content-Type: text/plain; charset=UTF-8 On 27 February 2017 at 15:32, Leif Lindholm wrote: > On Mon, Feb 27, 2017 at 02:38:05PM +0000, Ard Biesheuvel wrote: >> To prevent the initial MMU->GCD memory space map synchronization from >> stripping permissions attributes [which we cannot use in the GCD memory >> space map, unfortunately], implement the same approach as x86, and ignore >> SetMemoryAttributes() calls during the time SyncCacheConfig() is in >> progress. This is a horrible hack, but is currently the only way we can >> implement strict permissions on arbitrary memory regions [as opposed to >> PE/COFF text/data sections only] > > Sounds like another excellent argument for why this CpuDxe should be > cosying up with the UefiCpuPkg one longer-term. > I suppose so, yes. >> Contributed-under: TianoCore Contribution Agreement 1.0 >> Signed-off-by: Ard Biesheuvel >> Reviewed-by: Jiewen Yao >> --- >> ArmPkg/Drivers/CpuDxe/CpuDxe.c | 3 +++ >> ArmPkg/Drivers/CpuDxe/CpuDxe.h | 1 + >> ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 4 ++++ >> 3 files changed, 8 insertions(+) >> >> diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/ArmPkg/Drivers/CpuDxe/CpuDxe.c >> index 5aa5b874144a..1955d1dece03 100644 >> --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.c >> +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.c >> @@ -17,6 +17,7 @@ >> >> #include >> >> +BOOLEAN gIsFlushingGCD; > > OK, I am unable to not bikeshed this: > The behaviour you're copying is implemented via a variable called > mIsFlushingGCD. Why change the prefix? Surely we're not looking to > export this variable any further in ARM? > Because it is not local the one compilation unit, that's all. It is not in a library, so in that sense, it is guaranteed to remain local to this module, if that is any consolation. >> >> /** >> This function flushes the range of addresses from Start to Start+Length >> @@ -261,7 +262,9 @@ CpuDxeInitialize ( >> // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go >> // after the protocol is installed >> // >> + gIsFlushingGCD = TRUE; >> SyncCacheConfig (&mCpu); >> + gIsFlushingGCD = FALSE; >> >> // If the platform is a MPCore system then install the Configuration Table describing the >> // secondary core states >> diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.h b/ArmPkg/Drivers/CpuDxe/CpuDxe.h >> index a00fc3064362..085e4cab2921 100644 >> --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.h >> +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.h >> @@ -37,6 +37,7 @@ >> #include >> #include >> >> +extern BOOLEAN gIsFlushingGCD; > > Eew ... this suggest we are. > > / > Leif > >> >> /** >> This function registers and enables the handler specified by InterruptHandler for a processor >> diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c >> index ebe593d1c325..6dfec7e55888 100644 >> --- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c >> +++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c >> @@ -188,6 +188,10 @@ CpuSetMemoryAttributes ( >> UINTN RegionLength; >> UINTN RegionArmAttributes; >> >> + if (gIsFlushingGCD) { >> + return EFI_SUCCESS; >> + } >> + >> if ((BaseAddress & (SIZE_4KB - 1)) != 0) { >> // Minimum granularity is SIZE_4KB (4KB on ARM) >> DEBUG ((EFI_D_PAGE, "CpuSetMemoryAttributes(%lx, %lx, %lx): Minimum ganularity is SIZE_4KB\n", BaseAddress, Length, EfiAttributes)); >> -- >> 2.7.4 >>