From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-it0-x235.google.com (mail-it0-x235.google.com [IPv6:2607:f8b0:4001:c0b::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id ED870820AE for ; Thu, 16 Feb 2017 12:46:56 -0800 (PST) Received: by mail-it0-x235.google.com with SMTP id 203so115070434ith.0 for ; Thu, 16 Feb 2017 12:46:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=E0kOAajZPCZIKBILuALDXRy83qNFKinGqiNiiNxY6YQ=; b=Ce7a1xeHDFMF51nz/CydNkbpcko5xkj/527z6Y2xpGU0uo7HT/8VYt8Zf61FggZsc7 Xv+vLQm5Y1WzYOeH8eBIs7yOWWN1Rz9QYT2BsfEvGtVul2E398T7QPJRGM8nRbplyulp 3UFZYgLNXCSWhZjkFNtHFcOyDoNZ47sQrhG3Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=E0kOAajZPCZIKBILuALDXRy83qNFKinGqiNiiNxY6YQ=; b=Ln4ek/0tiRoifKlxH+gON4G/Vy2IJfVwEnx/yzg0MYIOQagk8RuMCKLvjhRnlyZZYc bRiP32083E9gPXxsRrid5Bqk/TVXkNgyBzjIcmUd6VqIF6bbcxLLRCKGurObhRJC++05 oCdS7ueC5nCe1Q1+WEYDuxxftV9CeebLCwYpqrDIUe/oQywNZAkAK373fkWIk4MbM2+D OUUfIRDZvDn0CDryQkYvQqKubvHiO+l1A26bmNhcorGLYbsWzk7+j+QcKmIhomj/8rtn MT240qrXoWH+td6NMCXdb++yGGsRzmMDW8ThbQCeVI0VkYVtKUHk7YULtlkbebrWPuzm HqnQ== X-Gm-Message-State: AMke39m8ORDQzWFemRXiUyyNDYaA+deOF8b/weoTyOEcE7YDBYQJR+eTrTswBklzI5ytCpvxocfhsdSfUZmB+Dga X-Received: by 10.36.23.74 with SMTP id 71mr14902279ith.37.1487278016141; Thu, 16 Feb 2017 12:46:56 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.198.134 with HTTP; Thu, 16 Feb 2017 12:46:55 -0800 (PST) In-Reply-To: References: <20170209192623.262044-1-evan.lloyd@arm.com> <20170209192623.262044-5-evan.lloyd@arm.com> From: Ard Biesheuvel Date: Thu, 16 Feb 2017 20:46:55 +0000 Message-ID: To: Evan Lloyd Cc: "edk2-devel@lists.01.org" , Leif Lindholm , "ryan.harkin@linaro.org" Subject: Re: [PATCH 4/4] ArmPkg:Provide GetTriggerType/SetTriggerType functions X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Feb 2017 20:46:57 -0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable On 16 February 2017 at 20:16, Evan Lloyd wrote: > Hi Ard. > Your comments make sense and we will comply (including "Please no spaces = after casts"). > However, I can find nothing requiring no space after casts in the CCS. > It does have some casts in example code: > 5.7.2.3 has "if ((INTN)foo >=3D 0)" with no space > 5.7.2.4 has "if (( LogEntryArray[Index].Handle =3D=3D (EFI_PHYSICAL_ADDRE= SS) (UINTN) Handle)" with spaces (and others). > > By the standard edk2 process we should determine which is the most popula= r and insist on the reverse. :-) > This comes up now and again on the mailing list, and there is consensus that, due to the high precedence of the cast operator, putting a space after it is counter intuitive. So please omit them, and certainly don't add spaces after casts when it is the only change made on those particular lines. Thanks, Ard. >>-----Original Message----- >>From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] >>Sent: 13 February 2017 13:05 >>To: Evan Lloyd >>Cc: edk2-devel@lists.01.org; Leif Lindholm; ryan.harkin@linaro.org >>Subject: Re: [PATCH 4/4] ArmPkg:Provide GetTriggerType/SetTriggerType >>functions >> >>(apologies for the delayed [and now somewhat redundant] response, this >>sat in my outbox since this morning) >> >>On 9 February 2017 at 19:26, wrote: >>> From: Girish Pathak >>> >>> This change implements GetTriggerType and SetTriggerType functions >>> in ArmGicV2Dxe (GicV2GetTriggerType/GicV2SetTriggerType) >>> and ArmGicV3Dxe (GicV3GetTriggerType/GicV3SetTriggerType) >>> >>> SetTriggerType configures the interrupt mode of an interrupt >>> as edge sensitive or level sensitive. >>> >>> GetTriggerType function returns the mode of an interrupt. >>> >>> The requirement for this change derives from a problem detected on >>ARM >>> Juno boards, but the change is of generic relevance. >>> >>> NOTE: At this point the GICv3 code is not tested. >>> >>> Contributed-under: TianoCore Contribution Agreement 1.0 >>> Signed-off-by: Girish Pathak >>> Signed-off-by: Evan Lloyd >>> Tested-by: Girish Pathak >> >>It's probably best to reorder this patch with #3, or perhaps fold it >>into #2 entirely. >> >>> --- >>> ArmPkg/Include/Library/ArmGicLib.h | 4 + >>> ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c | 165 >>++++++++++++++++++-- >>> ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 159 >>+++++++++++++++++-- >>> 3 files changed, 308 insertions(+), 20 deletions(-) >>> >>> diff --git a/ArmPkg/Include/Library/ArmGicLib.h >>b/ArmPkg/Include/Library/ArmGicLib.h >>> index >>4364f3ffef464596f64cf59881d703cf54cf0ddd..6610f356c20e73d84ff3ba51995 >>6b426d97ef1eb 100644 >>> --- a/ArmPkg/Include/Library/ArmGicLib.h >>> +++ b/ArmPkg/Include/Library/ArmGicLib.h >>> @@ -51,6 +51,10 @@ >>> #define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable >>(ARE) >>> #define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS) >>> >>> +// GICD_ICDICFR bits >>> +#define ARM_GIC_ICDICFR_LEVEL_TRIGGERED 0x0 // Level triggered >>interrupt >>> +#define ARM_GIC_ICDICFR_EDGE_TRIGGERED 0x1 // Edge triggered >>interrupt >>> + >>> // >>> // GIC Redistributor >>> // >>> diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c >>b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c >>> index >>8c4d66125e2e8c7af9898f336ee742ed0aebf058..1f47403c6cdc7e8c0f6ac65d3 >>b95a562da6a2d32 100644 >>> --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c >>> +++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c >>> @@ -29,6 +29,7 @@ Abstract: >>> #define ARM_GIC_DEFAULT_PRIORITY 0x80 >>> >>> extern EFI_HARDWARE_INTERRUPT_PROTOCOL >>gHardwareInterruptV2Protocol; >>> +extern EFI_HARDWARE_INTERRUPT2_PROTOCOL >>gHardwareInterrupt2V2Protocol; >>> >>> STATIC UINT32 mGicInterruptInterfaceBase; >>> STATIC UINT32 mGicDistributorBase; >>> @@ -193,19 +194,95 @@ EFI_HARDWARE_INTERRUPT_PROTOCOL >>gHardwareInterruptV2Protocol =3D { >>> GicV2EndOfInterrupt >>> }; >>> >>> +/** >>> + Calculate GICD_ICFGRn base address and corresponding bit >>> + field Int_config[1] of the GIC distributor register. >>> + >>> + @param Source Hardware source of the interrupt. >>> + @param RegAddress Corresponding GICD_ICFGRn base address. >>> + @param BitNumber Bit number in the register to set/reset. >>> + >>> + @retval EFI_SUCCESS Source interrupt supported. >>> + @retval EFI_UNSUPPORTED Source interrupt is not supported. >>> +**/ >>> STATIC >>> EFI_STATUS >>> +GicGetDistributorIntrCfgBaseAndBitField ( >>> + IN HARDWARE_INTERRUPT_SOURCE Source, >>> + OUT UINTN *RegAddress, >>> + OUT UINTN *BitNumber >>> + ) >>> +{ >>> + UINTN RegOffset; >>> + UINTN Field; >>> + >>> + if (Source >=3D mGicNumInterrupts) { >>> + ASSERT(Source < mGicNumInterrupts); >>> + return EFI_UNSUPPORTED; >>> + } >>> + >>> + RegOffset =3D Source / 16; >>> + Field =3D Source % 16; >>> + *RegAddress =3D PcdGet64 (PcdGicDistributorBase) >>> + + ARM_GIC_ICDICFR >>> + + (4 * RegOffset); >>> + *BitNumber =3D (Field * 2) + 1; >>> + >>> + return EFI_SUCCESS; >>> +} >>> + >>> +/** >>> + Get interrupt trigger type of an interrupt >>> + >>> + @param This Instance pointer for this protocol >>> + @param Source Hardware source of the interrupt. >>> + @param TriggerType Returns interrupt trigger type. >>> + >>> + @retval EFI_SUCCESS Source interrupt supported. >>> + @retval EFI_UNSUPPORTED Source interrupt is not supported. >>> +**/ >>> +EFI_STATUS >> >>STATIC ? >> >>> EFIAPI >>> GicV2GetTriggerType ( >>> IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, >>> - IN HARDWARE_INTERRUPT_SOURCE Source, >>> + IN HARDWARE_INTERRUPT_SOURCE Source, >>> OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType >>> ) >>> { >>> + UINTN RegAddress; >>> + UINTN BitNumber; >>> + EFI_STATUS Status; >>> + >>> + RegAddress =3D 0; >>> + BitNumber =3D 0; >>> + >>> + Status =3D GicGetDistributorIntrCfgBaseAndBitField ( >>> + Source, >>> + &RegAddress, >>> + &BitNumber >>> + ); >>> + >>> + if (EFI_ERROR (Status)) { >>> + return Status; >>> + } >>> + >>> + *TriggerType =3D (MmioBitFieldRead32 (RegAddress, BitNumber, >>BitNumber) =3D=3D 0) >>> + ? EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH >>> + : EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING; >>> + >>> return EFI_SUCCESS; >>> } >>> >>> -STATIC >> >>? >> >>> +/** >>> + Set interrupt trigger type of an interrupt >>> + >>> + @param This Instance pointer for this protocol >>> + @param Source Hardware source of the interrupt. >>> + @param TriggerType Interrupt trigger type. >>> + >>> + @retval EFI_SUCCESS Source interrupt supported. >>> + @retval EFI_UNSUPPORTED Source interrupt is not supported. >>> +**/ >>> EFI_STATUS >>> EFIAPI >>> GicV2SetTriggerType ( >>> @@ -214,20 +291,83 @@ GicV2SetTriggerType ( >>> IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType >>> ) >>> { >>> + UINTN RegAddress =3D 0; >>> + UINTN BitNumber =3D 0; >>> + UINT32 Value; >>> + EFI_STATUS Status; >>> + BOOLEAN IntrSourceEnabled; >>> + >>> + if (TriggerType !=3D >>EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING >>> + && TriggerType !=3D >>EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH) { >>> + DEBUG ((EFI_D_ERROR, "Invalid interrupt trigger type: %d\n",= \ >>> + TriggerType)); >>> + ASSERT (FALSE); >>> + return EFI_UNSUPPORTED; >>> + } >>> + >>> + Status =3D GicGetDistributorIntrCfgBaseAndBitField ( >>> + Source, >>> + &RegAddress, >>> + &BitNumber >>> + ); >>> + >>> + if (EFI_ERROR (Status)) { >>> + return Status; >>> + } >>> + >>> + Status =3D GicV2GetInterruptSourceState ( >>> + (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, >>> + Source, >>> + &IntrSourceEnabled >>> + ); >>> + >>> + if (EFI_ERROR (Status)) { >>> + return Status; >>> + } >>> + >>> + Value =3D (TriggerType =3D=3D >>EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING) >>> + ? ARM_GIC_ICDICFR_EDGE_TRIGGERED >>> + : ARM_GIC_ICDICFR_LEVEL_TRIGGERED; >>> + >>> + // >>> + // Before changing the value, we must disable the interrupt, >>> + // otherwise GIC behavior is UNPREDICTABLE. >>> + // >>> + if (IntrSourceEnabled) { >>> + GicV2DisableInterruptSource ( >>> + (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, >>> + Source >>> + ); >>> + } >>> + >>> + MmioAndThenOr32 ( >>> + RegAddress, >>> + ~(0x1 << BitNumber), >>> + Value << BitNumber >>> + ); >>> + // >>> + // Restore interrupt state >>> + // >>> + if (IntrSourceEnabled) { >>> + GicV2EnableInterruptSource ( >>> + (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, >>> + Source >>> + ); >>> + } >>> + >>> return EFI_SUCCESS; >>> } >>> >>> -STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL >>gHardwareInterrupt2V2Protocol =3D { >>> - (HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource, >>> - (HARDWARE_INTERRUPT2_ENABLE)GicV2EnableInterruptSource, >>> - (HARDWARE_INTERRUPT2_DISABLE)GicV2DisableInterruptSource, >>> - >>(HARDWARE_INTERRUPT2_INTERRUPT_STATE)GicV2GetInterruptSourceSta >>te, >>> - (HARDWARE_INTERRUPT2_END_OF_INTERRUPT)GicV2EndOfInterrupt, >>> +EFI_HARDWARE_INTERRUPT2_PROTOCOL >>gHardwareInterrupt2V2Protocol =3D { >>> + (HARDWARE_INTERRUPT2_REGISTER) RegisterInterruptSource, >>> + (HARDWARE_INTERRUPT2_ENABLE) GicV2EnableInterruptSource, >>> + (HARDWARE_INTERRUPT2_DISABLE) GicV2DisableInterruptSource, >>> + (HARDWARE_INTERRUPT2_INTERRUPT_STATE) >>GicV2GetInterruptSourceState, >>> + (HARDWARE_INTERRUPT2_END_OF_INTERRUPT) GicV2EndOfInterrupt, >> >>Please no spaces after casts >> >>> GicV2GetTriggerType, >>> GicV2SetTriggerType >>> }; >>> >>> - >> >>Spurious whitespace change >> >>> /** >>> Shutdown our hardware >>> >>> @@ -346,8 +486,11 @@ GicV2DxeInitialize ( >>> ArmGicEnableDistributor (mGicDistributorBase); >>> >>> Status =3D InstallAndRegisterInterruptService ( >>> - &gHardwareInterruptV2Protocol, >>&gHardwareInterrupt2V2Protocol, >>> - GicV2IrqInterruptHandler, GicV2ExitBootServicesEvent); >>> + &gHardwareInterruptV2Protocol, >>> + &gHardwareInterrupt2V2Protocol, >>> + GicV2IrqInterruptHandler, >>> + GicV2ExitBootServicesEvent >>> + ); >>> >> >>Spurious whitespace change >> >>> return Status; >>> } >>> diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c >>b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c >>> index >>02deeef78b6d7737172a5992c6decac43cfdd64a..a0383ecd7738750f73a225381 >>1403d6ed0d2fd51 100644 >>> --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c >>> +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c >>> @@ -19,6 +19,7 @@ >>> #define ARM_GIC_DEFAULT_PRIORITY 0x80 >>> >>> extern EFI_HARDWARE_INTERRUPT_PROTOCOL >>gHardwareInterruptV3Protocol; >>> +extern EFI_HARDWARE_INTERRUPT2_PROTOCOL >>gHardwareInterrupt2V3Protocol; >>> >>> STATIC UINTN mGicDistributorBase; >>> STATIC UINTN mGicRedistributorsBase; >>> @@ -184,8 +185,54 @@ EFI_HARDWARE_INTERRUPT_PROTOCOL >>gHardwareInterruptV3Protocol =3D { >>> GicV3EndOfInterrupt >>> }; >>> >>> +/** >>> + Calculate GICD_ICFGRn base address and corresponding bit >>> + field Int_config[1] in the GIC distributor register. >>> + >>> + @param Source Hardware source of the interrupt. >>> + @param RegAddress Corresponding GICD_ICFGRn base address. >>> + @param BitNumber Bit number in the register to set/reset. >>> + >>> + @retval EFI_SUCCESS Source interrupt supported. >>> + @retval EFI_UNSUPPORTED Source interrupt is not supported. >>> +**/ >>> STATIC >>> EFI_STATUS >>> +GicGetDistributorIntrCfgBaseAndBitField ( >>> + IN HARDWARE_INTERRUPT_SOURCE Source, >>> + OUT UINTN *RegAddress, >>> + OUT UINTN *BitNumber >>> + ) >>> +{ >>> + UINTN RegOffset; >>> + UINTN Field; >>> + >>> + if (Source >=3D mGicNumInterrupts) { >>> + ASSERT(FALSE); >>> + return EFI_UNSUPPORTED; >>> + } >>> + >>> + RegOffset =3D Source / 16; >>> + Field =3D Source % 16; >>> + *RegAddress =3D PcdGet64 (PcdGicDistributorBase) >>> + + ARM_GIC_ICDICFR >>> + + (4 * RegOffset); >>> + *BitNumber =3D (Field * 2) + 1; >>> + >>> + return EFI_SUCCESS; >>> +} >>> + >>> +/** >>> + Get interrupt trigger type of an interrupt >>> + >>> + @param This Instance pointer for this protocol >>> + @param Source Hardware source of the interrupt. >>> + @param TriggerType Returns interrupt trigger type. >>> + >>> + @retval EFI_SUCCESS Source interrupt supported. >>> + @retval EFI_UNSUPPORTED Source interrupt is not supported. >>> +**/ >>> +EFI_STATUS >> >>STATIC ? >> >>> EFIAPI >>> GicV3GetTriggerType ( >>> IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This, >>> @@ -193,10 +240,37 @@ GicV3GetTriggerType ( >>> OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType >>> ) >>> { >>> + UINTN RegAddress =3D 0; >>> + UINTN BitNumber =3D 0; >>> + EFI_STATUS Status; >>> + >>> + Status =3D GicGetDistributorIntrCfgBaseAndBitField ( >>> + Source, >>> + &RegAddress, >>> + &BitNumber >>> + ); >>> + >>> + if (EFI_ERROR (Status)) { >>> + return Status; >>> + } >>> + >>> + *TriggerType =3D (MmioBitFieldRead32 (RegAddress, BitNumber, >>BitNumber) =3D=3D 0) >>> + ? EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH >>> + : EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING; >>> + >>> return EFI_SUCCESS; >>> } >>> >>> -STATIC >>> +/** >>> + Set interrupt trigger type of an interrupt >>> + >>> + @param This Instance pointer for this protocol >>> + @param Source Hardware source of the interrupt. >>> + @param TriggerType Interrupt trigger type. >>> + >>> + @retval EFI_SUCCESS Source interrupt supported. >>> + @retval EFI_UNSUPPORTED Source interrupt is not supported. >>> +**/ >>> EFI_STATUS >>> EFIAPI >>> GicV3SetTriggerType ( >>> @@ -205,15 +279,79 @@ GicV3SetTriggerType ( >>> IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType >>> ) >>> { >>> + UINTN RegAddress; >>> + UINTN BitNumber; >>> + UINT32 Value; >>> + EFI_STATUS Status; >>> + BOOLEAN IntrSourceEnabled; >>> + >>> + if (TriggerType !=3D >>EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING >>> + && TriggerType !=3D >>EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH) { >>> + DEBUG ((EFI_D_ERROR, "Invalid interrupt trigger type: %d\n",= \ >>> + TriggerType)); >>> + ASSERT (FALSE); >>> + return EFI_UNSUPPORTED; >>> + } >>> + >>> + Status =3D GicGetDistributorIntrCfgBaseAndBitField ( >>> + Source, >>> + &RegAddress, >>> + &BitNumber >>> + ); >>> + >>> + if (EFI_ERROR (Status)) { >>> + return Status; >>> + } >>> + >>> + Status =3D GicV3GetInterruptSourceState ( >>> + (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, >>> + Source, >>> + &IntrSourceEnabled >>> + ); >>> + >>> + if (EFI_ERROR (Status)) { >>> + return Status; >>> + } >>> + >>> + Value =3D (TriggerType =3D=3D >>EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING) >>> + ? ARM_GIC_ICDICFR_EDGE_TRIGGERED >>> + : ARM_GIC_ICDICFR_LEVEL_TRIGGERED; >>> + >>> + // >>> + // Before changing the value, we must disable the interrupt, >>> + // otherwise GIC behavior is UNPREDICTABLE. >>> + // >>> + if (IntrSourceEnabled) { >>> + GicV3DisableInterruptSource ( >>> + (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, >>> + Source >>> + ); >>> + } >>> + >>> + MmioAndThenOr32 ( >>> + RegAddress, >>> + ~(0x1 << BitNumber), >>> + Value << BitNumber >>> + ); >>> + // >>> + // Restore interrupt state >>> + // >>> + if (IntrSourceEnabled) { >>> + GicV3EnableInterruptSource ( >>> + (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This, >>> + Source >>> + ); >>> + } >>> + >>> return EFI_SUCCESS; >>> } >>> >>> -STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL >>gHardwareInterrupt2V3Protocol =3D { >>> - (HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource, >>> - (HARDWARE_INTERRUPT2_ENABLE)GicV3EnableInterruptSource, >>> - (HARDWARE_INTERRUPT2_DISABLE)GicV3DisableInterruptSource, >>> - >>(HARDWARE_INTERRUPT2_INTERRUPT_STATE)GicV3GetInterruptSourceSta >>te, >>> - (HARDWARE_INTERRUPT2_END_OF_INTERRUPT)GicV3EndOfInterrupt, >>> +EFI_HARDWARE_INTERRUPT2_PROTOCOL >>gHardwareInterrupt2V3Protocol =3D { >>> + (HARDWARE_INTERRUPT2_REGISTER) RegisterInterruptSource, >>> + (HARDWARE_INTERRUPT2_ENABLE) GicV3EnableInterruptSource, >>> + (HARDWARE_INTERRUPT2_DISABLE) GicV3DisableInterruptSource, >>> + (HARDWARE_INTERRUPT2_INTERRUPT_STATE) >>GicV3GetInterruptSourceState, >>> + (HARDWARE_INTERRUPT2_END_OF_INTERRUPT) GicV3EndOfInterrupt, >>> GicV3GetTriggerType, >>> GicV3SetTriggerType >>> }; >>> @@ -365,8 +503,11 @@ GicV3DxeInitialize ( >>> ArmGicEnableDistributor (mGicDistributorBase); >>> >>> Status =3D InstallAndRegisterInterruptService ( >>> - &gHardwareInterruptV3Protocol, >>&gHardwareInterrupt2V3Protocol, >>> - GicV3IrqInterruptHandler, GicV3ExitBootServicesEvent); >>> + &gHardwareInterruptV3Protocol, >>> + &gHardwareInterrupt2V3Protocol, >>> + GicV3IrqInterruptHandler, >>> + GicV3ExitBootServicesEvent >>> + ); >>> >>> return Status; >>> } >>> -- >>> Guid("CE165669-3EF3-493F-B85D-6190EE5B9759") >>> > IMPORTANT NOTICE: The contents of this email and any attachments are conf= idential and may also be privileged. If you are not the intended recipient,= please notify the sender immediately and do not disclose the contents to a= ny other person, use it for any purpose, or store or copy the information i= n any medium. Thank you.