From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::143; helo=mail-it1-x143.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it1-x143.google.com (mail-it1-x143.google.com [IPv6:2607:f8b0:4864:20::143]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 237E82118847D for ; Wed, 7 Nov 2018 06:48:33 -0800 (PST) Received: by mail-it1-x143.google.com with SMTP id p11-v6so13248953itf.0 for ; Wed, 07 Nov 2018 06:48:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=sMKy4xSvm8ehP68zmsntYLrsT+unDE0txWxaD+CcljU=; b=IQNeLl0kPTfzwKbHEcaAQiXpcqKtcsrdeRhQ1xzKhje9WS/vqm5jeMd69eJOGYBtsX xaFdU48xYcr/PP9pQwqQgQZduVR5H2XZ1SqFBHcb4gYyH1n7tKbjzZ4B91yWERZ7MkWC 1mm195xUGnunfx/dwnXrhYxzOoEGAaooc6xE4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=sMKy4xSvm8ehP68zmsntYLrsT+unDE0txWxaD+CcljU=; b=rCrbH263BMjiXixLLGiSvDUJ4sEULWRQowbTPlbwACMmt6hAEPGjEqwA6gTbExGHOB yrFzJcVk/7KLTKSaxrD3R6ZT8NdYI/FmWLHnfVuwwL3SJp4H3+EYF0LRG9iwAgISERVm R4FFBYiI4yeQFFhG1YUfV9fibTTuk/G0RF0JjC74etci/r8VThtAtX+Dve4uvOyJfdDP G0DWjw7NFuN9niQQa0Gm+AyhjF78W5Zyeg3dKVH53S2x4725ysO7amFTHidWAkTLhqsp TIA8TR1DI+hVmi+BQZafo0q9PvG/CSe7xJ1kqbR7mmZ0m/s6BA9ZIfY6NIU8tqcgaVgS I1wg== X-Gm-Message-State: AGRZ1gI9GsiEMToYdKvOep80vTuB//jzRuGx5QheHMyitcs+qjl/baYh j9KKkH72F2h2JCn1Tra6tS+Nl6yH0ahbWKC1oHPARw== X-Google-Smtp-Source: AJdET5eNzmChD7XMqavu31vdUh32tk1T1zVBctLdPncrJTTHCEtMljrlvrSLqBWgBvuoaKXcJx5t7naCxuzN7/9WT6w= X-Received: by 2002:a24:7d8d:: with SMTP id b135-v6mr392130itc.121.1541602112384; Wed, 07 Nov 2018 06:48:32 -0800 (PST) MIME-Version: 1.0 Received: by 2002:a6b:4f16:0:0:0:0:0 with HTTP; Wed, 7 Nov 2018 06:48:31 -0800 (PST) In-Reply-To: <20181029045708.6292-2-ming.huang@linaro.org> References: <20181029045708.6292-1-ming.huang@linaro.org> <20181029045708.6292-2-ming.huang@linaro.org> From: Ard Biesheuvel Date: Wed, 7 Nov 2018 15:48:31 +0100 Message-ID: To: Ming Huang , Marc Zyngier Cc: Leif Lindholm , linaro-uefi , "edk2-devel@lists.01.org" , Graeme Gregory , "Kinney, Michael D" , Laszlo Ersek , wanghuiqiang , huangming , Jason Zhang , huangdaode@hisilicon.com, John Garry , Xinliang Liu , zhangfeng56@huawei.com Subject: Re: [PATCH edk2/ArmPkg v1 1/1] ArmPkg: Fix Gic interrupt routing modes bug X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 07 Nov 2018 14:48:33 -0000 Content-Type: text/plain; charset="UTF-8" (+ Marc) On 29 October 2018 at 05:57, Ming Huang wrote: > As GicV3 Spec, Interrupt Routing Modes should be 0 for > routing the SPIs to the primary CPU. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ming Huang > --- > ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > index 01154848f443..1558db31713a 100644 > --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > @@ -469,7 +469,7 @@ GicV3DxeInitialize ( > for (Index = 0; Index < (mGicNumInterrupts - 32); Index++) { > MmioWrite32 ( > mGicDistributorBase + ARM_GICD_IROUTER + (Index * 8), > - CpuTarget | ARM_GICD_IROUTER_IRM > + CpuTarget > ); > } > } > -- > 2.18.0 >