From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::241; helo=mail-it0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-it0-x241.google.com (mail-it0-x241.google.com [IPv6:2607:f8b0:4001:c0b::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3E37F224A9ED5 for ; Fri, 30 Mar 2018 08:34:07 -0700 (PDT) Received: by mail-it0-x241.google.com with SMTP id u62-v6so938062ita.5 for ; Fri, 30 Mar 2018 08:34:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=ejjDconYxCq2KTpAv7XZnQ3pGEuUQS9qNCRR4UaQbW4=; b=N4LUSf86BH3Z+aE9XkGsoli6kAOZM/Ms3cttb7oQXIioMhsNhGYjWq0qdnEfzmgogH ew5d1FAt2C2P6H9L9ON+IOBmbhlMKE03Gvode+f9mbxYXPINgSrHqpNgtI2e2rTuPqhB ygfiPsopRaneY19Lj8Fo0LVWt3bgESknvqHpA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=ejjDconYxCq2KTpAv7XZnQ3pGEuUQS9qNCRR4UaQbW4=; b=uD7si45FTyDf3LSuUuvD+CaGRIEdxFZs3hRn2JwTVDxGB8UKZpfje8DOZRQ5rFdXOK pEV/8ojt4mhebvMmThPanMws5mqcG0z7QFpQfKwWjgE053EbCDB+i7kEeVtr/6l/zgHK XbaJjDdW3xK91cEUAqbdwBNGRxOOAl7QuGkC5egLcszH2AHSeNJm4L39ESUpM/OQZEJR 5e3edy7Pv2Czgjwm2UxRJ61MPxXQxehoSqwHPSjtG54ixwPbAAGiMB0nLb2xp43PGolu QyLepgM6hN3pEhPHIC/S+3FAyRuvN2QqG+KcuRxkza7rzuwbCarQH/DbImlmrmFgsP2I gG1w== X-Gm-Message-State: AElRT7HOJA57zMD9xYW7hyvTD91i/utROuN8oCHcFHQC0X5mG4Y6sRWQ FlTaABTCpAlkZMlNScix1fi3AV8Xkkp5SvHeDvu5TIr8 X-Google-Smtp-Source: AIpwx49ZuNiBDNMSLpAVxniw4G/MYrZ5yB6zbuPKLwoP5AhwDlyMX5H/Q2FVArU9mlFX7M0ruRTXiOxS7bEn2ReUIrI= X-Received: by 2002:a24:30c:: with SMTP id e12-v6mr3493600ite.50.1522424046449; Fri, 30 Mar 2018 08:34:06 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.187.67 with HTTP; Fri, 30 Mar 2018 08:34:05 -0700 (PDT) In-Reply-To: <1521594198-52523-11-git-send-email-heyi.guo@linaro.org> References: <1521594198-52523-1-git-send-email-heyi.guo@linaro.org> <1521594198-52523-11-git-send-email-heyi.guo@linaro.org> From: Ard Biesheuvel Date: Fri, 30 Mar 2018 16:34:05 +0100 Message-ID: To: Heyi Guo Cc: "edk2-devel@lists.01.org" , Leif Lindholm , Michael D Kinney , Haojian Zhuang Subject: Re: [PATCH edk2-platforms 10/12] Hisilicon/D0x: Switch to generic PciHostBridge driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 30 Mar 2018 15:34:07 -0000 Content-Type: text/plain; charset="UTF-8" On 21 March 2018 at 01:03, Heyi Guo wrote: > Address translation support is added to generic PciHostBridge driver > in edk2 by commit 74d0a33, so we can switch to it for Hisilicon D03 > and D05 which are using address translation between device address and > host address for resource BAR. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Heyi Guo > Cc: Ard Biesheuvel > Cc: Leif Lindholm > Cc: Michael D Kinney > Cc: Haojian Zhuang > --- > Silicon/Hisilicon/Hisilicon.dsc.inc | 6 +++++- > Platform/Hisilicon/D03/D03.dsc | 6 ++++-- > Platform/Hisilicon/D05/D05.dsc | 6 ++++-- > Platform/Hisilicon/D03/D03.fdf | 3 ++- > Platform/Hisilicon/D05/D05.fdf | 3 ++- > 5 files changed, 17 insertions(+), 7 deletions(-) > > diff --git a/Silicon/Hisilicon/Hisilicon.dsc.inc b/Silicon/Hisilicon/Hisilicon.dsc.inc > index 77585933179e..8ee74a830e74 100644 > --- a/Silicon/Hisilicon/Hisilicon.dsc.inc > +++ b/Silicon/Hisilicon/Hisilicon.dsc.inc > @@ -253,7 +253,11 @@ [PcdsFeatureFlag.common] > > [PcdsFixedAtBuild.common] > gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|44 > - gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|0 > + # > + # IO is mapped to memory space, so we use the same size of > + # PcdPrePiCpuMemorySize > + # > + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|44 As noted in reply to the previous patches, I think we should avoid 1:1 mapping the I/O space like this. 20 bits of I/O space should be plenty, i.e., up to 16 segments using 64 KB of I/O space each. > gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000 > gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000 > gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000 > diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc > index 0b2bd29cdf83..26081a33a00a 100644 > --- a/Platform/Hisilicon/D03/D03.dsc > +++ b/Platform/Hisilicon/D03/D03.dsc > @@ -82,6 +82,8 @@ [LibraryClasses.common] > > LpcLib|Silicon/Hisilicon/Hi1610/Library/LpcLib/LpcLib.inf > SerialPortLib|Silicon/Hisilicon/Hi1610/Library/Uart/LpcSerialPortLib/LpcSerialPortLib.inf > + PciHostBridgeLib|Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.inf > + PciSegmentLib|Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/Hi161xPciSegmentLib.inf > > ## GIC on D02/D03 is not fully ARM GIC compatible: IRQ cannot be cancelled when > ## input signal is de-asserted, except for virtual timer interrupt IRQ #27. > @@ -336,6 +338,7 @@ [Components.common] > ArmPkg/Drivers/CpuDxe/CpuDxe.inf > MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf > > + Silicon/Hisilicon/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf > Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf > > Platform/Hisilicon/D03/Drivers/SFC/SfcDxeDriver.inf > @@ -457,9 +460,8 @@ [Components.common] > > NULL|Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf > } > - Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf { > + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { > > - DmaLib|EmbeddedPkg/Library/NonCoherentDmaLib/NonCoherentDmaLib.inf > NULL|Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.inf > } > > diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc > index 2150a6f4c0e9..d6febf471630 100644 > --- a/Platform/Hisilicon/D05/D05.dsc > +++ b/Platform/Hisilicon/D05/D05.dsc > @@ -97,6 +97,8 @@ [LibraryClasses.common] > > LpcLib|Silicon/Hisilicon/Hi1610/Library/LpcLib/LpcLib.inf > SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf > + PciHostBridgeLib|Platform/Hisilicon/Library/PciHostBridgeLib/PciHostBridgeLib.inf > + PciSegmentLib|Silicon/Hisilicon/Hi1610/Library/Hi161xPciSegmentLib/Hi161xPciSegmentLib.inf > > [LibraryClasses.common.SEC] > ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf > @@ -472,6 +474,7 @@ [Components.common] > ArmPkg/Drivers/CpuDxe/CpuDxe.inf > MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf > > + Silicon/Hisilicon/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf > Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf > > Platform/Hisilicon/D05/Drivers/SFC/SfcDxeDriver.inf > @@ -611,9 +614,8 @@ [Components.common] > > NULL|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf > } > - Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf { > + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { > > - DmaLib|EmbeddedPkg/Library/CoherentDmaLib/CoherentDmaLib.inf > NULL|Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf > } > > diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf > index e430d5c08982..0c843a3ce671 100644 > --- a/Platform/Hisilicon/D03/D03.fdf > +++ b/Platform/Hisilicon/D03/D03.fdf > @@ -157,6 +157,7 @@ [FV.FvMain] > INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf > > INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf > + INF Silicon/Hisilicon/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf > INF Platform/Hisilicon/D03/Drivers/SFC/SfcDxeDriver.inf > > INF Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf > @@ -263,7 +264,7 @@ [FV.FvMain] > # PCI Support > # > INF Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf > - INF Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf > + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf > INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > > INF Platform/Hisilicon/D03/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf > diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf > index 13a60837a607..b530e8e785a4 100644 > --- a/Platform/Hisilicon/D05/D05.fdf > +++ b/Platform/Hisilicon/D05/D05.fdf > @@ -161,6 +161,7 @@ [FV.FvMain] > INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf > > INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf > + INF Silicon/Hisilicon/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf > INF Platform/Hisilicon/D05/Drivers/SFC/SfcDxeDriver.inf > > INF Platform/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf > @@ -285,7 +286,7 @@ [FV.FvMain] > # PCI Support > # > INF Silicon/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf > - INF Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf > + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf > INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > > INF Platform/Hisilicon/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf > -- > 2.7.4 >